381 lines
8.7 KiB
C
381 lines
8.7 KiB
C
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/* $OpenBSD: igc_hw.h,v 1.2 2022/05/11 06:14:15 kevlo Exp $ */
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/*-
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* Copyright 2021 Intel Corp
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* Copyright 2021 Rubicon Communications, LLC (Netgate)
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* $FreeBSD$
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*/
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#ifndef _IGC_HW_H_
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#define _IGC_HW_H_
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#include "bpfilter.h"
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#include "vlan.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/sockio.h>
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#include <sys/mbuf.h>
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#include <sys/malloc.h>
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#include <sys/kernel.h>
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#include <sys/socket.h>
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#include <sys/device.h>
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#include <sys/endian.h>
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#include <sys/intrmap.h>
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#include <net/if.h>
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#include <net/if_media.h>
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#include <net/toeplitz.h>
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#include <netinet/in.h>
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#include <netinet/if_ether.h>
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#if NBPFILTER > 0
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#include <net/bpf.h>
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#endif
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/pci/igc_base.h>
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#include <dev/pci/igc_defines.h>
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#include <dev/pci/igc_i225.h>
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#include <dev/pci/igc_mac.h>
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#include <dev/pci/igc_nvm.h>
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#include <dev/pci/igc_phy.h>
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#include <dev/pci/igc_regs.h>
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struct igc_hw;
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#define IGC_FUNC_1 1
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#define IGC_ALT_MAC_ADDRESS_OFFSET_LAN0 0
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#define IGC_ALT_MAC_ADDRESS_OFFSET_LAN1 3
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enum igc_mac_type {
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igc_undefined = 0,
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igc_i225,
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igc_num_macs /* List is 1-based, so subtract 1 for TRUE count. */
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};
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enum igc_media_type {
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igc_media_type_unknown = 0,
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igc_media_type_copper = 1,
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igc_num_media_types
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};
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enum igc_nvm_type {
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igc_nvm_unknown = 0,
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igc_nvm_eeprom_spi,
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igc_nvm_flash_hw,
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igc_nvm_invm
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};
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enum igc_phy_type {
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igc_phy_unknown = 0,
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igc_phy_none,
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igc_phy_i225
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};
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enum igc_bus_type {
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igc_bus_type_unknown = 0,
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igc_bus_type_pci,
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igc_bus_type_pcix,
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igc_bus_type_pci_express,
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igc_bus_type_reserved
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};
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enum igc_bus_speed {
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igc_bus_speed_unknown = 0,
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igc_bus_speed_33,
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igc_bus_speed_66,
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igc_bus_speed_100,
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igc_bus_speed_120,
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igc_bus_speed_133,
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igc_bus_speed_2500,
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igc_bus_speed_5000,
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igc_bus_speed_reserved
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};
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enum igc_bus_width {
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igc_bus_width_unknown = 0,
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igc_bus_width_pcie_x1,
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igc_bus_width_pcie_x2,
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igc_bus_width_pcie_x4 = 4,
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igc_bus_width_pcie_x8 = 8,
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igc_bus_width_32,
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igc_bus_width_64,
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igc_bus_width_reserved
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};
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enum igc_fc_mode {
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igc_fc_none = 0,
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igc_fc_rx_pause,
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igc_fc_tx_pause,
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igc_fc_full,
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igc_fc_default = 0xFF
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};
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enum igc_ms_type {
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igc_ms_hw_default = 0,
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igc_ms_force_master,
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igc_ms_force_slave,
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igc_ms_auto
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};
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enum igc_smart_speed {
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igc_smart_speed_default = 0,
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igc_smart_speed_on,
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igc_smart_speed_off
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};
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/* Receive Descriptor */
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struct igc_rx_desc {
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uint64_t buffer_addr; /* Address of the descriptor's data buffer */
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uint64_t length; /* Length of data DMAed into data buffer */
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uint16_t csum; /* Packet checksum */
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uint8_t status; /* Descriptor status */
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uint8_t errors; /* Descriptor errors */
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uint16_t special;
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};
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/* Receive Descriptor - Extended */
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union igc_rx_desc_extended {
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struct {
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uint64_t buffer_addr;
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uint64_t reserved;
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} read;
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struct {
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struct {
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uint32_t mrq; /* Multiple Rx queues */
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union {
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uint32_t rss; /* RSS hash */
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struct {
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uint16_t ip_id; /* IP id */
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uint16_t csum; /* Packet checksum */
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} csum_ip;
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} hi_dword;
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} lower;
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struct {
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uint32_t status_error; /* ext status/error */
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uint16_t length;
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uint16_t vlan; /* VLAN tag */
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} upper;
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} wb; /* writeback */
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};
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/* Transmit Descriptor */
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struct igc_tx_desc {
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uint64_t buffer_addr; /* Address of the descriptor's data buffer */
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union {
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uint32_t data;
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struct {
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uint16_t length; /* Data buffer length */
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uint8_t cso; /* Checksum offset */
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uint8_t cmd; /* Descriptor control */
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} flags;
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} lower;
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union {
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uint32_t data;
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struct {
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uint8_t status; /* Descriptor status */
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uint8_t css; /* Checksum start */
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uint16_t special;
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} fields;
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} upper;
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};
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/* Function pointers for the MAC. */
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struct igc_mac_operations {
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int (*init_params)(struct igc_hw *);
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int (*check_for_link)(struct igc_hw *);
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void (*clear_hw_cntrs)(struct igc_hw *);
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void (*clear_vfta)(struct igc_hw *);
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int (*get_bus_info)(struct igc_hw *);
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void (*set_lan_id)(struct igc_hw *);
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int (*get_link_up_info)(struct igc_hw *, uint16_t *, uint16_t *);
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void (*update_mc_addr_list)(struct igc_hw *, uint8_t *, uint32_t);
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int (*reset_hw)(struct igc_hw *);
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int (*init_hw)(struct igc_hw *);
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int (*setup_link)(struct igc_hw *);
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int (*setup_physical_interface)(struct igc_hw *);
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void (*write_vfta)(struct igc_hw *, uint32_t, uint32_t);
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void (*config_collision_dist)(struct igc_hw *);
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int (*rar_set)(struct igc_hw *, uint8_t *, uint32_t);
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int (*read_mac_addr)(struct igc_hw *);
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int (*validate_mdi_setting)(struct igc_hw *);
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int (*acquire_swfw_sync)(struct igc_hw *, uint16_t);
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void (*release_swfw_sync)(struct igc_hw *, uint16_t);
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};
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/* When to use various PHY register access functions:
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*
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* Func Caller
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* Function Does Does When to use
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* ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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* X_reg L,P,A n/a for simple PHY reg accesses
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* X_reg_locked P,A L for multiple accesses of different regs
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* on different pages
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* X_reg_page A L,P for multiple accesses of different regs
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* on the same page
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*
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* Where X=[read|write], L=locking, P=sets page, A=register access
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*
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*/
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struct igc_phy_operations {
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int (*init_params)(struct igc_hw *);
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int (*acquire)(struct igc_hw *);
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int (*check_reset_block)(struct igc_hw *);
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int (*force_speed_duplex)(struct igc_hw *);
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int (*get_info)(struct igc_hw *);
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int (*set_page)(struct igc_hw *, uint16_t);
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int (*read_reg)(struct igc_hw *, uint32_t, uint16_t *);
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int (*read_reg_locked)(struct igc_hw *, uint32_t, uint16_t *);
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int (*read_reg_page)(struct igc_hw *, uint32_t, uint16_t *);
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void (*release)(struct igc_hw *);
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int (*reset)(struct igc_hw *);
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int (*set_d0_lplu_state)(struct igc_hw *, bool);
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int (*set_d3_lplu_state)(struct igc_hw *, bool);
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int (*write_reg)(struct igc_hw *, uint32_t, uint16_t);
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int (*write_reg_locked)(struct igc_hw *, uint32_t, uint16_t);
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int (*write_reg_page)(struct igc_hw *, uint32_t, uint16_t);
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void (*power_up)(struct igc_hw *);
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void (*power_down)(struct igc_hw *);
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};
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/* Function pointers for the NVM. */
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struct igc_nvm_operations {
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int (*init_params)(struct igc_hw *);
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int (*acquire)(struct igc_hw *);
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int (*read)(struct igc_hw *, uint16_t, uint16_t, uint16_t *);
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void (*release)(struct igc_hw *);
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void (*reload)(struct igc_hw *);
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int (*update)(struct igc_hw *);
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int (*validate)(struct igc_hw *);
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int (*write)(struct igc_hw *, uint16_t, uint16_t, uint16_t *);
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};
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struct igc_info {
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int (*get_invariants)(struct igc_hw *hw);
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struct igc_mac_operations *mac_ops;
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const struct igc_phy_operations *phy_ops;
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struct igc_nvm_operations *nvm_ops;
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};
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extern const struct igc_info igc_i225_info;
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struct igc_mac_info {
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struct igc_mac_operations ops;
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uint8_t addr[ETHER_ADDR_LEN];
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uint8_t perm_addr[ETHER_ADDR_LEN];
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enum igc_mac_type type;
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uint32_t mc_filter_type;
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uint16_t current_ifs_val;
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uint16_t ifs_max_val;
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uint16_t ifs_min_val;
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uint16_t ifs_ratio;
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uint16_t ifs_step_size;
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uint16_t mta_reg_count;
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uint16_t uta_reg_count;
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/* Maximum size of the MTA register table in all supported adapters */
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#define MAX_MTA_REG 128
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uint32_t mta_shadow[MAX_MTA_REG];
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uint16_t rar_entry_count;
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uint8_t forced_speed_duplex;
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bool asf_firmware_present;
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bool autoneg;
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bool get_link_status;
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uint32_t max_frame_size;
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};
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struct igc_phy_info {
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struct igc_phy_operations ops;
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enum igc_phy_type type;
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enum igc_smart_speed smart_speed;
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uint32_t addr;
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uint32_t id;
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uint32_t reset_delay_us; /* in usec */
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uint32_t revision;
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enum igc_media_type media_type;
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uint16_t autoneg_advertised;
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uint16_t autoneg_mask;
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uint8_t mdix;
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bool polarity_correction;
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bool speed_downgraded;
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bool autoneg_wait_to_complete;
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};
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struct igc_nvm_info {
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struct igc_nvm_operations ops;
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enum igc_nvm_type type;
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uint16_t word_size;
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uint16_t delay_usec;
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uint16_t address_bits;
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uint16_t opcode_bits;
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uint16_t page_size;
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};
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struct igc_bus_info {
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enum igc_bus_type type;
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enum igc_bus_speed speed;
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enum igc_bus_width width;
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uint16_t func;
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uint16_t pci_cmd_word;
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};
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struct igc_fc_info {
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uint32_t high_water;
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uint32_t low_water;
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uint16_t pause_time;
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uint16_t refresh_time;
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bool send_xon;
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bool strict_ieee;
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enum igc_fc_mode current_mode;
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enum igc_fc_mode requested_mode;
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};
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struct igc_dev_spec_i225 {
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bool eee_disable;
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bool clear_semaphore_once;
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uint32_t mtu;
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};
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struct igc_hw {
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void *back;
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uint8_t *hw_addr;
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struct igc_mac_info mac;
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struct igc_fc_info fc;
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struct igc_phy_info phy;
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struct igc_nvm_info nvm;
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struct igc_bus_info bus;
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|
union {
|
||
|
|
struct igc_dev_spec_i225 _i225;
|
||
|
|
} dev_spec;
|
||
|
|
|
||
|
|
uint16_t device_id;
|
||
|
|
};
|
||
|
|
|
||
|
|
#endif /* _IGC_HW_H_ */
|