sync with OpenBSD -current

lib/libcrypto/objects/obj_dat.c

@@ -1,4 +1,4 @@
-/* $OpenBSD: obj_dat.c,v 1.89 2024/03/02 11:11:11 tb Exp $ */
+/* $OpenBSD: obj_dat.c,v 1.90 2024/05/08 16:35:05 tb Exp $ */
 /* Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
  * All rights reserved.
  *
@@ -167,7 +167,8 @@ cleanup1_doall(ADDED_OBJ *a)
 	    ASN1_OBJECT_FLAG_DYNAMIC_DATA;
 }
 
-static void cleanup2_doall(ADDED_OBJ *a)
+static void
+cleanup2_doall(ADDED_OBJ *a)
 {
 	a->obj->nid++;
 }

sys/arch/amd64/amd64/cacheinfo.c

@@ -1,4 +1,4 @@
-/*	$OpenBSD: cacheinfo.c,v 1.13 2024/04/03 02:01:21 guenther Exp $	*/
+/*	$OpenBSD: cacheinfo.c,v 1.14 2024/05/08 18:00:55 guenther Exp $	*/
 
 /*
  * Copyright (c) 2022 Jonathan Gray <jsg@openbsd.org>
@@ -22,17 +22,36 @@
 #include <machine/cpu.h>
 #include <machine/specialreg.h>
 
+#define MAX_CACHE_LEAF	10
+
+#ifdef MULTIPROCESSOR
+uint32_t prev_cache[MAX_CACHE_LEAF][3];
+# define prev_e5_ecx	prev_cache[0][0]
+# define prev_e5_edx	prev_cache[0][1]
+# define prev_e6_ecx	prev_cache[0][2]
+# define PREV_SET(x,y)	(x) = (y)
+# define PREV_SAME(x,y)	((x) == (y))
+#else
+# define PREV_SET(x,y)	(void)0
+# define PREV_SAME(x,y)	0
+#endif
+
 void
 amd64_print_l1_cacheinfo(struct cpu_info *ci)
 {
 	u_int ways, linesize, totalsize;
-	u_int eax, ebx, ecx, edx;
+	u_int dummy, ecx, edx;
 
-	if (ci->ci_pnfeatset < 0x80000006)
+	if (ci->ci_pnfeatset < 0x80000005)
 		return;
 
-	CPUID(0x80000005, eax, ebx, ecx, edx);
+	CPUID(0x80000005, dummy, dummy, ecx, edx);
 
+	if (!CPU_IS_PRIMARY(ci) && PREV_SAME(ecx, prev_e5_ecx) &&
+	    PREV_SAME(edx, prev_e5_edx))
+		return;
+	PREV_SET(prev_e5_ecx, ecx);
+	PREV_SET(prev_e5_edx, edx);
 	if (ecx == 0)
 		return;
 
@@ -91,13 +110,16 @@ void
 amd64_print_l2_cacheinfo(struct cpu_info *ci)
 {
 	u_int ways, linesize, totalsize;
-	u_int eax, ebx, ecx, edx;
+	u_int dummy, ecx;
 
 	if (ci->ci_pnfeatset < 0x80000006)
 		return;
 
-	CPUID(0x80000006, eax, ebx, ecx, edx);
+	CPUID(0x80000006, dummy, dummy, ecx, dummy);
 
+	if (!CPU_IS_PRIMARY(ci) && PREV_SAME(ecx, prev_e6_ecx))
+		return;
+	PREV_SET(prev_e6_ecx, ecx);
 	if (ecx == 0)
 		return;
 
@@ -157,20 +179,16 @@ amd64_print_l2_cacheinfo(struct cpu_info *ci)
 	printf(" L2 cache\n");
 }
 
-void
+static inline int
-intel_print_cacheinfo(struct cpu_info *ci, u_int fn)
+intel_print_one_cache(struct cpu_info *ci, int leaf, u_int eax, u_int ebx,
+    u_int ecx)
 {
 	u_int ways, partitions, linesize, sets, totalsize;
-	int type, level, leaf;
+	int type, level;
-	u_int eax, ebx, ecx, edx;
 
-	printf("%s: ", ci->ci_dev->dv_xname);
-
-	for (leaf = 0; leaf < 10; leaf++) {
-		CPUID_LEAF(fn, leaf, eax, ebx, ecx, edx);
 	type = eax & 0x1f;
 	if (type == 0)
-			break;
+		return 1;
 	level = (eax >> 5) & 7;
 
 	ways = (ebx >> 22) + 1;
@@ -180,7 +198,9 @@ intel_print_cacheinfo(struct cpu_info *ci, u_int fn)
 
 	totalsize = ways * linesize * partitions * sets;
 
-		if (leaf > 0)
+	if (leaf == 0)
+		printf("%s: ", ci->ci_dev->dv_xname);
+	else
 		printf(", ");
 
 	if (totalsize < 1024*1024)
@@ -200,7 +220,52 @@ intel_print_cacheinfo(struct cpu_info *ci, u_int fn)
 	} else {
 		printf("L%d cache", level);
 	}
+	return 0;
+}
 
+void
+intel_print_cacheinfo(struct cpu_info *ci, u_int fn)
+{
+	int leaf;
+	u_int eax, ebx, ecx, dummy;
+
+	leaf = 0;
+#ifdef MULTIPROCESSOR
+	if (! CPU_IS_PRIMARY(ci)) {
+		int i;
+		/* find the first level that differs, if any */
+		for (; leaf < MAX_CACHE_LEAF; leaf++) {
+			CPUID_LEAF(fn, leaf, eax, ebx, ecx, dummy);
+			if (PREV_SAME(prev_cache[leaf][0], eax) &&
+			    PREV_SAME(prev_cache[leaf][1], ebx) &&
+			    PREV_SAME(prev_cache[leaf][2], ecx)) {
+				/* last level? */
+				if ((eax & 0x1f) == 0)
+					break;
+				continue;
+			}
+			/* print lower levels that were the same */
+			for (i = 0; i < leaf; i++)
+				intel_print_one_cache(ci, i, prev_cache[leaf][0],
+				    prev_cache[leaf][1], prev_cache[leaf][2]);
+			/* print this (differing) level and higher levels */
+			goto printit;
+		}
+		/* same as previous */
+		return;
+	}
+#endif
+
+	for (; leaf < MAX_CACHE_LEAF; leaf++) {
+		CPUID_LEAF(fn, leaf, eax, ebx, ecx, dummy);
+#ifdef MULTIPROCESSOR
+printit:
+#endif
+		PREV_SET(prev_cache[leaf][0], eax);
+		PREV_SET(prev_cache[leaf][1], ebx);
+		PREV_SET(prev_cache[leaf][2], ecx);
+		if (intel_print_one_cache(ci, leaf, eax, ebx, ecx))
+			break;
 	}
 	printf("\n");
 }
@@ -218,7 +283,7 @@ x86_print_cacheinfo(struct cpu_info *ci)
 	}
 
 	if (ci->ci_vendor == CPUV_AMD &&
-	    (ecpu_ecxfeature & CPUIDECX_TOPEXT)) {
+	    (ci->ci_efeature_ecx & CPUIDECX_TOPEXT)) {
 		intel_print_cacheinfo(ci, 0x8000001d);
 		return;
 	}

sys/dev/pci/if_ixl.c

@@ -1,4 +1,4 @@
-/*	$OpenBSD: if_ixl.c,v 1.99 2024/05/07 18:35:23 jan Exp $ */
+/*	$OpenBSD: if_ixl.c,v 1.100 2024/05/08 17:52:11 jan Exp $ */
 
 /*
  * Copyright (c) 2013-2015, Intel Corporation
@@ -2854,7 +2854,11 @@ ixl_tx_setup_offload(struct mbuf *m0, struct ixl_tx_ring *txr,
 
 			hlen += ext.tcphlen;
 
-			outlen = m0->m_pkthdr.ph_mss;
+			/*
+			 * The MSS should not be set to a lower value than 64
+			 * or larger than 9668 bytes.
+			 */
+			outlen = MIN(9668, MAX(64, m0->m_pkthdr.ph_mss));
 			paylen = m0->m_pkthdr.len - ETHER_HDR_LEN - hlen;
 
 			ring = IXL_DMA_KVA(&txr->txr_mem);