sync with OpenBSD -current
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b9b2353a61
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a48b7fc94f
GPG Key ID:
F42C07F07E2E35B7
@ -1,153 +0,0 @@
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#!/usr/bin/env perl
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$0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
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push(@INC, "${dir}perlasm", "perlasm");
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require "x86asm.pl";
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&asm_init($ARGV[0],"x86cpuid");
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for (@ARGV) { $sse2=1 if (/-DOPENSSL_IA32_SSE2/); }
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&function_begin("OPENSSL_ia32_cpuid");
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&xor ("edx","edx");
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&pushf ();
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&pop ("eax");
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&mov ("ecx","eax");
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&xor ("eax",1<<21);
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&push ("eax");
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&popf ();
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&pushf ();
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&pop ("eax");
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&xor ("ecx","eax");
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&xor ("eax","eax");
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&bt ("ecx",21);
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&jnc (&label("nocpuid"));
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&cpuid ();
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&mov ("edi","eax"); # max value for standard query level
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&xor ("eax","eax");
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&cmp ("ebx",0x756e6547); # "Genu"
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&setne (&LB("eax"));
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&mov ("ebp","eax");
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&cmp ("edx",0x49656e69); # "ineI"
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&setne (&LB("eax"));
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&or ("ebp","eax");
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&cmp ("ecx",0x6c65746e); # "ntel"
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&setne (&LB("eax"));
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&or ("ebp","eax"); # 0 indicates Intel CPU
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&jz (&label("intel"));
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&cmp ("ebx",0x68747541); # "Auth"
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&setne (&LB("eax"));
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&mov ("esi","eax");
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&cmp ("edx",0x69746E65); # "enti"
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&setne (&LB("eax"));
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&or ("esi","eax");
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&cmp ("ecx",0x444D4163); # "cAMD"
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&setne (&LB("eax"));
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&or ("esi","eax"); # 0 indicates AMD CPU
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&jnz (&label("intel"));
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# AMD specific
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&mov ("eax",0x80000000);
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&cpuid ();
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&cmp ("eax",0x80000001);
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&jb (&label("intel"));
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&mov ("esi","eax");
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&mov ("eax",0x80000001);
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&cpuid ();
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&and ("ecx","\$IA32CAP_MASK1_AMD_XOP"); # isolate AMD XOP bit
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&or ("ecx",1); # make sure ecx is not zero
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&mov ("ebp","ecx");
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&cmp ("esi",0x80000008);
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&jb (&label("intel"));
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&mov ("eax",0x80000008);
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&cpuid ();
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&movz ("esi",&LB("ecx")); # number of cores - 1
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&inc ("esi"); # number of cores
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&mov ("eax",1);
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&xor ("ecx","ecx");
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&cpuid ();
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&bt ("edx","\$IA32CAP_BIT0_HT");
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&jnc (&label("generic"));
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&shr ("ebx",16);
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&and ("ebx",0xff);
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&cmp ("ebx","esi");
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&ja (&label("generic"));
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&xor ("edx","\$IA32CAP_MASK0_HT"); # clear hyper-threading bit
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&jmp (&label("generic"));
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&set_label("intel");
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&cmp ("edi",4);
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&mov ("edi",-1);
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&jb (&label("nocacheinfo"));
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&mov ("eax",4);
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&mov ("ecx",0); # query L1D
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&cpuid ();
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&mov ("edi","eax");
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&shr ("edi",14);
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&and ("edi",0xfff); # number of cores -1 per L1D
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&set_label("nocacheinfo");
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&mov ("eax",1);
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&xor ("ecx","ecx");
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&cpuid ();
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# force reserved bits to 0.
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&and ("edx","\$~(IA32CAP_MASK0_INTELP4 | IA32CAP_MASK0_INTEL)");
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&cmp ("ebp",0);
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&jne (&label("notintel"));
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# set reserved bit#30 on Intel CPUs
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&or ("edx","\$IA32CAP_MASK0_INTEL");
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&and (&HB("eax"),15); # family ID
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&cmp (&HB("eax"),15); # P4?
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&jne (&label("notintel"));
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# set reserved bit#20 to engage RC4_CHAR
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&or ("edx","\$IA32CAP_MASK0_INTELP4");
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&set_label("notintel");
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&bt ("edx","\$IA32CAP_BIT0_HT"); # test hyper-threading bit
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&jnc (&label("generic"));
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&xor ("edx","\$IA32CAP_MASK0_HT");
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&cmp ("edi",0);
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&je (&label("generic"));
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&or ("edx","\$IA32CAP_MASK0_HT");
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&shr ("ebx",16);
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&cmp (&LB("ebx"),1); # see if cache is shared
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&ja (&label("generic"));
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&xor ("edx","\$IA32CAP_MASK0_HT"); # clear hyper-threading bit if not
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&set_label("generic");
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&and ("ebp","\$IA32CAP_MASK1_AMD_XOP"); # isolate AMD XOP flag
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# force reserved bits to 0.
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&and ("ecx","\$~IA32CAP_MASK1_AMD_XOP");
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&mov ("esi","edx");
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&or ("ebp","ecx"); # merge AMD XOP flag
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&bt ("ecx","\$IA32CAP_BIT1_OSXSAVE"); # check OSXSAVE bit
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&jnc (&label("clear_avx"));
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&xor ("ecx","ecx");
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&data_byte(0x0f,0x01,0xd0); # xgetbv
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&and ("eax",6);
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&cmp ("eax",6);
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&je (&label("done"));
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&cmp ("eax",2);
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&je (&label("clear_avx"));
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&set_label("clear_xmm");
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# clear AESNI and PCLMULQDQ bits.
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&and ("ebp","\$~(IA32CAP_MASK1_AESNI | IA32CAP_MASK1_PCLMUL)");
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# clear FXSR.
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&and ("esi","\$~IA32CAP_MASK0_FXSR");
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&set_label("clear_avx");
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# clear AVX, FMA3 and AMD XOP bits.
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&and ("ebp","\$~(IA32CAP_MASK1_AVX | IA32CAP_MASK1_FMA3 | IA32CAP_MASK1_AMD_XOP)");
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&set_label("done");
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&mov ("eax","esi");
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&mov ("edx","ebp");
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&set_label("nocpuid");
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&function_end("OPENSSL_ia32_cpuid");
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&asm_finish();
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@ -1,4 +1,4 @@
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/* $OpenBSD: sdhc_pci.c,v 1.26 2024/03/29 02:36:49 jsg Exp $ */
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/* $OpenBSD: sdhc_pci.c,v 1.27 2024/10/19 21:10:22 hastings Exp $ */
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/*
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* Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
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@ -126,16 +126,6 @@ sdhc_pci_attach(struct device *parent, struct device *self, void *aux)
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PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ENE_SDCARD)
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sc->sc.sc_flags |= SDHC_F_NOPWR0;
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/* Some Intel controllers break if set to 0V bus power. */
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if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL &&
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(PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_100SERIES_LP_EMMC ||
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PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_APOLLOLAKE_EMMC ||
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PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_GLK_EMMC ||
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PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_JSL_EMMC ||
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PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_EHL_EMMC ||
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PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_ADL_N_EMMC))
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sc->sc.sc_flags |= SDHC_F_NOPWR0;
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/* Some RICOH controllers need to be bumped into the right mode. */
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if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_RICOH &&
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(PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_RICOH_R5U822 ||
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@ -1,4 +1,4 @@
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/* $OpenBSD: sdhc.c,v 1.77 2024/08/06 15:03:36 patrick Exp $ */
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/* $OpenBSD: sdhc.c,v 1.78 2024/10/19 21:10:03 hastings Exp $ */
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/*
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* Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
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@ -591,14 +591,9 @@ sdhc_bus_power(sdmmc_chipset_handle_t sch, u_int32_t ocr)
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s = splsdmmc();
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/*
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* Disable bus power before voltage change.
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*/
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if (!(hp->sc->sc_flags & SDHC_F_NOPWR0))
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HWRITE1(hp, SDHC_POWER_CTL, 0);
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/* If power is disabled, reset the host and return now. */
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if (ocr == 0) {
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HWRITE1(hp, SDHC_POWER_CTL, 0);
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splx(s);
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(void)sdhc_host_reset(hp);
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return 0;
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@ -620,6 +615,21 @@ sdhc_bus_power(sdmmc_chipset_handle_t sch, u_int32_t ocr)
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return EINVAL;
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}
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/*
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* Return if no change to powered bus voltage.
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*/
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if (HREAD1(hp, SDHC_POWER_CTL) ==
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((vdd << SDHC_VOLTAGE_SHIFT) | SDHC_BUS_POWER)) {
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splx(s);
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return 0;
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}
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/*
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* Disable bus power before voltage change.
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*/
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if (!(hp->sc->sc_flags & SDHC_F_NOPWR0))
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HWRITE1(hp, SDHC_POWER_CTL, 0);
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/*
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* Enable bus power. Wait at least 1 ms (or 74 clocks) plus
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* voltage ramp until power rises.
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