sync with OpenBSD -current

This commit is contained in:
purplerain 2024-03-07 20:42:49 +00:00
parent f4dadbf64a
commit be37d2a32b
Signed by: purplerain
GPG Key ID: F42C07F07E2E35B7
13 changed files with 143 additions and 28 deletions

View File

@ -1,4 +1,4 @@
.\" $OpenBSD: sh.1,v 1.157 2023/05/13 18:34:49 jmc Exp $
.\" $OpenBSD: sh.1,v 1.158 2024/03/06 06:26:22 jmc Exp $
.\"
.\" Copyright (c) 2015 Jason McIntyre <jmc@openbsd.org>
.\"
@ -14,7 +14,7 @@
.\" ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
.\" OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
.\"
.Dd $Mdocdate: May 13 2023 $
.Dd $Mdocdate: March 6 2024 $
.Dt SH 1
.Os
.Sh NAME
@ -2140,7 +2140,7 @@ before each command is traced
option).
The default is
.Sq +\ \& .
.It PWD
.It Ev PWD
The absolute pathname to the current working directory.
.El
.Sh ASYNCHRONOUS EVENTS

View File

@ -1,4 +1,4 @@
.\" $OpenBSD: inet_addr.3,v 1.6 2022/09/11 06:38:10 jmc Exp $
.\" $OpenBSD: inet_addr.3,v 1.7 2024/03/06 07:29:37 bentley Exp $
.\" $NetBSD: inet.3,v 1.7 1997/06/18 02:25:24 lukem Exp $
.\"
.\" Copyright (c) 1983, 1990, 1991, 1993
@ -30,7 +30,7 @@
.\"
.\" @(#)inet.3 8.1 (Berkeley) 6/4/93
.\"
.Dd $Mdocdate: September 11 2022 $
.Dd $Mdocdate: March 6 2024 $
.Dt INET_ADDR 3
.Os
.Sh NAME
@ -154,7 +154,7 @@ otherwise, the number is interpreted as decimal).
The
.Nm inet_addr
and
.Nm inet_aton
.Nm inet_ntoa
functions conform to
.St -p1003.1-2008 .
.Sh HISTORY

View File

@ -1,4 +1,4 @@
.\" $OpenBSD: X509_STORE_load_locations.3,v 1.10 2021/11/12 14:05:28 schwarze Exp $
.\" $OpenBSD: X509_STORE_load_locations.3,v 1.11 2024/03/06 10:07:47 tb Exp $
.\" full merge up to:
.\" OpenSSL X509_STORE_add_cert b0edda11 Mar 20 13:00:17 2018 +0000
.\"
@ -16,7 +16,7 @@
.\" ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
.\" OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
.\"
.Dd $Mdocdate: November 12 2021 $
.Dd $Mdocdate: March 6 2024 $
.Dt X509_STORE_LOAD_LOCATIONS 3
.Os
.Sh NAME
@ -122,7 +122,7 @@ already contains an
.Vt X509_LOOKUP
object using the given
.Fa method ;
if it does, no action occurs.
if it does, the existing object is returned and no other action occurs.
Otherwise, a new
.Vt X509_LOOKUP
object is allocated, added, and returned.
@ -148,6 +148,7 @@ In particular, parse errors or lack of memory can cause failure.
returns the existing or new lookup object or
.Dv NULL
on failure.
This is an internal pointer that must not be freed.
With LibreSSL, the only reason for failure is lack of memory.
.Sh FILES
.Bl -tag -width Ds

View File

@ -1,4 +1,4 @@
/* $OpenBSD: rkclock.c,v 1.86 2024/03/02 19:48:13 kettenis Exp $ */
/* $OpenBSD: rkclock.c,v 1.87 2024/03/06 14:55:22 kettenis Exp $ */
/*
* Copyright (c) 2017, 2018 Mark Kettenis <kettenis@openbsd.org>
*
@ -1043,6 +1043,21 @@ const struct rkclock rk3308_clocks[] = {
SEL(15, 14), DIV(6, 0),
{ RK3308_PLL_DPLL, RK3308_PLL_VPLL0, RK3308_XIN24M }
},
{
RK3308_CLK_SPI0, RK3308_CRU_CLKSEL_CON(30),
SEL(15, 14), DIV(6, 0),
{ RK3308_PLL_DPLL, RK3308_PLL_VPLL0, RK3308_XIN24M }
},
{
RK3308_CLK_SPI1, RK3308_CRU_CLKSEL_CON(31),
SEL(15, 14), DIV(6, 0),
{ RK3308_PLL_DPLL, RK3308_PLL_VPLL0, RK3308_XIN24M }
},
{
RK3308_CLK_SPI2, RK3308_CRU_CLKSEL_CON(32),
SEL(15, 14), DIV(6, 0),
{ RK3308_PLL_DPLL, RK3308_PLL_VPLL0, RK3308_XIN24M }
},
{
RK3308_CLK_TSADC, RK3308_CRU_CLKSEL_CON(33),
0, DIV(10, 0),
@ -1531,6 +1546,11 @@ const struct rkclock rk3328_clocks[] = {
SEL(15, 14), DIV(13, 0),
{ RK3328_PLL_CPLL, RK3328_PLL_GPLL, RK3328_XIN24M }
},
{
RK3328_CLK_SPI, RK3328_CRU_CLKSEL_CON(24),
SEL(7, 7), DIV(6, 0),
{ RK3328_PLL_CPLL, RK3328_PLL_GPLL }
},
{
RK3328_CLK_SDMMC, RK3328_CRU_CLKSEL_CON(30),
SEL(9, 8), DIV(7, 0),
@ -2256,6 +2276,31 @@ const struct rkclock rk3399_clocks[] = {
SEL(15, 15), DIV(14, 8),
{ RK3399_PLL_CPLL, RK3399_PLL_GPLL }
},
{
RK3399_CLK_SPI0, RK3399_CRU_CLKSEL_CON(59),
SEL(7, 7), DIV(6, 0),
{ RK3399_PLL_CPLL, RK3399_PLL_GPLL }
},
{
RK3399_CLK_SPI1, RK3399_CRU_CLKSEL_CON(59),
SEL(15, 15), DIV(14, 8),
{ RK3399_PLL_CPLL, RK3399_PLL_GPLL }
},
{
RK3399_CLK_SPI2, RK3399_CRU_CLKSEL_CON(60),
SEL(7, 7), DIV(6, 0),
{ RK3399_PLL_CPLL, RK3399_PLL_GPLL }
},
{
RK3399_CLK_SPI4, RK3399_CRU_CLKSEL_CON(60),
SEL(15, 15), DIV(14, 8),
{ RK3399_PLL_CPLL, RK3399_PLL_GPLL }
},
{
RK3399_CLK_SPI5, RK3399_CRU_CLKSEL_CON(58),
SEL(15, 15), DIV(14, 8),
{ RK3399_PLL_CPLL, RK3399_PLL_GPLL }
},
{
RK3399_CLK_SDMMC, RK3399_CRU_CLKSEL_CON(16),
SEL(10, 8), DIV(6, 0),
@ -3284,6 +3329,26 @@ const struct rkclock rk3568_clocks[] = {
RK3568_CLK_I2C5, 0, 0, 0,
{ RK3568_CLK_I2C }
},
{
RK3568_CLK_SPI0, RK3568_CRU_CLKSEL_CON(72),
SEL(1, 0), 0,
{ RK3568_GPLL_200M, RK3568_XIN24M, RK3568_CPLL_100M }
},
{
RK3568_CLK_SPI1, RK3568_CRU_CLKSEL_CON(72),
SEL(3, 2), 0,
{ RK3568_GPLL_200M, RK3568_XIN24M, RK3568_CPLL_100M }
},
{
RK3568_CLK_SPI2, RK3568_CRU_CLKSEL_CON(72),
SEL(5, 4), 0,
{ RK3568_GPLL_200M, RK3568_XIN24M, RK3568_CPLL_100M }
},
{
RK3568_CLK_SPI3, RK3568_CRU_CLKSEL_CON(72),
SEL(7, 6), 0,
{ RK3568_GPLL_200M, RK3568_XIN24M, RK3568_CPLL_100M }
},
{
RK3568_SCLK_GMAC0, RK3568_CRU_CLKSEL_CON(31),
SEL(2, 2), 0,

View File

@ -57,6 +57,9 @@
#define RK3308_CLK_UART3 20
#define RK3308_CLK_UART4 21
#define RK3308_CLK_PWM0 26
#define RK3308_CLK_SPI0 27
#define RK3308_CLK_SPI1 28
#define RK3308_CLK_SPI2 29
#define RK3308_CLK_TSADC 36
#define RK3308_CLK_SARADC 37
#define RK3308_CLK_CRYPTO 41
@ -103,6 +106,7 @@
#define RK3328_ARMCLK 6
#define RK3328_CLK_RTC32K 30
#define RK3328_CLK_SPI 32
#define RK3328_CLK_SDMMC 33
#define RK3328_CLK_SDIO 34
#define RK3328_CLK_EMMC 35
@ -171,6 +175,11 @@
#define RK3399_CLK_I2C5 68
#define RK3399_CLK_I2C6 69
#define RK3399_CLK_I2C7 70
#define RK3399_CLK_SPI0 71
#define RK3399_CLK_SPI1 72
#define RK3399_CLK_SPI2 73
#define RK3399_CLK_SPI4 74
#define RK3399_CLK_SPI5 75
#define RK3399_CLK_SDMMC 76
#define RK3399_CLK_SDIO 77
#define RK3399_CLK_EMMC 78
@ -326,6 +335,10 @@
#define RK3568_CLK_I2C3 332
#define RK3568_CLK_I2C4 334
#define RK3568_CLK_I2C5 336
#define RK3568_CLK_SPI0 338
#define RK3568_CLK_SPI1 340
#define RK3568_CLK_SPI2 342
#define RK3568_CLK_SPI3 344
#define RK3568_SCLK_GMAC0 386
#define RK3568_SCLK_GMAC0_RGMII_SPEED 387
#define RK3568_SCLK_GMAC0_RMII_SPEED 388

View File

@ -1,4 +1,4 @@
/* $OpenBSD: sxiccmu.c,v 1.37 2024/03/04 04:11:52 deraadt Exp $ */
/* $OpenBSD: sxiccmu.c,v 1.38 2024/03/07 01:04:16 kevlo Exp $ */
/*
* Copyright (c) 2007,2009 Dale Rahn <drahn@openbsd.org>
* Copyright (c) 2013 Artturi Alm
@ -1265,12 +1265,15 @@ sxiccmu_a80_get_frequency(struct sxiccmu_softc *sc, uint32_t idx)
#define D1_RISCV_CLK_SEL_HOSC (0 << 24)
#define D1_RISCV_CLK_SEL_PLL_CPU (5 << 24)
#define D1_RISCV_DIV_CFG_FACTOR_M(x) (((x) >> 0) & 0x1f)
#define D1_PSI_CLK_REG 0x0510
#define D1_PSI_CLK_FACTOR_N(x) (((x) >> 8) & 0x3)
#define D1_PSI_CLK_FACTOR_M(x) (((x) >> 0) & 0x3)
uint32_t
sxiccmu_d1_get_frequency(struct sxiccmu_softc *sc, uint32_t idx)
{
uint32_t parent;
uint32_t reg;
uint32_t reg, freq;
uint32_t m, n;
switch (idx) {
@ -1301,6 +1304,13 @@ sxiccmu_d1_get_frequency(struct sxiccmu_softc *sc, uint32_t idx)
}
m = D1_RISCV_DIV_CFG_FACTOR_M(reg) + 1;
return sxiccmu_ccu_get_frequency(sc, &parent) / m;
case D1_CLK_PSI_AHB:
reg = SXIREAD4(sc, D1_PSI_CLK_REG);
/* assume PLL_PERIPH0 source */
freq = sxiccmu_d1_get_frequency(sc, D1_CLK_PLL_PERIPH0);
m = D1_PSI_CLK_FACTOR_M(reg) + 1;
n = 1 << D1_PSI_CLK_FACTOR_N(reg);
return freq / (m * n);
}
printf("%s: 0x%08x\n", __func__, idx);

View File

@ -364,6 +364,7 @@ const struct sxiccmu_ccu_bit sun9i_a80_mmc_gates[] = {
#define D1_CLK_PLL_CPU 0
#define D1_CLK_PLL_PERIPH0 5
#define D1_CLK_PSI_AHB 23
#define D1_CLK_APB1 25
#define D1_CLK_MMC0 56
#define D1_CLK_MMC1 57
@ -377,6 +378,7 @@ const struct sxiccmu_ccu_bit sun9i_a80_mmc_gates[] = {
#define D1_CLK_BUS_UART3 65
#define D1_CLK_BUS_UART4 66
#define D1_CLK_BUS_UART5 67
#define D1_CLK_BUS_EMAC 77
#define D1_CLK_USB_OHCI0 97
#define D1_CLK_USB_OHCI1 98
#define D1_CLK_BUS_OHCI0 99
@ -400,6 +402,7 @@ const struct sxiccmu_ccu_bit sun20i_d1_gates[] = {
[D1_CLK_BUS_UART3] = { 0x090c, 3, D1_CLK_APB1 },
[D1_CLK_BUS_UART4] = { 0x090c, 4, D1_CLK_APB1 },
[D1_CLK_BUS_UART5] = { 0x090c, 5, D1_CLK_APB1 },
[D1_CLK_BUS_EMAC] = { 0x097c, 0, D1_CLK_PSI_AHB },
[D1_CLK_USB_OHCI0] = { 0x0a70, 31 },
[D1_CLK_USB_OHCI1] = { 0x0a74, 31 },
[D1_CLK_BUS_OHCI0] = { 0x0a8c, 0 },
@ -989,6 +992,7 @@ const struct sxiccmu_ccu_bit sun9i_a80_mmc_resets[] = {
#define D1_RST_BUS_UART3 21
#define D1_RST_BUS_UART4 22
#define D1_RST_BUS_UART5 23
#define D1_RST_BUS_EMAC 30
#define D1_RST_USB_PHY0 40
#define D1_RST_USB_PHY1 41
#define D1_RST_BUS_OHCI0 42
@ -1006,6 +1010,7 @@ const struct sxiccmu_ccu_bit sun20i_d1_resets[] = {
[D1_RST_BUS_UART3] = { 0x090c, 19 },
[D1_RST_BUS_UART4] = { 0x090c, 20 },
[D1_RST_BUS_UART5] = { 0x090c, 21 },
[D1_RST_BUS_EMAC] = { 0x097c, 16 },
[D1_RST_USB_PHY0] = { 0x0a70, 30 },
[D1_RST_USB_PHY1] = { 0x0a74, 30 },
[D1_RST_BUS_OHCI0] = { 0x0a8c, 16 },

View File

@ -141,10 +141,6 @@ static const struct pci_matchid amdgpu_devices[] = {
{0x1002, 0x73AF },
{0x1002, 0x73BF },
/* Van Gogh */
{0x1002, 0x1435 }, /* Custom GPU 0932 */
{0x1002, 0x163F }, /* Custom GPU 0405 */
/* Yellow Carp */
{0x1002, 0x164D },
{0x1002, 0x1681 },
@ -197,6 +193,14 @@ static const struct pci_matchid amdgpu_devices[] = {
* display/dc/core/dc_resource.c resource_parse_asic_id()
*/
/* GC 9.4.3, APU/dGPU, "Aqua Vanjaram" */
{0x1002, 0x74a0 }, /* Instinct MI300A APU */
{0x1002, 0x74a1 }, /* Instinct MI300X dGPU */
/* GC 10.3.1, DCN 3.0.1, APU, "Van Gogh" */
{0x1002, 0x1435 }, /* Custom GPU 0932 */
{0x1002, 0x163f }, /* Custom GPU 0405 */
/* GC 10.3.6, DCN 3.1.5, APU, Ryzen 7000 "Raphael" */
{0x1002, 0x164e }, /* Radeon 610M */
@ -213,7 +217,7 @@ static const struct pci_matchid amdgpu_devices[] = {
/* GC 11.0.2, DCN 3.2.1, dGPU, "Navi 33" */
{0x1002, 0x7480 }, /* Radeon RX 7600S, 7700S, 7600M XT,
7600, Pro W7600 */
7600, 7600 XT, Pro W7600 */
{0x1002, 0x7483 }, /* Radeon RX 7600M */
{0x1002, 0x7489 }, /* Radeon Pro W7500 */
@ -225,4 +229,5 @@ static const struct pci_matchid amdgpu_devices[] = {
{0x1002, 0x15c8 }, /* Radeon 740M */
/* GC 11.5.0, DCN 3.5.0, APU, linux >= 6.7 */
/* GC 11.5.1, DCN 3.5.0, APU, linux >= 6.9 */
};

View File

@ -1,4 +1,4 @@
/* $OpenBSD: if_ix.c,v 1.209 2024/02/15 10:56:53 mglocker Exp $ */
/* $OpenBSD: if_ix.c,v 1.211 2024/03/07 17:09:02 jan Exp $ */
/******************************************************************************
@ -1932,7 +1932,9 @@ ixgbe_setup_interface(struct ix_softc *sc)
ifp->if_capabilities |= IFCAP_TSOv4 | IFCAP_TSOv6;
if (sc->hw.mac.type != ixgbe_mac_82598EB) {
#ifndef __sparc64__
ifp->if_xflags |= IFXF_LRO;
#endif
ifp->if_capabilities |= IFCAP_LRO;
}
@ -3174,10 +3176,10 @@ ixgbe_rxeof(struct rx_ring *rxr)
if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
if (rxbuf->fmp) {
m_freem(rxbuf->fmp);
rxbuf->fmp = NULL;
} else {
m_freem(mp);
}
m_freem(mp);
rxbuf->fmp = NULL;
rxbuf->buf = NULL;
goto next_desc;
}
@ -3224,6 +3226,8 @@ ixgbe_rxeof(struct rx_ring *rxr)
sendmp = mp;
sendmp->m_pkthdr.len = 0;
sendmp->m_pkthdr.ph_mss = 0;
} else {
mp->m_flags &= ~M_PKTHDR;
}
sendmp->m_pkthdr.len += mp->m_len;
/*

View File

@ -1,4 +1,4 @@
$OpenBSD: pcidevs,v 1.2067 2024/03/06 00:05:18 jsg Exp $
$OpenBSD: pcidevs,v 1.2068 2024/03/06 07:01:24 jsg Exp $
/* $NetBSD: pcidevs,v 1.30 1997/06/24 06:20:24 thorpej Exp $ */
/*
@ -2151,6 +2151,8 @@ product ATI NAVI32_2 0x747e Navi 32
product ATI NAVI33_1 0x7480 Navi 33
product ATI NAVI33_2 0x7483 Navi 33
product ATI NAVI33_3 0x7489 Navi 33
product ATI MI300A 0x74a0 MI300A
product ATI MI300X 0x74a1 MI300X
product ATI RADEON_9000IGP 0x7834 Radeon 9000/9100 IGP
product ATI RADEON_RS350IGP 0x7835 Radeon RS350IGP
product ATI RS690_HB 0x7910 RS690 Host

View File

@ -2,7 +2,7 @@
* THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* generated from:
* OpenBSD: pcidevs,v 1.2067 2024/03/06 00:05:18 jsg Exp
* OpenBSD: pcidevs,v 1.2068 2024/03/06 07:01:24 jsg Exp
*/
/* $NetBSD: pcidevs,v 1.30 1997/06/24 06:20:24 thorpej Exp $ */
@ -2156,6 +2156,8 @@
#define PCI_PRODUCT_ATI_NAVI33_1 0x7480 /* Navi 33 */
#define PCI_PRODUCT_ATI_NAVI33_2 0x7483 /* Navi 33 */
#define PCI_PRODUCT_ATI_NAVI33_3 0x7489 /* Navi 33 */
#define PCI_PRODUCT_ATI_MI300A 0x74a0 /* MI300A */
#define PCI_PRODUCT_ATI_MI300X 0x74a1 /* MI300X */
#define PCI_PRODUCT_ATI_RADEON_9000IGP 0x7834 /* Radeon 9000/9100 IGP */
#define PCI_PRODUCT_ATI_RADEON_RS350IGP 0x7835 /* Radeon RS350IGP */
#define PCI_PRODUCT_ATI_RS690_HB 0x7910 /* RS690 Host */

View File

@ -2,7 +2,7 @@
* THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* generated from:
* OpenBSD: pcidevs,v 1.2067 2024/03/06 00:05:18 jsg Exp
* OpenBSD: pcidevs,v 1.2068 2024/03/06 07:01:24 jsg Exp
*/
/* $NetBSD: pcidevs,v 1.30 1997/06/24 06:20:24 thorpej Exp $ */
@ -6743,6 +6743,14 @@ static const struct pci_known_product pci_known_products[] = {
PCI_VENDOR_ATI, PCI_PRODUCT_ATI_NAVI33_3,
"Navi 33",
},
{
PCI_VENDOR_ATI, PCI_PRODUCT_ATI_MI300A,
"MI300A",
},
{
PCI_VENDOR_ATI, PCI_PRODUCT_ATI_MI300X,
"MI300X",
},
{
PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_9000IGP,
"Radeon 9000/9100 IGP",

View File

@ -1,4 +1,4 @@
/* $OpenBSD: cmd-split-window.c,v 1.113 2022/06/07 10:02:19 nicm Exp $ */
/* $OpenBSD: cmd-split-window.c,v 1.114 2024/03/06 21:32:39 nicm Exp $ */
/*
* Copyright (c) 2009 Nicholas Marriott <nicholas.marriott@gmail.com>
@ -94,10 +94,10 @@ cmd_split_window_exec(struct cmd *self, struct cmdq_item *item)
size = -1;
if (args_has(args, 'l')) {
size = args_percentage_and_expand(args, 'l', 0, INT_MAX, curval,
item, &cause);
item, &cause);
} else if (args_has(args, 'p')) {
size = args_strtonum_and_expand(args, 'l', 0, 100, item,
&cause);
size = args_strtonum_and_expand(args, 'p', 0, 100, item,
&cause);
if (cause == NULL)
size = curval * size / 100;
}