sync with OpenBSD -current
This commit is contained in:
parent
d592c28c93
commit
c6ae013d06
GPG Key ID:
F42C07F07E2E35B7
@ -1842,6 +1842,7 @@
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./usr/share/man/man4/pppoe.4
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./usr/share/man/man4/pppx.4
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./usr/share/man/man4/psci.4
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./usr/share/man/man4/psp.4
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./usr/share/man/man4/pty.4
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./usr/share/man/man4/puc.4
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./usr/share/man/man4/pvbus.4
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@ -1,4 +1,4 @@
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/* $OpenBSD: cryptlib.c,v 1.53 2024/08/31 12:43:58 jsing Exp $ */
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/* $OpenBSD: cryptlib.c,v 1.54 2024/09/06 09:57:32 tb Exp $ */
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/* ====================================================================
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* Copyright (c) 1998-2006 The OpenSSL Project. All rights reserved.
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*
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@ -334,6 +334,12 @@ CRYPTO_THREADID_hash(const CRYPTO_THREADID *id)
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uint64_t OPENSSL_ia32cap_P;
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uint64_t
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crypto_cpu_caps_ia32(void)
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{
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return OPENSSL_ia32cap_P;
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}
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#if defined(OPENSSL_CPUID_OBJ) && !defined(OPENSSL_NO_ASM)
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#define OPENSSL_CPUID_SETUP
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void
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@ -352,6 +358,12 @@ OPENSSL_cpuid_setup(void)
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}
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#endif
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#else
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uint64_t
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crypto_cpu_caps_ia32(void)
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{
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return 0;
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}
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#endif
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#if !defined(OPENSSL_CPUID_SETUP) && !defined(OPENSSL_CPUID_OBJ)
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@ -1,4 +1,4 @@
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/* $OpenBSD: crypto_internal.h,v 1.11 2024/08/11 13:02:39 jsing Exp $ */
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/* $OpenBSD: crypto_internal.h,v 1.12 2024/09/06 09:57:32 tb Exp $ */
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/*
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* Copyright (c) 2023 Joel Sing <jsing@openbsd.org>
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*
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@ -220,4 +220,6 @@ crypto_ror_u64(uint64_t v, size_t shift)
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}
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#endif
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uint64_t crypto_cpu_caps_ia32(void);
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#endif
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@ -1,4 +1,4 @@
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/* $OpenBSD: e_aes.c,v 1.58 2024/04/09 13:52:41 beck Exp $ */
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/* $OpenBSD: e_aes.c,v 1.59 2024/09/06 09:57:32 tb Exp $ */
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/* ====================================================================
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* Copyright (c) 2001-2011 The OpenSSL Project. All rights reserved.
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*
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@ -55,6 +55,8 @@
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#include <openssl/opensslconf.h>
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#include "crypto_internal.h"
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#ifndef OPENSSL_NO_AES
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#include <openssl/aes.h>
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#include <openssl/err.h>
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@ -154,7 +156,7 @@ void AES_xts_decrypt(const char *inp, char *out, size_t len,
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#include "x86_arch.h"
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#ifdef VPAES_ASM
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#define VPAES_CAPABLE (OPENSSL_cpu_caps() & CPUCAP_MASK_SSSE3)
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#define VPAES_CAPABLE (crypto_cpu_caps_ia32() & CPUCAP_MASK_SSSE3)
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#endif
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#ifdef BSAES_ASM
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#define BSAES_CAPABLE VPAES_CAPABLE
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@ -162,7 +164,7 @@ void AES_xts_decrypt(const char *inp, char *out, size_t len,
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/*
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* AES-NI section
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*/
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#define AESNI_CAPABLE (OPENSSL_cpu_caps() & CPUCAP_MASK_AESNI)
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#define AESNI_CAPABLE (crypto_cpu_caps_ia32() & CPUCAP_MASK_AESNI)
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int aesni_set_encrypt_key(const unsigned char *userKey, int bits,
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AES_KEY *key);
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@ -1,4 +1,4 @@
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.\" $OpenBSD: X509_LOOKUP_new.3,v 1.11 2024/04/22 02:30:23 jsg Exp $
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.\" $OpenBSD: X509_LOOKUP_new.3,v 1.12 2024/09/06 07:48:20 tb Exp $
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.\"
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.\" Copyright (c) 2021 Ingo Schwarze <schwarze@openbsd.org>
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.\"
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@ -14,7 +14,7 @@
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.\" ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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.\" OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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.\"
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.Dd $Mdocdate: April 22 2024 $
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.Dd $Mdocdate: September 6 2024 $
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.Dt X509_LOOKUP_NEW 3
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.Os
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.Sh NAME
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@ -131,8 +131,6 @@ This lookup method is peculiar in so far as calling
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on a lookup object using it does not yet add any certificates to the associated
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.Vt X509_STORE
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object.
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They need to be added selectively using
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.Fn X509_LOOKUP_by_subject .
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.It Xr X509_LOOKUP_file 3
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The
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.Fa command
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@ -238,19 +236,6 @@ always ignores the
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.Fa ret
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argument.
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.Pp
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With LibreSSL,
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.Fn X509_LOOKUP_by_subject
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is only useful if
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.Fa lookup
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uses
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.Xr X509_LOOKUP_hash_dir 3 .
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It passes the
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.Fa name
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to
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.Xr X509_NAME_hash 3
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and converts the resulting hash to an eight-digit lower-case
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hexadecimal number.
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.Pp
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If the
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.Fa type
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is
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@ -284,28 +269,6 @@ returns 1 for success or 0 for failure.
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With library implementations other than LibreSSL,
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it might also return \-1 for internal errors.
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.Pp
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.Fn X509_LOOKUP_by_subject
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returns 1 for success or 0 for failure.
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In particular, it fails if
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.Fa lookup
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uses
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.Xr X509_LOOKUP_file 3
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or
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.Xr X509_LOOKUP_mem 3 ,
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if
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.Fa name
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is
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.Dv NULL ,
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if
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.Fa type
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is neither
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.Dv X509_LU_X509
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nor
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.Dv X509_LU_CRL ,
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if no match is found, or if memory allocation fails.
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With library implementations other than LibreSSL,
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it might also return negative values for internal errors.
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.Pp
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.Fn X509_get_default_cert_dir
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returns a pointer to the constant string
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.Qq /etc/ssl/certs ,
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@ -355,8 +318,7 @@ failed in
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was called with an invalid
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.Fa type .
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.It Dv ERR_R_BUF_LIB Qq "BUF lib"
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Memory allocation failed in
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.Fn X509_LOOKUP_by_subject .
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Memory allocation failed.
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.It Dv X509_R_INVALID_DIRECTORY Qq "invalid directory"
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The
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.Fa source
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@ -390,10 +352,7 @@ was called with
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and adding the certificates and revocation lists failed.
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This error is added after and in addition to a more specific diagnostic.
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.It Dv ERR_R_MALLOC_FAILURE Qq "malloc failure"
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Memory allocation failed in
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.Fn X509_LOOKUP_ctrl
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or
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.Fn X509_LOOKUP_by_subject .
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Memory allocation failed.
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.It Dv ERR_R_PEM_LIB Qq "PEM lib"
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.Xr PEM_X509_INFO_read_bio 3 ,
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.Xr PEM_read_bio_X509_AUX 3 ,
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@ -409,7 +368,7 @@ or
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failed in
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.Fn X509_LOOKUP_ctrl .
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.It Dv X509_R_WRONG_LOOKUP_TYPE Qq "wrong lookup type"
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.Fn X509_LOOKUP_by_subject
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.Xr X509_STORE_CTX_get_by_subject 3
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was called with an invalid
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.Fa type .
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.El
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@ -418,12 +377,6 @@ Passing an invalid
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.Fa command
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to
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.Fn X509_LOOKUP_ctrl
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or calling
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.Fn X509_LOOKUP_by_subject
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with a
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.Dv NULL
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.Fa name
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or with arguments that yield no match
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causes failure but provides no diagnostics.
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.Sh SEE ALSO
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.Xr d2i_X509_bio 3 ,
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@ -1,4 +1,4 @@
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/* $OpenBSD: gcm128.c,v 1.26 2023/08/10 07:18:43 jsing Exp $ */
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/* $OpenBSD: gcm128.c,v 1.27 2024/09/06 09:57:32 tb Exp $ */
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/* ====================================================================
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* Copyright (c) 2010 The OpenSSL Project. All rights reserved.
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*
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@ -50,10 +50,13 @@
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#define OPENSSL_FIPSAPI
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#include <openssl/crypto.h>
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#include "modes_local.h"
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#include <string.h>
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#include <openssl/crypto.h>
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#include "crypto_internal.h"
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#include "modes_local.h"
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#ifndef MODES_DEBUG
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# ifndef NDEBUG
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# define NDEBUG
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@ -660,7 +663,7 @@ CRYPTO_gcm128_init(GCM128_CONTEXT *ctx, void *key, block128_f block)
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# if defined(GHASH_ASM_X86_OR_64)
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# if !defined(GHASH_ASM_X86) || defined(OPENSSL_IA32_SSE2)
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/* check FXSR and PCLMULQDQ bits */
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if ((OPENSSL_cpu_caps() & (CPUCAP_MASK_FXSR | CPUCAP_MASK_PCLMUL)) ==
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if ((crypto_cpu_caps_ia32() & (CPUCAP_MASK_FXSR | CPUCAP_MASK_PCLMUL)) ==
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(CPUCAP_MASK_FXSR | CPUCAP_MASK_PCLMUL)) {
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gcm_init_clmul(ctx->Htable, ctx->H.u);
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ctx->gmult = gcm_gmult_clmul;
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@ -671,9 +674,9 @@ CRYPTO_gcm128_init(GCM128_CONTEXT *ctx, void *key, block128_f block)
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gcm_init_4bit(ctx->Htable, ctx->H.u);
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# if defined(GHASH_ASM_X86) /* x86 only */
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# if defined(OPENSSL_IA32_SSE2)
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if (OPENSSL_cpu_caps() & CPUCAP_MASK_SSE) { /* check SSE bit */
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if (crypto_cpu_caps_ia32() & CPUCAP_MASK_SSE) { /* check SSE bit */
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# else
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if (OPENSSL_cpu_caps() & CPUCAP_MASK_MMX) { /* check MMX bit */
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if (crypto_cpu_caps_ia32() & CPUCAP_MASK_MMX) { /* check MMX bit */
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# endif
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ctx->gmult = gcm_gmult_4bit_mmx;
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ctx->ghash = gcm_ghash_4bit_mmx;
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||||
@ -1,4 +1,4 @@
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||||
# $OpenBSD: tlsfuzzer.py,v 1.52 2023/08/14 18:10:42 tb Exp $
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# $OpenBSD: tlsfuzzer.py,v 1.53 2024/09/06 14:56:57 tb Exp $
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#
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# Copyright (c) 2020 Theo Buehler <tb@openbsd.org>
|
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#
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@ -352,7 +352,6 @@ tls12_tests = TestGroup("TLSv1.2 tests", [
|
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Test("test-cve-2016-2107.py"),
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Test("test-cve-2016-6309.py"),
|
||||
Test("test-dhe-rsa-key-exchange.py"),
|
||||
Test("test-dhe-rsa-key-exchange-with-bad-messages.py"),
|
||||
Test("test-early-application-data.py"),
|
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Test("test-empty-extensions.py"),
|
||||
Test("test-extensions.py"),
|
||||
@ -399,6 +398,10 @@ tls12_tests = TestGroup("TLSv1.2 tests", [
|
||||
"-e", "TLS_DHE_RSA_WITH_AES_256_CBC_SHA sha224 signature",
|
||||
]
|
||||
),
|
||||
Test("test-dhe-rsa-key-exchange-with-bad-messages.py", [
|
||||
"-x", "invalid dh_Yc value - missing",
|
||||
"-X", substitute_alert("decode_error", "illegal_parameter"),
|
||||
]),
|
||||
Test("test-dhe-key-share-random.py", tls12_exclude_legacy_protocols),
|
||||
Test("test-export-ciphers-rejected.py", ["--min-ver", "TLSv1.2"]),
|
||||
Test(
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
# $OpenBSD: Makefile,v 1.31 2024/02/05 15:30:04 mpi Exp $
|
||||
# $OpenBSD: Makefile,v 1.32 2024/09/06 08:00:36 mpi Exp $
|
||||
|
||||
BTRACE?= /usr/sbin/btrace
|
||||
ALLOWDT!= sysctl -n kern.allowdt 2>/dev/null
|
||||
@ -8,8 +8,8 @@ BT_LANG_SCRIPTS= arithm beginend beginend-argn boolean comments \
|
||||
delete exit histempty if \
|
||||
map mapclear mapempty mapsyntax mapzero map-unnamed \
|
||||
maxoperand min+max+sum multismts nsecs+var \
|
||||
precedence print read-map-after-clear staticv-empty \
|
||||
syntaxerror tuple tupleeval vareval
|
||||
precedence print printf read-map-after-clear \
|
||||
staticv-empty syntaxerror tuple tupleeval vareval
|
||||
|
||||
BT_ARG_LANG_SCRIPTS= staticv str
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
// Test multiple statements inside a single block;
|
||||
BEGIN {
|
||||
printf("One"); printf(", %d", "2");
|
||||
printf(" %s three%c\n", "and", "!");
|
||||
printf(" %s three!\n", "and");
|
||||
}
|
||||
|
||||
4
regress/usr.sbin/btrace/printf.bt
Normal file
4
regress/usr.sbin/btrace/printf.bt
Normal file
@ -0,0 +1,4 @@
|
||||
BEGIN {
|
||||
$c = 0x41; // 'A'
|
||||
printf("%c%c%c\n", $c, 0x41, 65);
|
||||
}
|
||||
1
regress/usr.sbin/btrace/printf.ok
Normal file
1
regress/usr.sbin/btrace/printf.ok
Normal file
@ -0,0 +1 @@
|
||||
AAA
|
||||
@ -2,7 +2,11 @@
|
||||
/* config.h.in. Generated from configure.ac by autoheader. */
|
||||
|
||||
/* apply the fallthrough attribute. */
|
||||
#if defined(__clang__)
|
||||
#define ATTR_FALLTHROUGH __attribute__((fallthrough));
|
||||
#else
|
||||
#define ATTR_FALLTHROUGH
|
||||
#endif
|
||||
|
||||
/* apply the noreturn attribute to a function that exits the program */
|
||||
#define ATTR_NORETURN __attribute__((__noreturn__))
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
.\" $OpenBSD: kubsan.4,v 1.3 2019/05/24 18:53:25 anton Exp $
|
||||
.\" $OpenBSD: kubsan.4,v 1.5 2024/09/06 13:31:59 mbuhl Exp $
|
||||
.\"
|
||||
.\" Copyright (c) 2019 Anton Lindqvist <anton@openbsd.org>
|
||||
.\"
|
||||
@ -13,7 +13,7 @@
|
||||
.\" WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
.\" ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
.\" OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
.Dd $Mdocdate: May 24 2019 $
|
||||
.Dd $Mdocdate: September 6 2024 $
|
||||
.Dt KUBSAN 4
|
||||
.Os
|
||||
.Sh NAME
|
||||
@ -37,6 +37,9 @@ option KUBSAN
|
||||
.Pp
|
||||
The following undefined behavior is detected:
|
||||
.Bl -tag -width 4n
|
||||
.It Float cast overflow
|
||||
The conversion from a floating point to an integer cannot be represented by
|
||||
the destination type.
|
||||
.It Integer overflow
|
||||
The result of an arithmetic computation on two integer operands cannot be
|
||||
represented by the destination type.
|
||||
@ -66,6 +69,8 @@ Passing
|
||||
.Dv NULL
|
||||
as the value for a function argument annotated with
|
||||
.Dv __nonnull__ .
|
||||
.It Invalid builtin
|
||||
Passing zero to a compiler builtin where not allowed.
|
||||
.It Invalid load
|
||||
Loading a value that cannot be represented by the destination type.
|
||||
.It Type mismatch
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $OpenBSD: dt_dev.c,v 1.36 2024/08/22 10:08:25 mvs Exp $ */
|
||||
/* $OpenBSD: dt_dev.c,v 1.37 2024/09/06 08:38:21 mpi Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2019 Martin Pieuchot <mpi@openbsd.org>
|
||||
@ -26,6 +26,8 @@
|
||||
#include <sys/proc.h>
|
||||
#include <sys/ptrace.h>
|
||||
|
||||
#include <machine/intr.h>
|
||||
|
||||
#include <dev/dt/dtvar.h>
|
||||
|
||||
/*
|
||||
@ -96,6 +98,7 @@ struct dt_softc {
|
||||
SLIST_ENTRY(dt_softc) ds_next; /* [K] descriptor list */
|
||||
int ds_unit; /* [I] D_CLONE unique unit */
|
||||
pid_t ds_pid; /* [I] PID of tracing program */
|
||||
void *ds_si; /* [I] to defer wakeup(9) */
|
||||
|
||||
struct mutex ds_mtx;
|
||||
|
||||
@ -142,6 +145,9 @@ int dt_ioctl_get_auxbase(struct dt_softc *, struct dtioc_getaux *);
|
||||
int dt_pcb_ring_copy(struct dt_pcb *, struct uio *, size_t, size_t *,
|
||||
uint64_t *);
|
||||
|
||||
void dt_wakeup(struct dt_softc *);
|
||||
void dt_deferred_wakeup(void *);
|
||||
|
||||
void
|
||||
dtattach(struct device *parent, struct device *self, void *aux)
|
||||
{
|
||||
@ -183,6 +189,11 @@ dtopen(dev_t dev, int flags, int mode, struct proc *p)
|
||||
sc->ds_evtcnt = 0;
|
||||
sc->ds_readevt = 0;
|
||||
sc->ds_dropevt = 0;
|
||||
sc->ds_si = softintr_establish(IPL_SOFTCLOCK, dt_deferred_wakeup, sc);
|
||||
if (sc->ds_si == NULL) {
|
||||
free(sc, M_DEVBUF, sizeof(*sc));
|
||||
return ENOMEM;
|
||||
}
|
||||
|
||||
SLIST_INSERT_HEAD(&dtdev_list, sc, ds_next);
|
||||
|
||||
@ -205,6 +216,7 @@ dtclose(dev_t dev, int flags, int mode, struct proc *p)
|
||||
SLIST_REMOVE(&dtdev_list, sc, dt_softc, ds_next);
|
||||
dt_ioctl_record_stop(sc);
|
||||
dt_pcb_purge(&sc->ds_pcbs);
|
||||
softintr_disestablish(sc->ds_si);
|
||||
|
||||
free(sc, M_DEVBUF, sizeof(*sc));
|
||||
|
||||
@ -719,7 +731,7 @@ dt_pcb_ring_consume(struct dt_pcb *dp, struct dt_evt *dtev)
|
||||
mtx_enter(&dp->dp_sc->ds_mtx);
|
||||
dp->dp_sc->ds_evtcnt++;
|
||||
mtx_leave(&dp->dp_sc->ds_mtx);
|
||||
wakeup(dp->dp_sc);
|
||||
dt_wakeup(dp->dp_sc);
|
||||
}
|
||||
|
||||
/*
|
||||
@ -780,3 +792,24 @@ out:
|
||||
*rcvd = copied;
|
||||
return error;
|
||||
}
|
||||
|
||||
void
|
||||
dt_wakeup(struct dt_softc *sc)
|
||||
{
|
||||
/*
|
||||
* It is not always safe or possible to call wakeup(9) and grab
|
||||
* the SCHED_LOCK() from a given tracepoint. This is true for
|
||||
* any tracepoint that might trigger inside the scheduler or at
|
||||
* any IPL higher than IPL_SCHED. For this reason use a soft-
|
||||
* interrupt to defer the wakeup.
|
||||
*/
|
||||
softintr_schedule(sc->ds_si);
|
||||
}
|
||||
|
||||
void
|
||||
dt_deferred_wakeup(void *arg)
|
||||
{
|
||||
struct dt_softc *sc = arg;
|
||||
|
||||
wakeup(sc);
|
||||
}
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $OpenBSD: inphyreg.h,v 1.5 2008/06/26 05:42:16 ray Exp $ */
|
||||
/* $OpenBSD: inphyreg.h,v 1.6 2024/09/06 10:54:08 jsg Exp $ */
|
||||
/* $NetBSD: inphyreg.h,v 1.1 1998/08/11 00:00:28 thorpej Exp $ */
|
||||
|
||||
/*-
|
||||
@ -60,7 +60,7 @@
|
||||
#define SCTRL_SCRBYPASS 0x8000 /* scrambler bypass */
|
||||
#define SCTRL_4B5BNYPASS 0x4000 /* 4bit to 5bit bypass */
|
||||
#define SCTRL_FTHP 0x2000 /* force transmit H-pattern */
|
||||
#define SCTRL_F34TP 0x1000 /* force 34 transmit patter */
|
||||
#define SCTRL_F34TP 0x1000 /* force 34 transmit pattern */
|
||||
#define SCTRL_GOODLINK 0x0800 /* 100baseTX link good */
|
||||
#define SCTRL_TCSD 0x0200 /* transmit carrier sense disable */
|
||||
#define SCTRL_DDPD 0x0100 /* disable dynamic power-down */
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $OpenBSD: dwiic_pci.c,v 1.30 2024/08/17 02:31:15 deraadt Exp $ */
|
||||
/* $OpenBSD: dwiic_pci.c,v 1.31 2024/09/06 03:52:38 jsg Exp $ */
|
||||
/*
|
||||
* Synopsys DesignWare I2C controller
|
||||
* PCI attachment
|
||||
@ -179,6 +179,12 @@ const struct pci_matchid dwiic_pci_ids[] = {
|
||||
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_I2C_3 },
|
||||
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_I2C_4 },
|
||||
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_I2C_5 },
|
||||
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_I2C_0 },
|
||||
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_I2C_1 },
|
||||
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_I2C_2 },
|
||||
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_I2C_3 },
|
||||
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_I2C_4 },
|
||||
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_I2C_5 },
|
||||
};
|
||||
|
||||
int
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $OpenBSD: if_lge.c,v 1.81 2024/05/24 06:02:53 jsg Exp $ */
|
||||
/* $OpenBSD: if_lge.c,v 1.82 2024/09/06 10:54:08 jsg Exp $ */
|
||||
/*
|
||||
* Copyright (c) 2001 Wind River Systems
|
||||
* Copyright (c) 1997, 1998, 1999, 2000, 2001
|
||||
@ -1063,7 +1063,7 @@ lge_init(void *xsc)
|
||||
CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX|
|
||||
LGE_MODE1_VLAN_STRIP|LGE_MODE1_VLAN_INSERT);
|
||||
|
||||
/* Workarond: FIFO overflow */
|
||||
/* Workaround: FIFO overflow */
|
||||
CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF);
|
||||
CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT);
|
||||
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $OpenBSD: if_wb.c,v 1.77 2024/05/24 06:02:57 jsg Exp $ */
|
||||
/* $OpenBSD: if_wb.c,v 1.78 2024/09/06 10:54:08 jsg Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1997, 1998
|
||||
@ -1304,7 +1304,7 @@ wb_start(struct ifnet *ifp)
|
||||
* the own bit is clear because the chip cleared it
|
||||
* and where the own bit is clear because we haven't
|
||||
* set it yet. The magic value WB_UNSET is just some
|
||||
* ramdomly chosen number which doesn't have the own
|
||||
* randomly chosen number which doesn't have the own
|
||||
* bit set. When we actually transmit the frame, the
|
||||
* status word will have _only_ the own bit set, so
|
||||
* the txeoc handler will be able to tell if it needs
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $OpenBSD: igc_defines.h,v 1.1 2021/10/31 14:52:57 patrick Exp $ */
|
||||
/* $OpenBSD: igc_defines.h,v 1.2 2024/09/06 10:54:08 jsg Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright 2021 Intel Corp
|
||||
@ -749,7 +749,7 @@
|
||||
/* TTQF SCTP Bit, shift with IGC_TTQF_PROTOCOL_SHIFT */
|
||||
#define IGC_TTQF_PROTOCOL_SCTP 0x2
|
||||
#define IGC_TTQF_PROTOCOL_SHIFT 5 /* TTQF Protocol Shift */
|
||||
#define IGC_TTQF_QUEUE_SHIFT 16 /* TTQF Queue Shfit */
|
||||
#define IGC_TTQF_QUEUE_SHIFT 16 /* TTQF Queue Shift */
|
||||
#define IGC_TTQF_RX_QUEUE_MASK 0x70000 /* TTQF Queue Mask */
|
||||
#define IGC_TTQF_MASK_ENABLE 0x10000000 /* TTQF Mask Enable Bit */
|
||||
#define IGC_IMIR_CLEAR_MASK 0xF001FFFF /* IMIR Reg Clear Mask */
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
$OpenBSD: pcidevs,v 1.2088 2024/09/04 23:56:43 dlg Exp $
|
||||
$OpenBSD: pcidevs,v 1.2089 2024/09/06 03:48:20 jsg Exp $
|
||||
/* $NetBSD: pcidevs,v 1.30 1997/06/24 06:20:24 thorpej Exp $ */
|
||||
|
||||
/*
|
||||
@ -6157,6 +6157,14 @@ product INTEL APOLLOLAKE_AHCI 0x5ae3 Apollo Lake AHCI
|
||||
product INTEL APOLLOLAKE_LPC 0x5ae8 Apollo Lake LPC
|
||||
product INTEL APOLLOLAKE_UART_4 0x5aee Apollo Lake HSUART
|
||||
product INTEL APOLLOLAKE_HB 0x5af0 Apollo Lake Host
|
||||
product INTEL LNL_HB 0x6400 Core Ultra Host
|
||||
product INTEL LNL_DTT 0x641d Core Ultra DTT
|
||||
product INTEL LNL_GT_1 0x6420 Graphics
|
||||
product INTEL LNL_NPU 0x643e Core Ultra NPU
|
||||
product INTEL LNL_IPU 0x645d Core Ultra IPU
|
||||
product INTEL LNL_CT 0x647d Core Ultra CT
|
||||
product INTEL LNL_GT_2 0x64a0 Graphics
|
||||
product INTEL LNL_GT_3 0x64b0 Graphics
|
||||
product INTEL 5100_HB 0x65c0 5100 Host
|
||||
product INTEL 5100_PCIE_2 0x65e2 5100 PCIE
|
||||
product INTEL 5100_PCIE_3 0x65e3 5100 PCIE
|
||||
@ -7263,6 +7271,58 @@ product INTEL RPL_P_GT_4 0xa7aa Graphics
|
||||
product INTEL RPL_P_GT_5 0xa7ab Graphics
|
||||
product INTEL RPL_U_GT_4 0xa7ac Graphics
|
||||
product INTEL RPL_U_GT_5 0xa7ad Graphics
|
||||
product INTEL LNL_ESPI 0xa807 Core Ultra eSPI
|
||||
product INTEL LNL_P2SB_1 0xa820 Core Ultra P2SB
|
||||
product INTEL LNL_PMC 0xa821 Core Ultra PMC
|
||||
product INTEL LNL_SPI 0xa823 Core Ultra SPI
|
||||
product INTEL LNL_TH 0xa824 Core Ultra TH
|
||||
product INTEL LNL_UART_0 0xa825 Core Ultra UART
|
||||
product INTEL LNL_UART_1 0xa826 Core Ultra UART
|
||||
product INTEL LNL_GSPI_0 0xa827 Core Ultra GSPI
|
||||
product INTEL LNL_HDA 0xa828 Core Ultra HD Audio
|
||||
product INTEL LNL_GSPI_1 0xa830 Core Ultra GSPI
|
||||
product INTEL LNL_TC_XHCI 0xa831 Core Ultra xHCI
|
||||
product INTEL LNL_TBT_DMA0 0xa833 Core Ultra TBT
|
||||
product INTEL LNL_TBT_DMA1 0xa834 Core Ultra TBT
|
||||
product INTEL LNL_PCIE_1 0xa838 Core Ultra PCIE
|
||||
product INTEL LNL_PCIE_2 0xa839 Core Ultra PCIE
|
||||
product INTEL LNL_PCIE_3 0xa83a Core Ultra PCIE
|
||||
product INTEL LNL_PCIE_4 0xa83b Core Ultra PCIE
|
||||
product INTEL LNL_PCIE_5 0xa83c Core Ultra PCIE
|
||||
product INTEL LNL_PCIE_6 0xa83d Core Ultra PCIE
|
||||
product INTEL LNL_ISH 0xa845 Core Ultra ISH
|
||||
product INTEL LNL_GSPI_2 0xa846 Core Ultra GSPI
|
||||
product INTEL LNL_THC_0_1 0xa848 Core Ultra THC
|
||||
product INTEL LNL_THC_0_2 0xa849 Core Ultra THC
|
||||
product INTEL LNL_THC_1_1 0xa84a Core Ultra THC
|
||||
product INTEL LNL_THC_1_2 0xa84b Core Ultra THC
|
||||
product INTEL LNL_P2SB_2 0xa84c Core Ultra P2SB
|
||||
product INTEL LNL_TC_PCIE_21 0xa84e Core Ultra PCIE
|
||||
product INTEL LNL_TC_PCIE_22 0xa84f Core Ultra PCIE
|
||||
product INTEL LNL_I2C_4 0xa850 Core Ultra I2C
|
||||
product INTEL LNL_I2C_5 0xa851 Core Ultra I2C
|
||||
product INTEL LNL_UART_2 0xa852 Core Ultra UART
|
||||
product INTEL LNL_HECI_4 0xa85d Core Ultra HECI
|
||||
product INTEL LNL_HECI_5 0xa85e Core Ultra HECI
|
||||
product INTEL LNL_HECI_6 0xa85f Core Ultra HECI
|
||||
product INTEL LNL_TC_PCIE_23 0xa860 Core Ultra PCIE
|
||||
product INTEL LNL_HECI_1 0xa862 Core Ultra HECI
|
||||
product INTEL LNL_HECI_2 0xa863 Core Ultra HECI
|
||||
product INTEL LNL_HECI_3 0xa864 Core Ultra HECI
|
||||
product INTEL LNL_CSE_HECI_1 0xa870 Core Ultra HECI
|
||||
product INTEL LNL_CSE_HECI_2 0xa871 Core Ultra HECI
|
||||
product INTEL LNL_IDER 0xa872 Core Ultra IDE-R
|
||||
product INTEL LNL_KT 0xa873 Core Ultra KT
|
||||
product INTEL LNL_CSE_HECI_3 0xa874 Core Ultra HECI
|
||||
product INTEL LNL_CSE_HECI_4 0xa875 Core Ultra HECI
|
||||
product INTEL LNL_I3C_2 0xa877 Core Ultra I3C
|
||||
product INTEL LNL_I2C_0 0xa878 Core Ultra I2C
|
||||
product INTEL LNL_I2C_1 0xa879 Core Ultra I2C
|
||||
product INTEL LNL_I2C_2 0xa87a Core Ultra I2C
|
||||
product INTEL LNL_I2C_3 0xa87b Core Ultra I2C
|
||||
product INTEL LNL_I3C_1 0xa87c Core Ultra I3C
|
||||
product INTEL LNL_XHCI 0xa87d Core Ultra xHCI
|
||||
product INTEL LNL_SRAM 0xa87f Core Ultra SRAM
|
||||
product INTEL 21152 0xb152 S21152BB
|
||||
product INTEL 21154 0xb154 21154AE/BE
|
||||
product INTEL CORE_DMI_0 0xd130 Core DMI
|
||||
|
||||
@ -2,7 +2,7 @@
|
||||
* THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
|
||||
*
|
||||
* generated from:
|
||||
* OpenBSD: pcidevs,v 1.2088 2024/09/04 23:56:43 dlg Exp
|
||||
* OpenBSD: pcidevs,v 1.2089 2024/09/06 03:48:20 jsg Exp
|
||||
*/
|
||||
/* $NetBSD: pcidevs,v 1.30 1997/06/24 06:20:24 thorpej Exp $ */
|
||||
|
||||
@ -6162,6 +6162,14 @@
|
||||
#define PCI_PRODUCT_INTEL_APOLLOLAKE_LPC 0x5ae8 /* Apollo Lake LPC */
|
||||
#define PCI_PRODUCT_INTEL_APOLLOLAKE_UART_4 0x5aee /* Apollo Lake HSUART */
|
||||
#define PCI_PRODUCT_INTEL_APOLLOLAKE_HB 0x5af0 /* Apollo Lake Host */
|
||||
#define PCI_PRODUCT_INTEL_LNL_HB 0x6400 /* Core Ultra Host */
|
||||
#define PCI_PRODUCT_INTEL_LNL_DTT 0x641d /* Core Ultra DTT */
|
||||
#define PCI_PRODUCT_INTEL_LNL_GT_1 0x6420 /* Graphics */
|
||||
#define PCI_PRODUCT_INTEL_LNL_NPU 0x643e /* Core Ultra NPU */
|
||||
#define PCI_PRODUCT_INTEL_LNL_IPU 0x645d /* Core Ultra IPU */
|
||||
#define PCI_PRODUCT_INTEL_LNL_CT 0x647d /* Core Ultra CT */
|
||||
#define PCI_PRODUCT_INTEL_LNL_GT_2 0x64a0 /* Graphics */
|
||||
#define PCI_PRODUCT_INTEL_LNL_GT_3 0x64b0 /* Graphics */
|
||||
#define PCI_PRODUCT_INTEL_5100_HB 0x65c0 /* 5100 Host */
|
||||
#define PCI_PRODUCT_INTEL_5100_PCIE_2 0x65e2 /* 5100 PCIE */
|
||||
#define PCI_PRODUCT_INTEL_5100_PCIE_3 0x65e3 /* 5100 PCIE */
|
||||
@ -7268,6 +7276,58 @@
|
||||
#define PCI_PRODUCT_INTEL_RPL_P_GT_5 0xa7ab /* Graphics */
|
||||
#define PCI_PRODUCT_INTEL_RPL_U_GT_4 0xa7ac /* Graphics */
|
||||
#define PCI_PRODUCT_INTEL_RPL_U_GT_5 0xa7ad /* Graphics */
|
||||
#define PCI_PRODUCT_INTEL_LNL_ESPI 0xa807 /* Core Ultra eSPI */
|
||||
#define PCI_PRODUCT_INTEL_LNL_P2SB_1 0xa820 /* Core Ultra P2SB */
|
||||
#define PCI_PRODUCT_INTEL_LNL_PMC 0xa821 /* Core Ultra PMC */
|
||||
#define PCI_PRODUCT_INTEL_LNL_SPI 0xa823 /* Core Ultra SPI */
|
||||
#define PCI_PRODUCT_INTEL_LNL_TH 0xa824 /* Core Ultra TH */
|
||||
#define PCI_PRODUCT_INTEL_LNL_UART_0 0xa825 /* Core Ultra UART */
|
||||
#define PCI_PRODUCT_INTEL_LNL_UART_1 0xa826 /* Core Ultra UART */
|
||||
#define PCI_PRODUCT_INTEL_LNL_GSPI_0 0xa827 /* Core Ultra GSPI */
|
||||
#define PCI_PRODUCT_INTEL_LNL_HDA 0xa828 /* Core Ultra HD Audio */
|
||||
#define PCI_PRODUCT_INTEL_LNL_GSPI_1 0xa830 /* Core Ultra GSPI */
|
||||
#define PCI_PRODUCT_INTEL_LNL_TC_XHCI 0xa831 /* Core Ultra xHCI */
|
||||
#define PCI_PRODUCT_INTEL_LNL_TBT_DMA0 0xa833 /* Core Ultra TBT */
|
||||
#define PCI_PRODUCT_INTEL_LNL_TBT_DMA1 0xa834 /* Core Ultra TBT */
|
||||
#define PCI_PRODUCT_INTEL_LNL_PCIE_1 0xa838 /* Core Ultra PCIE */
|
||||
#define PCI_PRODUCT_INTEL_LNL_PCIE_2 0xa839 /* Core Ultra PCIE */
|
||||
#define PCI_PRODUCT_INTEL_LNL_PCIE_3 0xa83a /* Core Ultra PCIE */
|
||||
#define PCI_PRODUCT_INTEL_LNL_PCIE_4 0xa83b /* Core Ultra PCIE */
|
||||
#define PCI_PRODUCT_INTEL_LNL_PCIE_5 0xa83c /* Core Ultra PCIE */
|
||||
#define PCI_PRODUCT_INTEL_LNL_PCIE_6 0xa83d /* Core Ultra PCIE */
|
||||
#define PCI_PRODUCT_INTEL_LNL_ISH 0xa845 /* Core Ultra ISH */
|
||||
#define PCI_PRODUCT_INTEL_LNL_GSPI_2 0xa846 /* Core Ultra GSPI */
|
||||
#define PCI_PRODUCT_INTEL_LNL_THC_0_1 0xa848 /* Core Ultra THC */
|
||||
#define PCI_PRODUCT_INTEL_LNL_THC_0_2 0xa849 /* Core Ultra THC */
|
||||
#define PCI_PRODUCT_INTEL_LNL_THC_1_1 0xa84a /* Core Ultra THC */
|
||||
#define PCI_PRODUCT_INTEL_LNL_THC_1_2 0xa84b /* Core Ultra THC */
|
||||
#define PCI_PRODUCT_INTEL_LNL_P2SB_2 0xa84c /* Core Ultra P2SB */
|
||||
#define PCI_PRODUCT_INTEL_LNL_TC_PCIE_21 0xa84e /* Core Ultra PCIE */
|
||||
#define PCI_PRODUCT_INTEL_LNL_TC_PCIE_22 0xa84f /* Core Ultra PCIE */
|
||||
#define PCI_PRODUCT_INTEL_LNL_I2C_4 0xa850 /* Core Ultra I2C */
|
||||
#define PCI_PRODUCT_INTEL_LNL_I2C_5 0xa851 /* Core Ultra I2C */
|
||||
#define PCI_PRODUCT_INTEL_LNL_UART_2 0xa852 /* Core Ultra UART */
|
||||
#define PCI_PRODUCT_INTEL_LNL_HECI_4 0xa85d /* Core Ultra HECI */
|
||||
#define PCI_PRODUCT_INTEL_LNL_HECI_5 0xa85e /* Core Ultra HECI */
|
||||
#define PCI_PRODUCT_INTEL_LNL_HECI_6 0xa85f /* Core Ultra HECI */
|
||||
#define PCI_PRODUCT_INTEL_LNL_TC_PCIE_23 0xa860 /* Core Ultra PCIE */
|
||||
#define PCI_PRODUCT_INTEL_LNL_HECI_1 0xa862 /* Core Ultra HECI */
|
||||
#define PCI_PRODUCT_INTEL_LNL_HECI_2 0xa863 /* Core Ultra HECI */
|
||||
#define PCI_PRODUCT_INTEL_LNL_HECI_3 0xa864 /* Core Ultra HECI */
|
||||
#define PCI_PRODUCT_INTEL_LNL_CSE_HECI_1 0xa870 /* Core Ultra HECI */
|
||||
#define PCI_PRODUCT_INTEL_LNL_CSE_HECI_2 0xa871 /* Core Ultra HECI */
|
||||
#define PCI_PRODUCT_INTEL_LNL_IDER 0xa872 /* Core Ultra IDE-R */
|
||||
#define PCI_PRODUCT_INTEL_LNL_KT 0xa873 /* Core Ultra KT */
|
||||
#define PCI_PRODUCT_INTEL_LNL_CSE_HECI_3 0xa874 /* Core Ultra HECI */
|
||||
#define PCI_PRODUCT_INTEL_LNL_CSE_HECI_4 0xa875 /* Core Ultra HECI */
|
||||
#define PCI_PRODUCT_INTEL_LNL_I3C_2 0xa877 /* Core Ultra I3C */
|
||||
#define PCI_PRODUCT_INTEL_LNL_I2C_0 0xa878 /* Core Ultra I2C */
|
||||
#define PCI_PRODUCT_INTEL_LNL_I2C_1 0xa879 /* Core Ultra I2C */
|
||||
#define PCI_PRODUCT_INTEL_LNL_I2C_2 0xa87a /* Core Ultra I2C */
|
||||
#define PCI_PRODUCT_INTEL_LNL_I2C_3 0xa87b /* Core Ultra I2C */
|
||||
#define PCI_PRODUCT_INTEL_LNL_I3C_1 0xa87c /* Core Ultra I3C */
|
||||
#define PCI_PRODUCT_INTEL_LNL_XHCI 0xa87d /* Core Ultra xHCI */
|
||||
#define PCI_PRODUCT_INTEL_LNL_SRAM 0xa87f /* Core Ultra SRAM */
|
||||
#define PCI_PRODUCT_INTEL_21152 0xb152 /* S21152BB */
|
||||
#define PCI_PRODUCT_INTEL_21154 0xb154 /* 21154AE/BE */
|
||||
#define PCI_PRODUCT_INTEL_CORE_DMI_0 0xd130 /* Core DMI */
|
||||
|
||||
@ -2,7 +2,7 @@
|
||||
* THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
|
||||
*
|
||||
* generated from:
|
||||
* OpenBSD: pcidevs,v 1.2088 2024/09/04 23:56:43 dlg Exp
|
||||
* OpenBSD: pcidevs,v 1.2089 2024/09/06 03:48:20 jsg Exp
|
||||
*/
|
||||
|
||||
/* $NetBSD: pcidevs,v 1.30 1997/06/24 06:20:24 thorpej Exp $ */
|
||||
@ -21975,6 +21975,38 @@ static const struct pci_known_product pci_known_products[] = {
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_APOLLOLAKE_HB,
|
||||
"Apollo Lake Host",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_HB,
|
||||
"Core Ultra Host",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_DTT,
|
||||
"Core Ultra DTT",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_GT_1,
|
||||
"Graphics",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_NPU,
|
||||
"Core Ultra NPU",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_IPU,
|
||||
"Core Ultra IPU",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_CT,
|
||||
"Core Ultra CT",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_GT_2,
|
||||
"Graphics",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_GT_3,
|
||||
"Graphics",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_5100_HB,
|
||||
"5100 Host",
|
||||
@ -26399,6 +26431,214 @@ static const struct pci_known_product pci_known_products[] = {
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_RPL_U_GT_5,
|
||||
"Graphics",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_ESPI,
|
||||
"Core Ultra eSPI",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_P2SB_1,
|
||||
"Core Ultra P2SB",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_PMC,
|
||||
"Core Ultra PMC",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_SPI,
|
||||
"Core Ultra SPI",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_TH,
|
||||
"Core Ultra TH",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_UART_0,
|
||||
"Core Ultra UART",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_UART_1,
|
||||
"Core Ultra UART",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_GSPI_0,
|
||||
"Core Ultra GSPI",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_HDA,
|
||||
"Core Ultra HD Audio",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_GSPI_1,
|
||||
"Core Ultra GSPI",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_TC_XHCI,
|
||||
"Core Ultra xHCI",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_TBT_DMA0,
|
||||
"Core Ultra TBT",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_TBT_DMA1,
|
||||
"Core Ultra TBT",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_PCIE_1,
|
||||
"Core Ultra PCIE",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_PCIE_2,
|
||||
"Core Ultra PCIE",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_PCIE_3,
|
||||
"Core Ultra PCIE",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_PCIE_4,
|
||||
"Core Ultra PCIE",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_PCIE_5,
|
||||
"Core Ultra PCIE",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_PCIE_6,
|
||||
"Core Ultra PCIE",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_ISH,
|
||||
"Core Ultra ISH",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_GSPI_2,
|
||||
"Core Ultra GSPI",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_THC_0_1,
|
||||
"Core Ultra THC",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_THC_0_2,
|
||||
"Core Ultra THC",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_THC_1_1,
|
||||
"Core Ultra THC",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_THC_1_2,
|
||||
"Core Ultra THC",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_P2SB_2,
|
||||
"Core Ultra P2SB",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_TC_PCIE_21,
|
||||
"Core Ultra PCIE",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_TC_PCIE_22,
|
||||
"Core Ultra PCIE",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_I2C_4,
|
||||
"Core Ultra I2C",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_I2C_5,
|
||||
"Core Ultra I2C",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_UART_2,
|
||||
"Core Ultra UART",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_HECI_4,
|
||||
"Core Ultra HECI",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_HECI_5,
|
||||
"Core Ultra HECI",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_HECI_6,
|
||||
"Core Ultra HECI",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_TC_PCIE_23,
|
||||
"Core Ultra PCIE",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_HECI_1,
|
||||
"Core Ultra HECI",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_HECI_2,
|
||||
"Core Ultra HECI",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_HECI_3,
|
||||
"Core Ultra HECI",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_CSE_HECI_1,
|
||||
"Core Ultra HECI",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_CSE_HECI_2,
|
||||
"Core Ultra HECI",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_IDER,
|
||||
"Core Ultra IDE-R",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_KT,
|
||||
"Core Ultra KT",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_CSE_HECI_3,
|
||||
"Core Ultra HECI",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_CSE_HECI_4,
|
||||
"Core Ultra HECI",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_I3C_2,
|
||||
"Core Ultra I3C",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_I2C_0,
|
||||
"Core Ultra I2C",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_I2C_1,
|
||||
"Core Ultra I2C",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_I2C_2,
|
||||
"Core Ultra I2C",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_I2C_3,
|
||||
"Core Ultra I2C",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_I3C_1,
|
||||
"Core Ultra I3C",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_XHCI,
|
||||
"Core Ultra xHCI",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_SRAM,
|
||||
"Core Ultra SRAM",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_21152,
|
||||
"S21152BB",
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $OpenBSD: pciide_cmd_reg.h,v 1.11 2010/07/23 07:47:13 jsg Exp $ */
|
||||
/* $OpenBSD: pciide_cmd_reg.h,v 1.12 2024/09/06 10:54:08 jsg Exp $ */
|
||||
/* $NetBSD: pciide_cmd_reg.h,v 1.9 2000/08/02 20:23:46 bouyer Exp $ */
|
||||
|
||||
/*
|
||||
@ -78,12 +78,12 @@
|
||||
#define CMD_DMA 0x00
|
||||
#define CMD_DMA_MULTIPLE 0x01
|
||||
#define CMD_DMA_LINE 0x03
|
||||
/* the followings bits are only for 0646U/646U2/648/649 */
|
||||
/* the following bits are only for 0646U/646U2/648/649 */
|
||||
#define CMD_DMA_IRQ(chan) (0x4 << (chan))
|
||||
#define CMD_DMA_IRQ_DIS(chan) (0x10 << (chan))
|
||||
#define CMD_DMA_RST 0x40
|
||||
|
||||
/* the followings are only for 0646U/646U2/648/649 */
|
||||
/* the following is only for 0646U/646U2/648/649 */
|
||||
/* busmaster control/status register */
|
||||
#define CMD_BICSR 0x79
|
||||
#define CMD_BICSR_80(chan) (0x01 << (chan))
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $OpenBSD: kern_exit.c,v 1.232 2024/08/16 16:19:03 mpi Exp $ */
|
||||
/* $OpenBSD: kern_exit.c,v 1.233 2024/09/06 08:21:21 mpi Exp $ */
|
||||
/* $NetBSD: kern_exit.c,v 1.39 1996/04/22 01:38:25 christos Exp $ */
|
||||
|
||||
/*
|
||||
@ -390,7 +390,6 @@ exit1(struct proc *p, int xexit, int xsig, int flags)
|
||||
* Note that cpu_exit() will end with a call equivalent to
|
||||
* cpu_switch(), finishing our execution (pun intended).
|
||||
*/
|
||||
uvmexp.swtch++;
|
||||
cpu_exit(p);
|
||||
panic("cpu_exit returned");
|
||||
}
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $OpenBSD: subr_kubsan.c,v 1.12 2019/11/06 19:16:48 anton Exp $ */
|
||||
/* $OpenBSD: subr_kubsan.c,v 1.13 2024/09/06 13:31:59 mbuhl Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2019 Anton Lindqvist <anton@openbsd.org>
|
||||
@ -38,6 +38,7 @@
|
||||
struct kubsan_report {
|
||||
enum {
|
||||
KUBSAN_FLOAT_CAST_OVERFLOW,
|
||||
KUBSAN_INVALID_BUILTIN,
|
||||
KUBSAN_INVALID_VALUE,
|
||||
KUBSAN_NEGATE_OVERFLOW,
|
||||
KUBSAN_NONNULL_ARG,
|
||||
@ -57,6 +58,10 @@ struct kubsan_report {
|
||||
unsigned long v_val;
|
||||
} v_float_cast_overflow;
|
||||
|
||||
struct {
|
||||
const struct invalid_builtin_data *v_data;
|
||||
} v_invalid_builtin;
|
||||
|
||||
struct {
|
||||
const struct invalid_value_data *v_data;
|
||||
unsigned long v_val;
|
||||
@ -102,6 +107,7 @@ struct kubsan_report {
|
||||
} kr_u;
|
||||
};
|
||||
#define kr_float_cast_overflow kr_u.v_float_cast_overflow
|
||||
#define kr_invalid_builtin kr_u.v_invalid_builtin
|
||||
#define kr_invalid_value kr_u.v_invalid_value
|
||||
#define kr_negate_overflow kr_u.v_negate_overflow
|
||||
#define kr_nonnull_arg kr_u.v_nonnull_arg
|
||||
@ -129,6 +135,11 @@ struct float_cast_overflow_data {
|
||||
struct type_descriptor *d_ttype; /* to type */
|
||||
};
|
||||
|
||||
struct invalid_builtin_data {
|
||||
struct source_location d_src;
|
||||
uint8_t d_kind;
|
||||
};
|
||||
|
||||
struct invalid_value_data {
|
||||
struct source_location d_src;
|
||||
struct type_descriptor *d_type;
|
||||
@ -264,6 +275,18 @@ __ubsan_handle_float_cast_overflow(struct float_cast_overflow_data *data,
|
||||
kubsan_defer_report(&kr);
|
||||
}
|
||||
|
||||
void
|
||||
__ubsan_handle_invalid_builtin(struct invalid_builtin_data *data)
|
||||
{
|
||||
struct kubsan_report kr = {
|
||||
.kr_type = KUBSAN_INVALID_VALUE,
|
||||
.kr_src = &data->d_src,
|
||||
.kr_invalid_builtin = { data },
|
||||
};
|
||||
|
||||
kubsan_defer_report(&kr);
|
||||
}
|
||||
|
||||
void
|
||||
__ubsan_handle_load_invalid_value(struct invalid_value_data *data,
|
||||
unsigned long val)
|
||||
@ -562,6 +585,16 @@ again:
|
||||
break;
|
||||
}
|
||||
|
||||
case KUBSAN_INVALID_BUILTIN: {
|
||||
const struct invalid_builtin_data *data =
|
||||
kr->kr_invalid_builtin.v_data;
|
||||
|
||||
printf("kubsan: %s: invalid builtin: passing zero to "
|
||||
"%s, which is not a valid argument\n",
|
||||
bloc, kubsan_kind(data->d_kind));
|
||||
break;
|
||||
}
|
||||
|
||||
case KUBSAN_INVALID_VALUE: {
|
||||
const struct invalid_value_data *data =
|
||||
kr->kr_invalid_value.v_data;
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
/* $OpenBSD: memmove.S,v 1.2 2004/02/01 05:47:10 drahn Exp $ */
|
||||
/* $OpenBSD: memmove.S,v 1.3 2024/09/06 10:54:08 jsg Exp $ */
|
||||
/* $NetBSD: memmove.S,v 1.2 2001/11/20 00:29:20 chris Exp $ */
|
||||
|
||||
/*
|
||||
* placeholder to keep the make system happy, memove is actually in memcpy.S
|
||||
* placeholder to keep the make system happy, memmove is actually in memcpy.S
|
||||
*/
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $OpenBSD: match.c,v 1.44 2023/04/06 03:19:32 djm Exp $ */
|
||||
/* $OpenBSD: match.c,v 1.45 2024/09/06 02:30:44 djm Exp $ */
|
||||
/*
|
||||
* Author: Tatu Ylonen <ylo@cs.hut.fi>
|
||||
* Copyright (c) 1995 Tatu Ylonen <ylo@cs.hut.fi>, Espoo, Finland
|
||||
@ -234,7 +234,7 @@ match_user(const char *user, const char *host, const char *ipaddr,
|
||||
|
||||
/* test mode */
|
||||
if (user == NULL && host == NULL && ipaddr == NULL) {
|
||||
if ((p = strchr(pattern, '@')) != NULL &&
|
||||
if ((p = strrchr(pattern, '@')) != NULL &&
|
||||
match_host_and_ip(NULL, NULL, p + 1) < 0)
|
||||
return -1;
|
||||
return 0;
|
||||
@ -243,11 +243,11 @@ match_user(const char *user, const char *host, const char *ipaddr,
|
||||
if (user == NULL)
|
||||
return 0; /* shouldn't happen */
|
||||
|
||||
if ((p = strchr(pattern, '@')) == NULL)
|
||||
if (strrchr(pattern, '@') == NULL)
|
||||
return match_pattern(user, pattern);
|
||||
|
||||
pat = xstrdup(pattern);
|
||||
p = strchr(pat, '@');
|
||||
p = strrchr(pat, '@');
|
||||
*p++ = '\0';
|
||||
|
||||
if ((ret = match_pattern(user, pat)) == 1)
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $OpenBSD: ssh-add.c,v 1.172 2024/01/11 01:45:36 djm Exp $ */
|
||||
/* $OpenBSD: ssh-add.c,v 1.173 2024/09/06 02:30:44 djm Exp $ */
|
||||
/*
|
||||
* Author: Tatu Ylonen <ylo@cs.hut.fi>
|
||||
* Copyright (c) 1995 Tatu Ylonen <ylo@cs.hut.fi>, Espoo, Finland
|
||||
@ -691,7 +691,7 @@ parse_dest_constraint_hop(const char *s, struct dest_constraint_hop *dch,
|
||||
|
||||
memset(dch, '\0', sizeof(*dch));
|
||||
os = xstrdup(s);
|
||||
if ((host = strchr(os, '@')) == NULL)
|
||||
if ((host = strrchr(os, '@')) == NULL)
|
||||
host = os;
|
||||
else {
|
||||
*host++ = '\0';
|
||||
|
||||
@ -1,3 +1,3 @@
|
||||
/* $OpenBSD: version.h,v 1.16 2024/06/26 08:28:45 claudio Exp $ */
|
||||
/* $OpenBSD: version.h,v 1.17 2024/09/05 20:28:42 claudio Exp $ */
|
||||
|
||||
#define BGPD_VERSION "8.5"
|
||||
#define BGPD_VERSION "8.6"
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $OpenBSD: printf.c,v 1.2 2020/09/18 19:19:38 jasper Exp $ */
|
||||
/* $OpenBSD: printf.c,v 1.3 2024/09/06 07:58:50 mpi Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1989 The Regents of the University of California.
|
||||
@ -400,7 +400,7 @@ getchr(void)
|
||||
if (gargv == NULL)
|
||||
return((int)'\0');
|
||||
|
||||
c = (int)*ba2str(gargv, gdevt);
|
||||
c = ba2long(gargv, gdevt);
|
||||
gargv = SLIST_NEXT(gargv, ba_next);
|
||||
return c;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user