From f609457dcf785e98c7f1172a815d1eb314fab6ff Mon Sep 17 00:00:00 2001 From: purplerain Date: Tue, 2 May 2023 22:23:09 +0000 Subject: [PATCH] sync --- distrib/miniroot/install.sub | 4 +- etc/skel/dot.version | 2 +- gnu/usr.bin/binutils-2.17/binutils/configure | 2 +- gnu/usr.bin/binutils-2.17/gas/configure.tgt | 2 +- lib/libcrypto/ec/ec_curve.c | 44 +- .../man/X509_NAME_get_index_by_NID.3 | 30 +- lib/libcrypto/pkcs7/pk7_mime.c | 15 +- lib/libcrypto/x509/x509name.c | 37 +- lib/libz/README | 9 +- lib/libz/zconf.h | 2 +- lib/libz/zlib.h | 2 +- regress/lib/libcrypto/bio/bio_asn1.c | 6 +- regress/lib/libcrypto/man/check_complete.pl | 2 +- regress/lib/libcrypto/x509/x509_asn1.c | 79 +- share/misc/airport | 3 +- sys/dev/acpi/abl.c | 2 +- sys/dev/acpi/acpi_x86.c | 2 +- sys/dev/acpi/acpiec.c | 2 +- sys/dev/acpi/acpithinkpad.c | 8 +- sys/dev/kstat.c | 4 +- sys/dev/pci/aac_pci.c | 2 +- sys/dev/pci/agp.c | 8 +- sys/dev/pci/agp_ali.c | 6 +- sys/dev/pci/agp_i810.c | 8 +- sys/dev/pci/agp_intel.c | 10 +- sys/dev/pci/agp_sis.c | 6 +- sys/dev/pci/agp_via.c | 2 +- sys/dev/pci/agpreg.h | 2 +- sys/dev/pci/agpvar.h | 2 +- sys/dev/pci/ahc_pci.c | 16 +- sys/dev/pci/ahd_pci.c | 26 +- sys/dev/pci/drm/amd/amdgpu/ObjectID.h | 24 +- sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c | 2 +- sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c | 2 +- sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c | 2 +- sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c | 2 +- sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c | 4 +- sys/dev/pci/drm/amd/amdgpu/imu_v11_0.c | 8 +- sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c | 2 +- sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c | 2 +- sys/dev/pci/drm/amd/include/amd_shared.h | 2 +- sys/dev/pci/drm/amd/include/atomfirmware.h | 534 ++--- sys/dev/pci/drm/amd/include/atomfirmwareid.h | 4 +- sys/dev/pci/drm/amd/include/displayobject.h | 22 +- .../pci/drm/amd/include/navi10_ip_offset.h | 2 +- sys/dev/pci/drm/amd/include/pptable.h | 42 +- .../pm/powerplay/inc/vega12/smu9_driver_if.h | 10 +- sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 4 +- sys/dev/pci/drm/drm_drv.c | 12 +- sys/dev/pci/drm/drm_gem.c | 8 +- sys/dev/pci/drm/drm_linux.c | 36 +- sys/dev/pci/drm/drm_lock.c | 2 +- sys/dev/pci/drm/drm_managed.c | 2 +- sys/dev/pci/drm/drm_mm.c | 2 +- sys/dev/pci/drm/i915/gt/agp_intel_gtt.c | 2 +- sys/dev/pci/drm/i915/gt/shmem_utils.c | 2 +- sys/dev/pci/drm/include/linux/atomic.h | 6 +- sys/dev/pci/drm/include/linux/capability.h | 6 +- sys/dev/pci/drm/include/linux/dma-buf.h | 2 +- sys/dev/pci/drm/include/linux/file.h | 2 +- sys/dev/pci/drm/include/linux/interrupt.h | 2 +- sys/dev/pci/drm/include/linux/io.h | 2 +- sys/dev/pci/drm/include/linux/pci.h | 12 +- sys/dev/pci/drm/include/linux/rbtree.h | 2 +- sys/dev/pci/drm/include/linux/scatterlist.h | 2 +- sys/dev/pci/drm/include/linux/seqlock.h | 2 +- sys/dev/pci/drm/include/linux/string.h | 2 +- sys/dev/pci/drm/include/linux/swap.h | 4 +- sys/dev/pci/drm/include/linux/types.h | 10 +- sys/dev/pci/drm/include/linux/wait.h | 4 +- sys/dev/pci/drm/include/linux/ww_mutex.h | 4 +- sys/dev/pci/drm/include/uapi/drm/radeon_drm.h | 2 +- sys/dev/pci/drm/linux_sort.c | 4 +- sys/dev/pci/drm/radeon/ObjectID.h | 24 +- sys/dev/pci/drm/radeon/atombios.h | 1842 ++++++++--------- sys/dev/pci/if_aq_pci.c | 4 +- sys/dev/softraid_raid1c.c | 2 +- sys/dev/spdmem.c | 8 +- sys/lib/libz/zconf.h | 2 +- sys/lib/libz/zlib.h | 2 +- sys/netinet6/nd6.c | 22 +- sys/netinet6/nd6.h | 4 +- sys/netinet6/nd6_nbr.c | 11 +- usr.bin/wall/ttymsg.c | 8 +- usr.sbin/vmctl/vmctl.c | 4 +- 85 files changed, 1589 insertions(+), 1491 deletions(-) diff --git a/distrib/miniroot/install.sub b/distrib/miniroot/install.sub index ce362fd1d..9ab3330d5 100644 --- a/distrib/miniroot/install.sub +++ b/distrib/miniroot/install.sub @@ -1,5 +1,5 @@ #!/bin/ksh -# $OpenBSD: install.sub,v 1.1243 2023/04/25 14:20:13 kn Exp $ +# $OpenBSD: install.sub,v 1.1244 2023/05/02 15:55:58 deraadt Exp $ # # Copyright (c) 1997-2015 Todd Miller, Theo de Raadt, Ken Westerback # Copyright (c) 2015, Robert Peichaer @@ -3102,7 +3102,7 @@ Create a passphrase protected CRYPTO softraid volume to be used as root disk. __EOT diskinfo $(get_dkdevs);; '') ;; - no) return;; + n|no) return;; *) isin "$resp" $(get_dkdevs) && break echo 'No such disk.';; esac diff --git a/etc/skel/dot.version b/etc/skel/dot.version index 3d33be54f..70a024f66 100644 --- a/etc/skel/dot.version +++ b/etc/skel/dot.version @@ -1 +1 @@ -# SecBSD 1.3-df696c4: Mon May 2 00:00:00 UTC 2023 (Quetzalcoatl) +# SecBSD 1.3-8bfda6e: Mon May 2 00:00:00 UTC 2023 (Quetzalcoatl) diff --git a/gnu/usr.bin/binutils-2.17/binutils/configure b/gnu/usr.bin/binutils-2.17/binutils/configure index 2d8e0cb97..6c3d13260 100755 --- a/gnu/usr.bin/binutils-2.17/binutils/configure +++ b/gnu/usr.bin/binutils-2.17/binutils/configure @@ -3508,7 +3508,7 @@ else lt_cv_sys_max_cmd_len=8192; ;; - netbsd* | freebsd* | openbsd* | darwin* | dragonfly*) + netbsd* | freebsd* | openbsd* | darwin* | dragonfly* | secbsd*) # This has been around since 386BSD, at least. Likely further. if test -x /sbin/sysctl; then lt_cv_sys_max_cmd_len=`/sbin/sysctl -n kern.argmax` diff --git a/gnu/usr.bin/binutils-2.17/gas/configure.tgt b/gnu/usr.bin/binutils-2.17/gas/configure.tgt index 31b406a01..0932f6008 100644 --- a/gnu/usr.bin/binutils-2.17/gas/configure.tgt +++ b/gnu/usr.bin/binutils-2.17/gas/configure.tgt @@ -185,7 +185,7 @@ case ${generic_target} in esac ;; i386-*-openbsd[0-2].* | \ i386-*-openbsd3.[0-2]) fmt=aout em=obsd ;; - i386-*-openbsd* | i386-*-secbsd) fmt=elf em=obsd ;; + i386-*-openbsd* | i386-*-secbsd*) fmt=elf em=obsd ;; i386-*-linux*aout*) fmt=aout em=linux ;; i386-*-linux*oldld) fmt=aout em=linux ;; i386-*-linux*coff*) fmt=coff em=linux ;; diff --git a/lib/libcrypto/ec/ec_curve.c b/lib/libcrypto/ec/ec_curve.c index 9ab8c88f5..a8a1e4d52 100644 --- a/lib/libcrypto/ec/ec_curve.c +++ b/lib/libcrypto/ec/ec_curve.c @@ -1,4 +1,4 @@ -/* $OpenBSD: ec_curve.c,v 1.39 2023/05/01 17:53:01 tb Exp $ */ +/* $OpenBSD: ec_curve.c,v 1.41 2023/05/02 13:01:57 tb Exp $ */ /* * Written by Nils Larsch for the OpenSSL project. */ @@ -3000,11 +3000,10 @@ static const struct ec_list_element { static EC_GROUP * ec_group_new_from_data(const struct ec_list_element *curve) { - EC_GROUP *group = NULL; - EC_POINT *P = NULL; + EC_GROUP *group = NULL, *ret = NULL; + EC_POINT *generator = NULL; BN_CTX *ctx = NULL; BIGNUM *p, *a, *b, *x, *y, *order, *cofactor; - int ok = 0; if ((ctx = BN_CTX_new()) == NULL) { ECerror(ERR_R_MALLOC_FAILURE); @@ -3057,8 +3056,9 @@ ec_group_new_from_data(const struct ec_list_element *curve) ECerror(ERR_R_EC_LIB); goto err; } + EC_GROUP_set_curve_name(group, curve->nid); - if ((P = EC_POINT_new(group)) == NULL) { + if ((generator = EC_POINT_new(group)) == NULL) { ECerror(ERR_R_EC_LIB); goto err; } @@ -3070,7 +3070,7 @@ ec_group_new_from_data(const struct ec_list_element *curve) ECerror(ERR_R_BN_LIB); goto err; } - if (!EC_POINT_set_affine_coordinates(group, P, x, y, ctx)) { + if (!EC_POINT_set_affine_coordinates(group, generator, x, y, ctx)) { ECerror(ERR_R_EC_LIB); goto err; } @@ -3082,51 +3082,45 @@ ec_group_new_from_data(const struct ec_list_element *curve) ECerror(ERR_R_BN_LIB); goto err; } - if (!EC_GROUP_set_generator(group, P, order, cofactor)) { + if (!EC_GROUP_set_generator(group, generator, order, cofactor)) { ECerror(ERR_R_EC_LIB); goto err; } + if (curve->seed != NULL) { if (!EC_GROUP_set_seed(group, curve->seed, curve->seed_len)) { ECerror(ERR_R_EC_LIB); goto err; } } - ok = 1; + + ret = group; + group = NULL; + err: - if (!ok) { - EC_GROUP_free(group); - group = NULL; - } - EC_POINT_free(P); + EC_GROUP_free(group); + EC_POINT_free(generator); BN_CTX_end(ctx); BN_CTX_free(ctx); - return group; + return ret; } EC_GROUP * EC_GROUP_new_by_curve_name(int nid) { size_t i; - EC_GROUP *ret = NULL; if (nid <= 0) return NULL; for (i = 0; i < CURVE_LIST_LENGTH; i++) { - if (curve_list[i].nid == nid) { - ret = ec_group_new_from_data(&curve_list[i]); - break; - } + if (curve_list[i].nid == nid) + return ec_group_new_from_data(&curve_list[i]); } - if (ret == NULL) { - ECerror(EC_R_UNKNOWN_GROUP); - return NULL; - } - EC_GROUP_set_curve_name(ret, nid); - return ret; + ECerror(EC_R_UNKNOWN_GROUP); + return NULL; } size_t diff --git a/lib/libcrypto/man/X509_NAME_get_index_by_NID.3 b/lib/libcrypto/man/X509_NAME_get_index_by_NID.3 index 71dd98ce4..19a123a4a 100644 --- a/lib/libcrypto/man/X509_NAME_get_index_by_NID.3 +++ b/lib/libcrypto/man/X509_NAME_get_index_by_NID.3 @@ -1,4 +1,4 @@ -.\" $OpenBSD: X509_NAME_get_index_by_NID.3,v 1.13 2022/07/02 17:09:09 jsing Exp $ +.\" $OpenBSD: X509_NAME_get_index_by_NID.3,v 1.14 2023/05/02 14:13:05 beck Exp $ .\" OpenSSL aebb9aac Jul 19 09:27:53 2016 -0400 .\" .\" This file was written by Dr. Stephen Henson . @@ -49,7 +49,7 @@ .\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED .\" OF THE POSSIBILITY OF SUCH DAMAGE. .\" -.Dd $Mdocdate: July 2 2022 $ +.Dd $Mdocdate: May 2 2023 $ .Dt X509_NAME_GET_INDEX_BY_NID 3 .Os .Sh NAME @@ -136,22 +136,32 @@ run from 0 to .Fn X509_NAME_get_text_by_NID and .Fn X509_NAME_get_text_by_OBJ -retrieve the "text" from the first entry in +retrieve the bytes encoded as UTF-8 from the first entry in .Fa name which matches .Fa nid or .Fa obj . -At most -.Fa len -bytes will be written and the text written to -.Fa buf -will be NUL terminated. If .Fa buf is .Dv NULL , nothing is written, but the return value is calculated as usual. +If +.Fa buf +is not +.Dv NULL , +no more than +.Fa len +bytes will be written and the text written to +.Fa buf +will be NUL terminated. +.Pp +Nothing is written and it is a failure if +.Fa len +is not large enough to hold the NUL byte terminated UTF-8 encoding of +the text, or if the UTF-8 encoding ot the text would contins a NUL +byte. .Pp All relevant .Dv NID_* @@ -189,8 +199,8 @@ if the index is invalid. .Fn X509_NAME_get_text_by_NID and .Fn X509_NAME_get_text_by_OBJ -return the length of the output string written, not counting the -terminating NUL, or -1 if no match is found. +return the length of the output UTF-8 string written, not counting the +terminating NUL, or -1 in the case of an error or no match being found. .Pp In some cases of failure of .Fn X509_NAME_get_index_by_NID diff --git a/lib/libcrypto/pkcs7/pk7_mime.c b/lib/libcrypto/pkcs7/pk7_mime.c index 68767db7c..f00e18c7e 100644 --- a/lib/libcrypto/pkcs7/pk7_mime.c +++ b/lib/libcrypto/pkcs7/pk7_mime.c @@ -1,4 +1,4 @@ -/* $OpenBSD: pk7_mime.c,v 1.17 2023/04/26 14:25:58 tb Exp $ */ +/* $OpenBSD: pk7_mime.c,v 1.19 2023/05/02 09:56:12 tb Exp $ */ /* Written by Dr Stephen N Henson (steve@openssl.org) for the OpenSSL * project. */ @@ -71,8 +71,7 @@ LCRYPTO_ALIAS(BIO_new_PKCS7); int i2d_PKCS7_bio_stream(BIO *out, PKCS7 *p7, BIO *in, int flags) { - return i2d_ASN1_bio_stream(out, (ASN1_VALUE *)p7, in, flags, - &PKCS7_it); + return i2d_ASN1_bio_stream(out, (ASN1_VALUE *)p7, in, flags, &PKCS7_it); } LCRYPTO_ALIAS(i2d_PKCS7_bio_stream); @@ -87,16 +86,14 @@ LCRYPTO_ALIAS(PEM_write_bio_PKCS7_stream); int SMIME_write_PKCS7(BIO *bio, PKCS7 *p7, BIO *data, int flags) { - STACK_OF(X509_ALGOR) *mdalgs; - int ctype_nid = OBJ_obj2nid(p7->type); - if (ctype_nid == NID_pkcs7_signed) + STACK_OF(X509_ALGOR) *mdalgs = NULL; + int ctype_nid; + + if ((ctype_nid = OBJ_obj2nid(p7->type)) == NID_pkcs7_signed) mdalgs = p7->d.sign->md_algs; - else - mdalgs = NULL; flags ^= SMIME_OLDMIME; - return SMIME_write_ASN1(bio, (ASN1_VALUE *)p7, data, flags, ctype_nid, NID_undef, mdalgs, &PKCS7_it); } diff --git a/lib/libcrypto/x509/x509name.c b/lib/libcrypto/x509/x509name.c index a6e4dbef8..3c9e224c1 100644 --- a/lib/libcrypto/x509/x509name.c +++ b/lib/libcrypto/x509/x509name.c @@ -1,4 +1,4 @@ -/* $OpenBSD: x509name.c,v 1.31 2023/02/16 08:38:17 tb Exp $ */ +/* $OpenBSD: x509name.c,v 1.32 2023/05/02 14:13:05 beck Exp $ */ /* Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com) * All rights reserved. * @@ -66,6 +66,7 @@ #include #include +#include "bytestring.h" #include "x509_local.h" int @@ -84,21 +85,37 @@ int X509_NAME_get_text_by_OBJ(X509_NAME *name, const ASN1_OBJECT *obj, char *buf, int len) { - int i; + unsigned char *text = NULL; ASN1_STRING *data; + int i, text_len; + int ret = -1; + CBS cbs; i = X509_NAME_get_index_by_OBJ(name, obj, -1); if (i < 0) - return (-1); + goto err; data = X509_NAME_ENTRY_get_data(X509_NAME_get_entry(name, i)); - i = (data->length > (len - 1)) ? (len - 1) : data->length; - if (buf == NULL) - return (data->length); - if (i >= 0) { - memcpy(buf, data->data, i); - buf[i] = '\0'; + /* + * Fail if we cannot encode as UTF-8, or if the UTF-8 encoding of the + * string contains a 0 byte, because mortal callers seldom handle the + * length difference correctly + */ + if ((text_len = ASN1_STRING_to_UTF8(&text, data)) < 0) + goto err; + CBS_init(&cbs, text, text_len); + if (CBS_contains_zero_byte(&cbs)) + goto err; + /* We still support the "pass NULL to find out how much" API */ + if (buf != NULL) { + if (!CBS_write_bytes(&cbs, buf, len - 1, NULL)) + goto err; + /* It must be a C string */ + buf[text_len] = '\0'; } - return (i); + ret = text_len; + err: + free(text); + return (ret); } LCRYPTO_ALIAS(X509_NAME_get_text_by_OBJ); diff --git a/lib/libz/README b/lib/libz/README index a9b1b053d..a77433e28 100644 --- a/lib/libz/README +++ b/lib/libz/README @@ -35,12 +35,11 @@ The changes made in version 1.2.13.1 are documented in the file ChangeLog. Unsupported third party contributions are provided in directory contrib/ . -zlib is available in Java using the java.util.zip package, documented at -http://java.sun.com/developer/technicalArticles/Programming/compression/ . +zlib is available in Java using the java.util.zip package. Follow the API +Documentation link at: https://docs.oracle.com/search/?q=java.util.zip . -A Perl interface to zlib written by Paul Marquess is available -at CPAN (Comprehensive Perl Archive Network) sites, including -http://search.cpan.org/~pmqs/IO-Compress-Zlib/ . +A Perl interface to zlib and bzip2 written by Paul Marquess +can be found at https://github.com/pmqs/IO-Compress . A Python interface to zlib written by A.M. Kuchling is available in Python 1.5 and later versions, see diff --git a/lib/libz/zconf.h b/lib/libz/zconf.h index 6ae145896..7c1dc4fc6 100644 --- a/lib/libz/zconf.h +++ b/lib/libz/zconf.h @@ -522,7 +522,7 @@ typedef uLong FAR uLongf; #if !defined(_WIN32) && defined(Z_LARGE64) # define z_off64_t off64_t #else -# if defined(_WIN32) && !defined(__GNUC__) && !defined(Z_SOLO) +# if defined(_WIN32) && !defined(__GNUC__) # define z_off64_t __int64 # else # define z_off64_t z_off_t diff --git a/lib/libz/zlib.h b/lib/libz/zlib.h index 33a9e9ddc..f0c514483 100644 --- a/lib/libz/zlib.h +++ b/lib/libz/zlib.h @@ -729,7 +729,7 @@ ZEXTERN int ZEXPORT deflateParams(z_streamp strm, Then no more input data should be provided before the deflateParams() call. If this is done, the old level and strategy will be applied to the data compressed before deflateParams(), and the new level and strategy will be - applied to the the data compressed after deflateParams(). + applied to the data compressed after deflateParams(). deflateParams returns Z_OK on success, Z_STREAM_ERROR if the source stream state was inconsistent or if a parameter was invalid, or Z_BUF_ERROR if diff --git a/regress/lib/libcrypto/bio/bio_asn1.c b/regress/lib/libcrypto/bio/bio_asn1.c index abb164237..92a18d03a 100644 --- a/regress/lib/libcrypto/bio/bio_asn1.c +++ b/regress/lib/libcrypto/bio/bio_asn1.c @@ -1,4 +1,4 @@ -/* $OpenBSD: bio_asn1.c,v 1.3 2023/04/25 19:48:24 tb Exp $ */ +/* $OpenBSD: bio_asn1.c,v 1.4 2023/05/02 09:30:37 tb Exp $ */ /* * Copyright (c) 2023 Theo Buehler @@ -125,8 +125,8 @@ test_prefix_leak(void) if ((bio_out = BIO_new(BIO_s_mem())) == NULL) goto err; - if (!i2d_ASN1_bio_stream(bio_out, (ASN1_VALUE *)pkcs7, bio_in, - SMIME_STREAM | SMIME_BINARY, &PKCS7_it)) + if (!i2d_PKCS7_bio_stream(bio_out, pkcs7, bio_in, + SMIME_STREAM | SMIME_BINARY)) goto err; if (set_me != 1) { diff --git a/regress/lib/libcrypto/man/check_complete.pl b/regress/lib/libcrypto/man/check_complete.pl index f4b63a6f2..b937c1960 100755 --- a/regress/lib/libcrypto/man/check_complete.pl +++ b/regress/lib/libcrypto/man/check_complete.pl @@ -272,7 +272,7 @@ try_again: print "D- $line\n" if $verbose; next; } - if ($id =~ /^(?:ASN1|BN|X509(?:V3)?)_[FR]_\w+$/) { + if ($id =~ /^(?:ASN1|BIO|BN|X509(?:V3)?)_[FR]_\w+$/) { print "D- $line\n" if $verbose; next; } diff --git a/regress/lib/libcrypto/x509/x509_asn1.c b/regress/lib/libcrypto/x509/x509_asn1.c index 146b0aba7..1ce8ed3aa 100644 --- a/regress/lib/libcrypto/x509/x509_asn1.c +++ b/regress/lib/libcrypto/x509/x509_asn1.c @@ -1,4 +1,4 @@ -/* $OpenBSD: x509_asn1.c,v 1.16 2023/05/01 11:02:23 job Exp $ */ +/* $OpenBSD: x509_asn1.c,v 1.17 2023/05/02 14:13:05 beck Exp $ */ /* * Copyright (c) 2023 Job Snijders * @@ -512,13 +512,88 @@ test_x509_req_setters(void) return failed; } -int main(void) +static const struct testcase { + char *data; + int len; + int len_to_pass; + int encode_type; + int expected_result; + char *expected_string; +} testCases[] = { + /* should work */ + {"fozzie", 6, 80, MBSTRING_ASC, 6, "fozzie"}, + /* should work */ + {"fozzie", 6, -1, MBSTRING_ASC, 6, ""}, + /* should fail, truncation */ + {"muppet", 6, 5, MBSTRING_ASC, -1, ""}, + /* should fail, contains 0 byte */ + {"g\0nzo", 5, 80, MBSTRING_ASC, -1, ""}, + /* should fail, can't encode as utf-8 */ + {"\x30\x00", 2, 80, V_ASN1_SEQUENCE, -1, ""}, +}; + +#define NUM_TEST_CASES (sizeof(testCases) / sizeof(testCases[0])) + +static int +test_x509_name_get(void) +{ + int failed = 0; + size_t i; + + for (i = 0; i < NUM_TEST_CASES; i++) { + const struct testcase *test = testCases + i; + X509_NAME_ENTRY *entry = NULL; + X509_NAME *name = NULL; + char textbuf[80]; + int result; + + textbuf[0] = '\0'; + if ((name = X509_NAME_new()) == NULL) + err(1, "X509_NAME_new"); + if ((entry = X509_NAME_ENTRY_new()) == NULL) + err(1, "X509_NAME_ENTRY_new"); + if (!X509_NAME_ENTRY_set_object(entry, + OBJ_nid2obj(NID_commonName))) + err(1, "X509_NAME_ENTRY_set_object"); + if (!X509_NAME_ENTRY_set_data(entry, test->encode_type, + test->data, test->len)) + err(1, "X509_NAME_ENTRY_set_data"); + if (!X509_NAME_add_entry(name, entry, -1, 0)) + err(1, "X509_NAME_add_entry"); + if (test->len_to_pass == -1) + result = X509_NAME_get_text_by_NID(name, NID_commonName, + NULL, 0); + else + result = X509_NAME_get_text_by_NID(name, NID_commonName, + textbuf, test->len_to_pass); + if (result != test->expected_result) { + fprintf(stderr, + "Test %zu X509_GET_text_by_NID returned %d," + "expected %d\n", i, result, test->expected_result); + failed++; + } + if (result != -1 && + strcmp(test->expected_string, textbuf) != 0) { + fprintf(stderr, + "Test %zu, X509_GET_text_by_NID returned bytes do" + "not match \n", i); + failed++; + } + X509_NAME_ENTRY_free(entry); + X509_NAME_free(name); + } + return failed; +} + +int +main(void) { int failed = 0; failed |= test_x509_setters(); /* failed |= */ test_x509_crl_setters(); /* failed |= */ test_x509_req_setters(); + failed |= test_x509_name_get(); OPENSSL_cleanup(); diff --git a/share/misc/airport b/share/misc/airport index 422187aa7..933479484 100644 --- a/share/misc/airport +++ b/share/misc/airport @@ -1,4 +1,4 @@ -# $OpenBSD: airport,v 1.89 2023/04/21 00:37:10 kn Exp $ +# $OpenBSD: airport,v 1.90 2023/05/02 08:48:06 stsp Exp $ # @(#)airport 8.1 (Berkeley) 6/8/93 # # Some of this information from the Airport Search Engine at @@ -374,6 +374,7 @@ CPR:Casper/Natrone County International, Wyoming, USA CPT:Cape Town International, Cape Town, South Africa CRD:Comodoro Rivadavia, Chubut, Argentina CRI:Crooked Island, Bahamas +CRL:Brussels South / Gosselies, Charleroi, Belgium CRM:Charleston (WV) Yeager, South Carolina, USA CRP:Corpus Christi International, Texas, USA CRU:Carriacou Island, Grenada diff --git a/sys/dev/acpi/abl.c b/sys/dev/acpi/abl.c index adb49b4bc..13b644d7f 100644 --- a/sys/dev/acpi/abl.c +++ b/sys/dev/acpi/abl.c @@ -86,7 +86,7 @@ abl_match(struct device *parent, void *match, void *aux) { struct acpi_attach_args *aa = aux; struct cfdata *cf = match; - + return acpi_matchhids(aa, abl_hids, cf->cf_driver->cd_name); } diff --git a/sys/dev/acpi/acpi_x86.c b/sys/dev/acpi/acpi_x86.c index 7a07e482a..0e1e44719 100644 --- a/sys/dev/acpi/acpi_x86.c +++ b/sys/dev/acpi/acpi_x86.c @@ -134,7 +134,7 @@ checklids(struct acpi_softc *sc) if (lids == 0 && lid_action != 0) return EAGAIN; return 0; -} +} int diff --git a/sys/dev/acpi/acpiec.c b/sys/dev/acpi/acpiec.c index 5ef24d517..e6b362941 100644 --- a/sys/dev/acpi/acpiec.c +++ b/sys/dev/acpi/acpiec.c @@ -259,7 +259,7 @@ acpiec_match(struct device *parent, void *match, void *aux) struct acpi_softc *acpisc = (struct acpi_softc *)parent; /* Check for early ECDT table attach */ - if (ecdt && + if (ecdt && !memcmp(ecdt->hdr.signature, ECDT_SIG, sizeof(ECDT_SIG) - 1)) return (1); if (acpisc->sc_ec) diff --git a/sys/dev/acpi/acpithinkpad.c b/sys/dev/acpi/acpithinkpad.c index d749588f2..deddede9e 100644 --- a/sys/dev/acpi/acpithinkpad.c +++ b/sys/dev/acpi/acpithinkpad.c @@ -435,7 +435,7 @@ thinkpad_hotkey(struct aml_node *node, int notify_type, void *arg) case THINKPAD_BUTTON_SUSPEND: #ifndef SMALL_KERNEL if (acpi_record_event(sc->sc_acpi, APM_USER_SUSPEND_REQ)) - acpi_addtask(sc->sc_acpi, acpi_sleep_task, + acpi_addtask(sc->sc_acpi, acpi_sleep_task, sc->sc_acpi, SLEEP_SUSPEND); #endif break; @@ -456,7 +456,7 @@ thinkpad_hotkey(struct aml_node *node, int notify_type, void *arg) case THINKPAD_BUTTON_HIBERNATE: #if defined(HIBERNATE) && !defined(SMALL_KERNEL) if (acpi_record_event(sc->sc_acpi, APM_USER_HIBERNATE_REQ)) - acpi_addtask(sc->sc_acpi, acpi_sleep_task, + acpi_addtask(sc->sc_acpi, acpi_sleep_task, sc->sc_acpi, SLEEP_HIBERNATE); #endif break; @@ -472,12 +472,12 @@ thinkpad_hotkey(struct aml_node *node, int notify_type, void *arg) break; case THINKPAD_PORT_REPL_DOCKED: sc->sc_sens[THINKPAD_SENSOR_PORTREPL].value = 1; - sc->sc_sens[THINKPAD_SENSOR_PORTREPL].status = + sc->sc_sens[THINKPAD_SENSOR_PORTREPL].status = SENSOR_S_OK; break; case THINKPAD_PORT_REPL_UNDOCKED: sc->sc_sens[THINKPAD_SENSOR_PORTREPL].value = 0; - sc->sc_sens[THINKPAD_SENSOR_PORTREPL].status = + sc->sc_sens[THINKPAD_SENSOR_PORTREPL].status = SENSOR_S_OK; break; default: diff --git a/sys/dev/kstat.c b/sys/dev/kstat.c index 073f61a2c..5da636a06 100644 --- a/sys/dev/kstat.c +++ b/sys/dev/kstat.c @@ -230,7 +230,7 @@ kstatioc_leave(struct kstat_req *ksreq, struct kstat *ks) ksreq->ks_interval = ks->ks_interval; if (ksreq->ks_data == NULL) { - /* userland doesn't want actual data, so shortcut */ + /* userland doesn't want actual data, so shortcut */ kstat_enter(ks); ksreq->ks_datalen = ks->ks_datalen; ksreq->ks_updated = ks->ks_updated; @@ -633,7 +633,7 @@ kstat_remove(struct kstat *ks) KASSERTMSG(ks->ks_state == KSTAT_S_INSTALLED, "kstat %p %s:%u:%s:%u is not installed", ks, ks->ks_provider, ks->ks_instance, ks->ks_name, ks->ks_unit); - + ks->ks_state = KSTAT_S_CREATED; rw_exit_write(&kstat_lock); } diff --git a/sys/dev/pci/aac_pci.c b/sys/dev/pci/aac_pci.c index 480ad4e15..52840060d 100644 --- a/sys/dev/pci/aac_pci.c +++ b/sys/dev/pci/aac_pci.c @@ -285,7 +285,7 @@ aac_pci_attach(parent, self, aux) printf("%s\n", intrstr); sc->aac_dmat = pa->pa_dmat; - + for (m = aac_identifiers; m->vendor != 0; m++) if (m->vendor == PCI_VENDOR(pa->pa_id) && m->device == PCI_PRODUCT(pa->pa_id)) { diff --git a/sys/dev/pci/agp.c b/sys/dev/pci/agp.c index a0bab2839..bf6fa2774 100644 --- a/sys/dev/pci/agp.c +++ b/sys/dev/pci/agp.c @@ -64,7 +64,7 @@ agpbus_probe(struct agp_attach_args *aa) struct pci_attach_args *pa = aa->aa_pa; if (strncmp(aa->aa_busname, "agp", 3) == 0 && - PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && + PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_HOST) return (1); return (0); @@ -215,7 +215,7 @@ agp_generic_enable(struct agp_softc *sc, u_int32_t mode) struct pci_attach_args pa; pcireg_t tstatus, mstatus, command; int rq, sba, fw, rate, capoff; - + if (pci_find_device(&pa, agpvga_match) == 0 || pci_get_capability(pa.pa_pc, pa.pa_tag, PCI_CAP_AGP, &capoff, NULL) == 0) { @@ -359,7 +359,7 @@ agp_acquire(void *dev) { struct agp_softc *sc = (struct agp_softc *)dev; - if (sc->sc_chipc == NULL) + if (sc->sc_chipc == NULL) return (EINVAL); if (sc->sc_state != AGP_ACQUIRE_FREE) @@ -377,7 +377,7 @@ agp_release(void *dev) if (sc->sc_state == AGP_ACQUIRE_FREE) return (0); - if (sc->sc_state != AGP_ACQUIRE_KERNEL) + if (sc->sc_state != AGP_ACQUIRE_KERNEL) return (EBUSY); sc->sc_state = AGP_ACQUIRE_FREE; diff --git a/sys/dev/pci/agp_ali.c b/sys/dev/pci/agp_ali.c index 308299f66..db2c64316 100644 --- a/sys/dev/pci/agp_ali.c +++ b/sys/dev/pci/agp_ali.c @@ -96,7 +96,7 @@ agp_ali_probe(struct device *parent, void *match, void *aux) return (0); } -void +void agp_ali_attach(struct device *parent, struct device *self, void *aux) { struct agp_ali_softc *asc = (struct agp_ali_softc *)self; @@ -135,7 +135,7 @@ agp_ali_attach(struct device *parent, struct device *self, void *aux) reg = pci_conf_read(asc->asc_pc, asc->asc_tag, AGP_ALI_ATTBASE); reg = (reg & 0xff) | gatt->ag_physical; pci_conf_write(asc->asc_pc, asc->asc_tag, AGP_ALI_ATTBASE, reg); - + /* Enable the TLB. */ reg = pci_conf_read(asc->asc_pc, asc->asc_tag, AGP_ALI_TLBCTRL); reg = (reg & ~0xff) | 0x10; @@ -179,7 +179,7 @@ agp_ali_restore(struct agp_ali_softc *asc) /* Install the gatt and aperture size. */ pci_conf_write(asc->asc_pc, asc->asc_tag, AGP_ALI_ATTBASE, asc->asc_attbase); - + /* Enable the TLB. */ pci_conf_write(asc->asc_pc, asc->asc_tag, AGP_ALI_TLBCTRL, asc->asc_tlbctrl); diff --git a/sys/dev/pci/agp_i810.c b/sys/dev/pci/agp_i810.c index f0863f0b4..274e707e2 100644 --- a/sys/dev/pci/agp_i810.c +++ b/sys/dev/pci/agp_i810.c @@ -59,7 +59,7 @@ /* I810/I815 only, memory is in dcache */ #define INTEL_LOCAL 0x2 /* Memory is snooped, must not be accessed through gtt from the cpu. */ -#define INTEL_COHERENT 0x6 +#define INTEL_COHERENT 0x6 enum { CHIP_NONE = 0, /* not integrated graphics */ @@ -194,7 +194,7 @@ agp_i810_get_chiptype(struct pci_attach_args *pa) return (CHIP_IRONLAKE); break; } - + return (CHIP_NONE); } @@ -379,7 +379,7 @@ agp_i810_attach(struct device *parent, struct device *self, void *aux) /* FALLTHROUGH */ case CHIP_I915: /* FALLTHROUGH */ - case CHIP_I965: + case CHIP_I965: /* FALLTHROUGH */ case CHIP_G33: /* FALLTHROUGH */ @@ -559,7 +559,7 @@ agp_i810_configure(struct agp_i810_softc *isc) tmp = isc->isc_apaddr; if (isc->chiptype == CHIP_I810) { tmp += isc->dcache_size; - } else { + } else { tmp += isc->stolen << AGP_PAGE_SHIFT; } diff --git a/sys/dev/pci/agp_intel.c b/sys/dev/pci/agp_intel.c index 628b12218..0ff430869 100644 --- a/sys/dev/pci/agp_intel.c +++ b/sys/dev/pci/agp_intel.c @@ -59,7 +59,7 @@ struct agp_intel_softc { CHIP_I845, CHIP_I850, CHIP_I865 - } chiptype; + } chiptype; /* registers saved during a suspend/resume cycle. */ pcireg_t savectrl; pcireg_t savecmd; @@ -115,7 +115,7 @@ agp_intel_probe(struct device *parent, void *match, void *aux) case PCI_PRODUCT_INTEL_82840_HB: case PCI_PRODUCT_INTEL_82845_HB: case PCI_PRODUCT_INTEL_82845G_HB: - case PCI_PRODUCT_INTEL_82850_HB: + case PCI_PRODUCT_INTEL_82850_HB: case PCI_PRODUCT_INTEL_82855PM_HB: case PCI_PRODUCT_INTEL_82855GM_HB: case PCI_PRODUCT_INTEL_82860_HB: @@ -202,7 +202,7 @@ agp_intel_attach(struct device *parent, struct device *self, void *aux) /* Install the gatt. */ pci_conf_write(pa->pa_pc, pa->pa_tag, AGP_INTEL_ATTBASE, gatt->ag_physical); - + /* Enable the GLTB and setup the control register. */ switch (isc->chiptype) { case CHIP_I443: @@ -262,7 +262,7 @@ agp_intel_attach(struct device *parent, struct device *self, void *aux) pci_conf_write(isc->isc_pc, isc->isc_tag, AGP_INTEL_ERRCMD, reg); } - + isc->agpdev = (struct agp_softc *)agp_attach_bus(pa, &agp_intel_methods, isc->isc_apaddr, isc->isc_apsize, &isc->dev); return; @@ -329,7 +329,7 @@ agp_intel_restore(struct agp_intel_softc *isc) /* Install the gatt. */ pci_conf_write(isc->isc_pc, isc->isc_tag, AGP_INTEL_ATTBASE, isc->gatt->ag_physical); - + /* Enable the GLTB and setup the control register. */ switch (isc->chiptype) { case CHIP_I443: diff --git a/sys/dev/pci/agp_sis.c b/sys/dev/pci/agp_sis.c index f0d59d054..145dcfe1d 100644 --- a/sys/dev/pci/agp_sis.c +++ b/sys/dev/pci/agp_sis.c @@ -135,7 +135,7 @@ agp_sis_attach(struct device *parent, struct device *self, void *aux) /* Install the gatt. */ pci_conf_write(ssc->ssc_pc, ssc->ssc_tag, AGP_SIS_ATTBASE, gatt->ag_physical); - + /* Enable the aperture and auto-tlb-inval */ reg = pci_conf_read(ssc->ssc_pc, ssc->ssc_tag, AGP_SIS_WINCTRL); reg |= (0x05 << 24) | 3; @@ -176,7 +176,7 @@ agp_sis_restore(struct agp_sis_softc *ssc) /* Install the gatt. */ pci_conf_write(ssc->ssc_pc, ssc->ssc_tag, AGP_SIS_ATTBASE, ssc->gatt->ag_physical); - + /* * Enable the aperture, reset the aperture size and enable and * auto-tlb-inval. @@ -217,7 +217,7 @@ agp_sis_set_aperture(void *sc, bus_size_t aperture) gws = ffs(aperture / 4*1024*1024) - 1; - reg = pci_conf_read(ssc->ssc_pc, ssc->ssc_tag, AGP_SIS_WINCTRL); + reg = pci_conf_read(ssc->ssc_pc, ssc->ssc_tag, AGP_SIS_WINCTRL); reg &= ~0x00000070; reg |= gws << 4; pci_conf_write(ssc->ssc_pc, ssc->ssc_tag, AGP_SIS_WINCTRL, reg); diff --git a/sys/dev/pci/agp_via.c b/sys/dev/pci/agp_via.c index 75828c10a..d0e27d5ef 100644 --- a/sys/dev/pci/agp_via.c +++ b/sys/dev/pci/agp_via.c @@ -238,7 +238,7 @@ agp_via_get_aperture(void *sc) struct agp_via_softc *vsc = sc; bus_size_t apsize; - apsize = pci_conf_read(vsc->vsc_pc, vsc->vsc_tag, + apsize = pci_conf_read(vsc->vsc_pc, vsc->vsc_tag, vsc->regs[REG_APSIZE]) & 0x1f; /* diff --git a/sys/dev/pci/agpreg.h b/sys/dev/pci/agpreg.h index 1d8924d58..0f1e2b920 100644 --- a/sys/dev/pci/agpreg.h +++ b/sys/dev/pci/agpreg.h @@ -210,7 +210,7 @@ #define AGP_I810_MISCC_RPTC 0x00c0 #define AGP_I810_MISCC_RPTC_NOLIMIT 0x0000 #define AGP_I810_MISCC_RPTC_62 0x0040 -#define AGP_I810_MISCC_RPTC_50 0x0080 +#define AGP_I810_MISCC_RPTC_50 0x0080 #define AGP_I810_MISCC_RPTC_37 0x00c0 /* diff --git a/sys/dev/pci/agpvar.h b/sys/dev/pci/agpvar.h index 522d1dd1b..569df51f2 100644 --- a/sys/dev/pci/agpvar.h +++ b/sys/dev/pci/agpvar.h @@ -105,7 +105,7 @@ struct agp_softc { pcireg_t sc_id; int sc_opened; - int sc_capoff; + int sc_capoff; int sc_nextid; /* next mem block id */ enum agp_acquire_state sc_state; diff --git a/sys/dev/pci/ahc_pci.c b/sys/dev/pci/ahc_pci.c index 373e87e89..6f95e9b20 100644 --- a/sys/dev/pci/ahc_pci.c +++ b/sys/dev/pci/ahc_pci.c @@ -459,7 +459,7 @@ const struct ahc_pci_identity ahc_pci_ident_table [] = ID_ALL_MASK, ahc_aic7892_setup }, - /* aic7895 based controllers */ + /* aic7895 based controllers */ { ID_AHA_2940U_DUAL, ID_ALL_MASK, @@ -480,7 +480,7 @@ const struct ahc_pci_identity ahc_pci_ident_table [] = ID_AIC7895_ARO_MASK, ahc_aic7895_setup }, - /* aic7896/97 based controllers */ + /* aic7896/97 based controllers */ { ID_AHA_3950U2B_0, ID_ALL_MASK, @@ -506,7 +506,7 @@ const struct ahc_pci_identity ahc_pci_ident_table [] = ID_ALL_MASK, ahc_aic7896_setup }, - /* aic7899 based controllers */ + /* aic7899 based controllers */ { ID_AHA_3960D, ID_ALL_MASK, @@ -665,7 +665,7 @@ ahc_find_pci_device(pcireg_t id, pcireg_t subid, u_int func) * ID as valid. */ if (func > 0 - && ahc_9005_subdevinfo_valid(PCI_VENDOR(id), PCI_PRODUCT(id), + && ahc_9005_subdevinfo_valid(PCI_VENDOR(id), PCI_PRODUCT(id), PCI_VENDOR(subid), PCI_PRODUCT(subid)) && SUBID_9005_MFUNCENB(PCI_PRODUCT(subid)) == 0) return (NULL); @@ -834,7 +834,7 @@ ahc_pci_attach(struct device *parent, struct device *self, void *aux) ahc_name(ahc)); devconfig |= DACEN; } - + /* Ensure that pci error generation, a test feature, is disabled. */ devconfig |= PCIERRGENDIS; @@ -963,7 +963,7 @@ ahc_pci_attach(struct device *parent, struct device *self, void *aux) M_NOWAIT | M_ZERO); if (ahc->seep_config == NULL) goto error_out; - + /* See if we have a SEEPROM and perform auto-term */ ahc_check_extport(ahc, &sxfrctl1); @@ -1208,7 +1208,7 @@ ahc_probe_ext_scbram(struct ahc_softc *ahc) fast = FALSE; large = FALSE; num_scbs = 0; - + if (ahc_ext_scbram_present(ahc) == 0) goto done; @@ -1402,7 +1402,7 @@ ahc_pci_intr(struct ahc_softc *ahc) if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { printf("%s: Latched PCIERR interrupt with " - "no status bits set\n", ahc_name(ahc)); + "no status bits set\n", ahc_name(ahc)); } else { ahc_outb(ahc, CLRINT, CLRPARERR); } diff --git a/sys/dev/pci/ahd_pci.c b/sys/dev/pci/ahd_pci.c index b6b6affaf..171579a72 100644 --- a/sys/dev/pci/ahd_pci.c +++ b/sys/dev/pci/ahd_pci.c @@ -170,7 +170,7 @@ const struct ahd_pci_identity ahd_pci_ident_table[] = ID_ALL_MASK, ahd_aic7901A_setup }, - /* aic7902 based controllers */ + /* aic7902 based controllers */ { ID_AHA_29320, ID_ALL_MASK, @@ -240,7 +240,7 @@ const struct ahd_pci_identity ahd_pci_ident_table[] = }; const u_int ahd_num_pci_devs = NUM_ELEMENTS(ahd_pci_ident_table); - + #define DEVCONFIG 0x40 #define PCIXINITPAT 0x0000E000ul #define PCIXINIT_PCI33_66 0x0000E000ul @@ -342,7 +342,7 @@ ahd_pci_attach(struct device *parent, struct device *self, void *aux) pci_intr_handle_t ih; const char *intrstr; pcireg_t devconfig, memtype, subid; - uint16_t device, subvendor; + uint16_t device, subvendor; int error, ioh_valid, ioh2_valid, l, memh_valid; ahd->dev_softc = pa; @@ -373,10 +373,10 @@ ahd_pci_attach(struct device *parent, struct device *self, void *aux) error = entry->setup(ahd, pa); if (error != 0) return; - + /* XXX ahc on sparc64 needs this twice */ devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); - + if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) { ahd->chip |= AHD_PCI; /* Disable PCIX workarounds when running in PCI mode. */ @@ -482,7 +482,7 @@ ahd_pci_attach(struct device *parent, struct device *self, void *aux) devconfig |= DACEN; pci_conf_write(pa->pa_pc, pa->pa_tag, DEVCONFIG, devconfig); } - + ahd_softc_init(ahd); /* @@ -514,7 +514,7 @@ ahd_pci_attach(struct device *parent, struct device *self, void *aux) } if (intrstr != NULL) printf(": %s\n", intrstr); - + /* Get the size of the cache */ ahd->pci_cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); ahd->pci_cachesize *= 4; @@ -668,7 +668,7 @@ ahd_check_extport(struct ahd_softc *ahd) /* * Fetch VPD for this function and parse it. */ - if (bootverbose) + if (bootverbose) printf("%s: Reading VPD from SEEPROM...", ahd_name(ahd)); @@ -681,12 +681,12 @@ ahd_check_extport(struct ahd_softc *ahd) /*bytestream*/TRUE); if (error == 0) error = ahd_parse_vpddata(ahd, &vpd); - if (bootverbose) + if (bootverbose) printf("%s: VPD parsing %s\n", ahd_name(ahd), error == 0 ? "successful" : "failed"); - if (bootverbose) + if (bootverbose) printf("%s: Reading SEEPROM...", ahd_name(ahd)); /* Address is always in units of 16bit words */ @@ -941,7 +941,7 @@ ahd_pci_intr(struct ahd_softc *ahd) u_int intstat; u_int i; u_int reg; - + intstat = ahd_inb(ahd, INTSTAT); if ((intstat & SPLTINT) != 0) @@ -965,7 +965,7 @@ ahd_pci_intr(struct ahd_softc *ahd) for (i = 0; i < 8; i++) { u_int bit; - + if (i == 5) continue; @@ -980,7 +980,7 @@ ahd_pci_intr(struct ahd_softc *ahd) pci_status_strings[bit], pci_status_source[i]); } - } + } } pci_status1 = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG , pci_status1); diff --git a/sys/dev/pci/drm/amd/amdgpu/ObjectID.h b/sys/dev/pci/drm/amd/amdgpu/ObjectID.h index a0f0a17e2..361559756 100644 --- a/sys/dev/pci/drm/amd/amdgpu/ObjectID.h +++ b/sys/dev/pci/drm/amd/amdgpu/ObjectID.h @@ -1,5 +1,5 @@ /* -* Copyright 2006-2007 Advanced Micro Devices, Inc. +* Copyright 2006-2007 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -37,13 +37,13 @@ #define GRAPH_OBJECT_TYPE_CONNECTOR 0x3 #define GRAPH_OBJECT_TYPE_ROUTER 0x4 /* deleted */ -#define GRAPH_OBJECT_TYPE_DISPLAY_PATH 0x6 +#define GRAPH_OBJECT_TYPE_DISPLAY_PATH 0x6 #define GRAPH_OBJECT_TYPE_GENERIC 0x7 /****************************************************/ /* Encoder Object ID Definition */ /****************************************************/ -#define ENCODER_OBJECT_ID_NONE 0x00 +#define ENCODER_OBJECT_ID_NONE 0x00 /* Radeon Class Display Hardware */ #define ENCODER_OBJECT_ID_INTERNAL_LVDS 0x01 @@ -96,7 +96,7 @@ /****************************************************/ /* Connector Object ID Definition */ /****************************************************/ -#define CONNECTOR_OBJECT_ID_NONE 0x00 +#define CONNECTOR_OBJECT_ID_NONE 0x00 #define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I 0x01 #define CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I 0x02 #define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D 0x03 @@ -158,7 +158,7 @@ #define RESERVED1_ID_MASK 0x0800 #define OBJECT_TYPE_MASK 0x7000 #define RESERVED2_ID_MASK 0x8000 - + #define OBJECT_ID_SHIFT 0x00 #define ENUM_ID_SHIFT 0x08 #define OBJECT_TYPE_SHIFT 0x0C @@ -179,14 +179,14 @@ /* Encoder Object ID definition - Shared with BIOS */ /****************************************************/ /* -#define ENCODER_INTERNAL_LVDS_ENUM_ID1 0x2101 +#define ENCODER_INTERNAL_LVDS_ENUM_ID1 0x2101 #define ENCODER_INTERNAL_TMDS1_ENUM_ID1 0x2102 #define ENCODER_INTERNAL_TMDS2_ENUM_ID1 0x2103 #define ENCODER_INTERNAL_DAC1_ENUM_ID1 0x2104 #define ENCODER_INTERNAL_DAC2_ENUM_ID1 0x2105 #define ENCODER_INTERNAL_SDVOA_ENUM_ID1 0x2106 #define ENCODER_INTERNAL_SDVOB_ENUM_ID1 0x2107 -#define ENCODER_SIL170B_ENUM_ID1 0x2108 +#define ENCODER_SIL170B_ENUM_ID1 0x2108 #define ENCODER_CH7303_ENUM_ID1 0x2109 #define ENCODER_CH7301_ENUM_ID1 0x210A #define ENCODER_INTERNAL_DVO1_ENUM_ID1 0x210B @@ -200,8 +200,8 @@ #define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1 0x2113 #define ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1 0x2114 #define ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1 0x2115 -#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 0x2116 -#define ENCODER_SI178_ENUM_ID1 0x2117 +#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 0x2116 +#define ENCODER_SI178_ENUM_ID1 0x2117 #define ENCODER_MVPU_FPGA_ENUM_ID1 0x2118 #define ENCODER_INTERNAL_DDI_ENUM_ID1 0x2119 #define ENCODER_VT1625_ENUM_ID1 0x211A @@ -316,7 +316,7 @@ #define ENCODER_SI178_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - ENCODER_OBJECT_ID_SI178 << OBJECT_ID_SHIFT) + ENCODER_OBJECT_ID_SI178 << OBJECT_ID_SHIFT) #define ENCODER_MVPU_FPGA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ @@ -324,7 +324,7 @@ #define ENCODER_INTERNAL_DDI_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - ENCODER_OBJECT_ID_INTERNAL_DDI << OBJECT_ID_SHIFT) + ENCODER_OBJECT_ID_INTERNAL_DDI << OBJECT_ID_SHIFT) #define ENCODER_VT1625_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ @@ -352,7 +352,7 @@ #define ENCODER_INTERNAL_KLDSCP_LVTMA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA << OBJECT_ID_SHIFT) + ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA << OBJECT_ID_SHIFT) #define ENCODER_INTERNAL_UNIPHY1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ diff --git a/sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c b/sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c index 113ce8245..5552fa3c7 100644 --- a/sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c +++ b/sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c @@ -6137,7 +6137,7 @@ int amdgpu_in_reset(struct amdgpu_device *adev) { return atomic_read(&adev->reset_domain->in_gpu_reset); } - + /** * amdgpu_device_halt() - bring hardware to some kind of halt state * diff --git a/sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c b/sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c index d54444f92..ef9debc9c 100644 --- a/sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c +++ b/sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c @@ -3418,7 +3418,7 @@ amdgpu_init_backlight(struct amdgpu_device *adev) if (bd == NULL) return; - + drm_connector_list_iter_begin(dev, &conn_iter); drm_for_each_connector_iter(connector, &conn_iter) { if (connector->connector_type != DRM_MODE_CONNECTOR_LVDS && diff --git a/sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c b/sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c index 2c1285b26..118580123 100644 --- a/sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c +++ b/sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c @@ -1100,7 +1100,7 @@ void amdgpu_bo_fini(struct amdgpu_device *adev) arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size); #else drm_mtrr_del(0, adev->gmc.aper_base, adev->gmc.aper_size, DRM_MTRR_WC); - + #endif } drm_dev_exit(idx); diff --git a/sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c b/sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c index a1c8f2dc2..00bb631d5 100644 --- a/sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c +++ b/sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c @@ -101,7 +101,7 @@ amdgpu_vm_it_iter_next(struct amdgpu_bo_va_mapping *node, uint64_t start, static void amdgpu_vm_it_remove(struct amdgpu_bo_va_mapping *node, - struct rb_root_cached *root) + struct rb_root_cached *root) { rb_erase_cached(&node->rb, root); } diff --git a/sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c b/sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c index 5c2050dac..68e31cd1a 100644 --- a/sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c +++ b/sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c @@ -1906,7 +1906,7 @@ static int gfx_v11_0_rlc_load_microcode(struct amdgpu_device *adev) if (version_minor == 3) gfx_v11_0_load_rlcp_rlcv_microcode(adev); } - + return 0; } @@ -3348,7 +3348,7 @@ static int gfx_v11_0_cp_compute_load_microcode(struct amdgpu_device *adev) } memcpy(fw, fw_data, fw_size); - + amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); diff --git a/sys/dev/pci/drm/amd/amdgpu/imu_v11_0.c b/sys/dev/pci/drm/amd/amdgpu/imu_v11_0.c index 8ec1b9699..d588a4939 100644 --- a/sys/dev/pci/drm/amd/amdgpu/imu_v11_0.c +++ b/sys/dev/pci/drm/amd/amdgpu/imu_v11_0.c @@ -58,7 +58,7 @@ static int imu_v11_0_init_microcode(struct amdgpu_device *adev) imu_hdr = (const struct imu_firmware_header_v1_0 *)adev->gfx.imu_fw->data; adev->gfx.imu_fw_version = le32_to_cpu(imu_hdr->header.ucode_version); //adev->gfx.imu_feature_version = le32_to_cpu(imu_hdr->ucode_feature_version); - + if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { info = &adev->firmware.ucode[AMDGPU_UCODE_ID_IMU_I]; info->ucode_id = AMDGPU_UCODE_ID_IMU_I; @@ -240,9 +240,9 @@ static const struct imu_rlc_ram_golden imu_rlc_ram_golden_11[] = IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_AGP_BOT, 0x00000002, 0xe0000000), IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_AGP_TOP, 0x00000000, 0xe0000000), IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL2, 0x00020000, 0xe0000000), - IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regSDMA0_UCODE_SELFLOAD_CONTROL, 0x00000210, 0), - IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regSDMA1_UCODE_SELFLOAD_CONTROL, 0x00000210, 0), - IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCPC_PSP_DEBUG, CPC_PSP_DEBUG__GPA_OVERRIDE_MASK, 0), + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regSDMA0_UCODE_SELFLOAD_CONTROL, 0x00000210, 0), + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regSDMA1_UCODE_SELFLOAD_CONTROL, 0x00000210, 0), + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCPC_PSP_DEBUG, CPC_PSP_DEBUG__GPA_OVERRIDE_MASK, 0), IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCPG_PSP_DEBUG, CPG_PSP_DEBUG__GPA_OVERRIDE_MASK, 0) }; diff --git a/sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c b/sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c index 0c16f2977..f2b487573 100644 --- a/sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c +++ b/sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c @@ -186,7 +186,7 @@ static int xgpu_ai_send_access_requests(struct amdgpu_device *adev, /* Dummy REQ_GPU_INIT_DATA handling */ r = xgpu_ai_poll_msg(adev, IDH_REQ_GPU_INIT_DATA_READY); /* version set to 0 since dummy */ - adev->virt.req_init_data_ver = 0; + adev->virt.req_init_data_ver = 0; } return 0; diff --git a/sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c b/sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c index 4c9e51093..8a9b9786a 100644 --- a/sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c +++ b/sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c @@ -273,7 +273,7 @@ static int sdma_v5_0_init_microcode(struct amdgpu_device *adev) if (ret) return ret; } - + return ret; } diff --git a/sys/dev/pci/drm/amd/include/amd_shared.h b/sys/dev/pci/drm/amd/include/amd_shared.h index f175e65b8..46ed216f0 100644 --- a/sys/dev/pci/drm/amd/include/amd_shared.h +++ b/sys/dev/pci/drm/amd/include/amd_shared.h @@ -60,7 +60,7 @@ enum amd_apu_flags { * acquires the list of IP blocks for the GPU in use on initialization. * It can then operate on this list to perform standard driver operations * such as: init, fini, suspend, resume, etc. -* +* * * IP block implementations are named using the following convention: * _v (E.g.: gfx_v6_0). diff --git a/sys/dev/pci/drm/amd/include/atomfirmware.h b/sys/dev/pci/drm/amd/include/atomfirmware.h index ff855cb21..4eb42d4df 100644 --- a/sys/dev/pci/drm/amd/include/atomfirmware.h +++ b/sys/dev/pci/drm/amd/include/atomfirmware.h @@ -1,5 +1,5 @@ /****************************************************************************\ -* +* * File Name atomfirmware.h * Project This is an interface header file between atombios and OS GPU drivers for SoC15 products * @@ -7,7 +7,7 @@ * * Copyright 2014 Advanced Micro Devices, Inc. * -* Permission is hereby granted, free of charge, to any person obtaining a copy of this software +* Permission is hereby granted, free of charge, to any person obtaining a copy of this software * and associated documentation files (the "Software"), to deal in the Software without restriction, * including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, @@ -49,7 +49,7 @@ enum atom_bios_header_version_def{ typedef unsigned short uint16_t; #endif - #ifndef uint8_t + #ifndef uint8_t typedef unsigned char uint8_t; #endif #endif @@ -203,7 +203,7 @@ enum atom_dp_vs_preemph_def{ /* enum atom_string_def{ -asic_bus_type_pcie_string = "PCI_EXPRESS", +asic_bus_type_pcie_string = "PCI_EXPRESS", atom_fire_gl_string = "FGL", atom_bios_string = "ATOM" }; @@ -222,26 +222,26 @@ enum atombios_image_offset{ OFFSET_TO_VBIOS_DATE = 0x50, }; -/**************************************************************************** +/**************************************************************************** * Common header for all tables (Data table, Command function). -* Every table pointed in _ATOM_MASTER_DATA_TABLE has this common header. +* Every table pointed in _ATOM_MASTER_DATA_TABLE has this common header. * And the pointer actually points to this header. -****************************************************************************/ +****************************************************************************/ struct atom_common_table_header { uint16_t structuresize; - uint8_t format_revision; //mainly used for a hw function, when the parser is not backward compatible - uint8_t content_revision; //change it when a data table has a structure change, or a hw function has a input/output parameter change + uint8_t format_revision; //mainly used for a hw function, when the parser is not backward compatible + uint8_t content_revision; //change it when a data table has a structure change, or a hw function has a input/output parameter change }; -/**************************************************************************** +/**************************************************************************** * Structure stores the ROM header. -****************************************************************************/ +****************************************************************************/ struct atom_rom_header_v2_2 { struct atom_common_table_header table_header; - uint8_t atom_bios_string[4]; //enum atom_string_def atom_bios_string; //Signature to distinguish between Atombios and non-atombios, + uint8_t atom_bios_string[4]; //enum atom_string_def atom_bios_string; //Signature to distinguish between Atombios and non-atombios, uint16_t bios_segment_address; uint16_t protectedmodeoffset; uint16_t configfilenameoffset; @@ -262,33 +262,33 @@ struct atom_rom_header_v2_2 /*==============================hw function portion======================================================================*/ -/**************************************************************************** +/**************************************************************************** * Structures used in Command.mtb, each function name is not given here since those function could change from time to time * The real functionality of each function is associated with the parameter structure version when defined * For all internal cmd function definitions, please reference to atomstruct.h -****************************************************************************/ +****************************************************************************/ struct atom_master_list_of_command_functions_v2_1{ uint16_t asic_init; //Function uint16_t cmd_function1; //used as an internal one uint16_t cmd_function2; //used as an internal one uint16_t cmd_function3; //used as an internal one - uint16_t digxencodercontrol; //Function + uint16_t digxencodercontrol; //Function uint16_t cmd_function5; //used as an internal one - uint16_t cmd_function6; //used as an internal one + uint16_t cmd_function6; //used as an internal one uint16_t cmd_function7; //used as an internal one uint16_t cmd_function8; //used as an internal one uint16_t cmd_function9; //used as an internal one uint16_t setengineclock; //Function uint16_t setmemoryclock; //Function uint16_t setpixelclock; //Function - uint16_t enabledisppowergating; //Function - uint16_t cmd_function14; //used as an internal one + uint16_t enabledisppowergating; //Function + uint16_t cmd_function14; //used as an internal one uint16_t cmd_function15; //used as an internal one uint16_t cmd_function16; //used as an internal one uint16_t cmd_function17; //used as an internal one uint16_t cmd_function18; //used as an internal one - uint16_t cmd_function19; //used as an internal one - uint16_t cmd_function20; //used as an internal one + uint16_t cmd_function19; //used as an internal one + uint16_t cmd_function20; //used as an internal one uint16_t cmd_function21; //used as an internal one uint16_t cmd_function22; //used as an internal one uint16_t cmd_function23; //used as an internal one @@ -315,20 +315,20 @@ struct atom_master_list_of_command_functions_v2_1{ uint16_t cmd_function44; //used as an internal one uint16_t cmd_function45; //used as an internal one uint16_t setdceclock; //Function - uint16_t getmemoryclock; //Function - uint16_t getengineclock; //Function + uint16_t getmemoryclock; //Function + uint16_t getengineclock; //Function uint16_t setcrtc_usingdtdtiming; //Function - uint16_t externalencodercontrol; //Function + uint16_t externalencodercontrol; //Function uint16_t cmd_function51; //used as an internal one uint16_t cmd_function52; //used as an internal one uint16_t cmd_function53; //used as an internal one - uint16_t processi2cchanneltransaction;//Function + uint16_t processi2cchanneltransaction;//Function uint16_t cmd_function55; //used as an internal one uint16_t cmd_function56; //used as an internal one uint16_t cmd_function57; //used as an internal one uint16_t cmd_function58; //used as an internal one uint16_t cmd_function59; //used as an internal one - uint16_t computegpuclockparam; //Function + uint16_t computegpuclockparam; //Function uint16_t cmd_function61; //used as an internal one uint16_t cmd_function62; //used as an internal one uint16_t dynamicmemorysettings; //Function function @@ -338,7 +338,7 @@ struct atom_master_list_of_command_functions_v2_1{ uint16_t setvoltage; //Function uint16_t cmd_function68; //used as an internal one uint16_t readefusevalue; //Function - uint16_t cmd_function70; //used as an internal one + uint16_t cmd_function70; //used as an internal one uint16_t cmd_function71; //used as an internal one uint16_t cmd_function72; //used as an internal one uint16_t cmd_function73; //used as an internal one @@ -357,26 +357,26 @@ struct atom_master_command_function_v2_1 struct atom_master_list_of_command_functions_v2_1 listofcmdfunctions; }; -/**************************************************************************** +/**************************************************************************** * Structures used in every command function -****************************************************************************/ +****************************************************************************/ struct atom_function_attribute { - uint16_t ws_in_bytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), - uint16_t ps_in_bytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), + uint16_t ws_in_bytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), + uint16_t ps_in_bytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), uint16_t updated_by_util:1; //[15]=flag to indicate the function is updated by util }; -/**************************************************************************** +/**************************************************************************** * Common header for all hw functions. -* Every function pointed by _master_list_of_hw_function has this common header. +* Every function pointed by _master_list_of_hw_function has this common header. * And the pointer actually points to this header. -****************************************************************************/ +****************************************************************************/ struct atom_rom_hw_function_header { struct atom_common_table_header func_header; - struct atom_function_attribute func_attrib; + struct atom_function_attribute func_attrib; }; @@ -387,25 +387,25 @@ struct atom_rom_hw_function_header ****************************************************************************/ struct atom_master_list_of_data_tables_v2_1{ uint16_t utilitypipeline; /* Offest for the utility to get parser info,Don't change this position!*/ - uint16_t multimedia_info; + uint16_t multimedia_info; uint16_t smc_dpm_info; - uint16_t sw_datatable3; + uint16_t sw_datatable3; uint16_t firmwareinfo; /* Shared by various SW components */ uint16_t sw_datatable5; uint16_t lcd_info; /* Shared by various SW components */ uint16_t sw_datatable7; - uint16_t smu_info; + uint16_t smu_info; uint16_t sw_datatable9; - uint16_t sw_datatable10; + uint16_t sw_datatable10; uint16_t vram_usagebyfirmware; /* Shared by various SW components */ uint16_t gpio_pin_lut; /* Shared by various SW components */ - uint16_t sw_datatable13; + uint16_t sw_datatable13; uint16_t gfx_info; uint16_t powerplayinfo; /* Shared by various SW components */ - uint16_t sw_datatable16; + uint16_t sw_datatable16; uint16_t sw_datatable17; uint16_t sw_datatable18; - uint16_t sw_datatable19; + uint16_t sw_datatable19; uint16_t sw_datatable20; uint16_t sw_datatable21; uint16_t displayobjectinfo; /* Shared by various SW components */ @@ -425,7 +425,7 @@ struct atom_master_list_of_data_tables_v2_1{ struct atom_master_data_table_v2_1 -{ +{ struct atom_common_table_header table_header; struct atom_master_list_of_data_tables_v2_1 listOfdatatables; }; @@ -468,7 +468,7 @@ enum atom_dtd_format_modemiscinfo{ */ -/* +/* *************************************************************************** Data Table firmwareinfo structure *************************************************************************** @@ -482,12 +482,12 @@ struct atom_firmware_info_v3_1 uint32_t bootup_mclk_in10khz; uint32_t firmware_capability; // enum atombios_firmware_capability uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */ - uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address + uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address uint16_t bootup_vddc_mv; - uint16_t bootup_vddci_mv; + uint16_t bootup_vddci_mv; uint16_t bootup_mvddc_mv; uint16_t bootup_vddgfx_mv; - uint8_t mem_module_id; + uint8_t mem_module_id; uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ uint8_t reserved1[2]; uint32_t mc_baseaddr_high; @@ -609,7 +609,7 @@ struct atom_firmware_info_v3_4 { uint32_t reserved[2]; }; -/* +/* *************************************************************************** Data Table lcd_info structure *************************************************************************** @@ -652,13 +652,13 @@ enum atom_lcd_info_panel_misc{ //uceDPToLVDSRxId enum atom_lcd_info_dptolvds_rx_id { - eDP_TO_LVDS_RX_DISABLE = 0x00, // no eDP->LVDS translator chip + eDP_TO_LVDS_RX_DISABLE = 0x00, // no eDP->LVDS translator chip eDP_TO_LVDS_COMMON_ID = 0x01, // common eDP->LVDS translator chip without AMD SW init eDP_TO_LVDS_REALTEK_ID = 0x02, // Realtek tansaltor which require AMD SW init }; - -/* + +/* *************************************************************************** Data Table gpio_pin_lut structure *************************************************************************** @@ -676,7 +676,7 @@ struct atom_gpio_pin_assignment /* atom_gpio_pin_assignment.gpio_id definition */ enum atom_gpio_pin_assignment_gpio_id { I2C_HW_LANE_MUX =0x0f, /* only valid when bit7=1 */ - I2C_HW_ENGINE_ID_MASK =0x70, /* only valid when bit7=1 */ + I2C_HW_ENGINE_ID_MASK =0x70, /* only valid when bit7=1 */ I2C_HW_CAP =0x80, /*only when the I2C_HW_CAP is set, the pin ID is assigned to an I2C pin pair, otherwise, it's an generic GPIO pin */ /* gpio_id pre-define id for multiple usage */ @@ -705,7 +705,7 @@ struct atom_gpio_pin_lut_v2_1 }; -/* +/* *************************************************************************** Data Table vram_usagebyfirmware structure *************************************************************************** @@ -716,11 +716,11 @@ struct vram_usagebyfirmware_v2_1 struct atom_common_table_header table_header; uint32_t start_address_in_kb; uint16_t used_by_firmware_in_kb; - uint16_t used_by_driver_in_kb; + uint16_t used_by_driver_in_kb; }; -/* +/* *************************************************************************** Data Table displayobjectinfo structure *************************************************************************** @@ -751,14 +751,14 @@ struct atom_common_record_header struct atom_i2c_record { struct atom_common_record_header record_header; //record_type = ATOM_I2C_RECORD_TYPE - uint8_t i2c_id; + uint8_t i2c_id; uint8_t i2c_slave_addr; //The slave address, it's 0 when the record is attached to connector for DDC }; struct atom_hpd_int_record { struct atom_common_record_header record_header; //record_type = ATOM_HPD_INT_RECORD_TYPE - uint8_t pin_id; //Corresponding block in GPIO_PIN_INFO table gives the pin info + uint8_t pin_id; //Corresponding block in GPIO_PIN_INFO table gives the pin info uint8_t plugin_pin_state; }; @@ -779,10 +779,10 @@ struct atom_connector_speed_record { enum atom_encoder_caps_def { ATOM_ENCODER_CAP_RECORD_HBR2 =0x01, // DP1.2 HBR2 is supported by HW encoder, it is retired in NI. the real meaning from SI is MST_EN - ATOM_ENCODER_CAP_RECORD_MST_EN =0x01, // from SI, this bit means DP MST is enable or not. - ATOM_ENCODER_CAP_RECORD_HBR2_EN =0x02, // DP1.2 HBR2 setting is qualified and HBR2 can be enabled - ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN =0x04, // HDMI2.0 6Gbps enable or not. - ATOM_ENCODER_CAP_RECORD_HBR3_EN =0x08, // DP1.3 HBR3 is supported by board. + ATOM_ENCODER_CAP_RECORD_MST_EN =0x01, // from SI, this bit means DP MST is enable or not. + ATOM_ENCODER_CAP_RECORD_HBR2_EN =0x02, // DP1.2 HBR2 setting is qualified and HBR2 can be enabled + ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN =0x04, // HDMI2.0 6Gbps enable or not. + ATOM_ENCODER_CAP_RECORD_HBR3_EN =0x08, // DP1.3 HBR3 is supported by board. ATOM_ENCODER_CAP_RECORD_DP2 =0x10, // DP2 is supported by ASIC/board. ATOM_ENCODER_CAP_RECORD_UHBR10_EN =0x20, // DP2.0 UHBR10 settings is supported by board ATOM_ENCODER_CAP_RECORD_UHBR13_5_EN =0x40, // DP2.0 UHBR13.5 settings is supported by board @@ -799,13 +799,13 @@ struct atom_encoder_caps_record enum atom_connector_caps_def { ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY = 0x01, //a cap bit to indicate that this non-embedded display connector is an internal display - ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL = 0x02, //a cap bit to indicate that this internal display requires BL control from GPU, refers to lcd_info for BL PWM freq + ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL = 0x02, //a cap bit to indicate that this internal display requires BL control from GPU, refers to lcd_info for BL PWM freq }; struct atom_disp_connector_caps_record { struct atom_common_record_header record_header; - uint32_t connectcaps; + uint32_t connectcaps; }; //The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually @@ -823,21 +823,21 @@ struct atom_object_gpio_cntl_record struct atom_gpio_pin_control_pair gpio[1]; // the real gpio pin pair determined by number of pins ucNumberOfPins }; -//Definitions for GPIO pin state +//Definitions for GPIO pin state enum atom_gpio_pin_control_pinstate_def { GPIO_PIN_TYPE_INPUT = 0x00, GPIO_PIN_TYPE_OUTPUT = 0x10, GPIO_PIN_TYPE_HW_CONTROL = 0x20, -//For GPIO_PIN_TYPE_OUTPUT the following is defined +//For GPIO_PIN_TYPE_OUTPUT the following is defined GPIO_PIN_OUTPUT_STATE_MASK = 0x01, GPIO_PIN_OUTPUT_STATE_SHIFT = 0, GPIO_PIN_STATE_ACTIVE_LOW = 0x0, GPIO_PIN_STATE_ACTIVE_HIGH = 0x1, }; -// Indexes to GPIO array in GLSync record +// Indexes to GPIO array in GLSync record // GLSync record is for Frame Lock/Gen Lock feature. enum atom_glsync_record_gpio_index_def { @@ -857,7 +857,7 @@ enum atom_glsync_record_gpio_index_def struct atom_connector_hpdpin_lut_record //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE { struct atom_common_record_header record_header; - uint8_t hpd_pin_map[8]; + uint8_t hpd_pin_map[8]; }; struct atom_connector_auxddc_lut_record //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE @@ -872,7 +872,7 @@ struct atom_connector_forced_tmds_cap_record // override TMDS capability on this connector when it operate in TMDS mode. usMaxTmdsClkRate = max TMDS Clock in Mhz/2.5 uint8_t maxtmdsclkrate_in2_5mhz; uint8_t reserved; -}; +}; struct atom_connector_layout_info { @@ -885,7 +885,7 @@ struct atom_connector_layout_info enum atom_connector_layout_info_connector_type_def { CONNECTOR_TYPE_DVI_D = 1, - + CONNECTOR_TYPE_HDMI = 4, CONNECTOR_TYPE_DISPLAY_PORT = 5, CONNECTOR_TYPE_MINI_DISPLAY_PORT = 6, @@ -936,7 +936,7 @@ struct atom_display_object_path_v2 uint16_t extencoderobjid; //2nd encoder after the first encoder, from the connector point of view; uint16_t encoder_recordoffset; uint16_t extencoder_recordoffset; - uint16_t device_tag; //a supported device vector, each display path starts with this.the paths are enumerated in the way of priority, a path appears first + uint16_t device_tag; //a supported device vector, each display path starts with this.the paths are enumerated in the way of priority, a path appears first uint8_t priority_id; uint8_t reserved; }; @@ -973,7 +973,7 @@ struct display_object_info_table_v1_5 { struct atom_display_object_path_v3 display_path[8]; }; -/* +/* *************************************************************************** Data Table dce_info structure *************************************************************************** @@ -986,18 +986,18 @@ struct atom_display_controller_info_v4_1 uint16_t dce_refclk_10khz; uint16_t i2c_engine_refclk_10khz; uint16_t dvi_ss_percentage; // in unit of 0.001% - uint16_t dvi_ss_rate_10hz; + uint16_t dvi_ss_rate_10hz; uint16_t hdmi_ss_percentage; // in unit of 0.001% uint16_t hdmi_ss_rate_10hz; uint16_t dp_ss_percentage; // in unit of 0.001% uint16_t dp_ss_rate_10hz; uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode - uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode + uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode uint8_t ss_reserved; uint8_t hardcode_mode_num; // a hardcode mode number defined in StandardVESA_TimingTable when a CRT or DFP EDID is not available uint8_t reserved1[3]; - uint16_t dpphy_refclk_10khz; + uint16_t dpphy_refclk_10khz; uint16_t reserved2; uint8_t dceip_min_ver; uint8_t dceip_max_ver; @@ -1013,11 +1013,11 @@ struct atom_display_controller_info_v4_1 struct atom_display_controller_info_v4_2 { struct atom_common_table_header table_header; - uint32_t display_caps; + uint32_t display_caps; uint32_t bootup_dispclk_10khz; uint16_t dce_refclk_10khz; uint16_t i2c_engine_refclk_10khz; - uint16_t dvi_ss_percentage; // in unit of 0.001% + uint16_t dvi_ss_percentage; // in unit of 0.001% uint16_t dvi_ss_rate_10hz; uint16_t hdmi_ss_percentage; // in unit of 0.001% uint16_t hdmi_ss_rate_10hz; @@ -1025,13 +1025,13 @@ struct atom_display_controller_info_v4_2 uint16_t dp_ss_rate_10hz; uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode - uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode + uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode uint8_t ss_reserved; uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable - uint16_t dpphy_refclk_10khz; + uint16_t dpphy_refclk_10khz; uint16_t reserved2; uint8_t dcnip_min_ver; uint8_t dcnip_max_ver; @@ -1201,15 +1201,15 @@ struct atom_display_controller_info_v4_5 uint32_t reserved[26]; }; -/* +/* *************************************************************************** Data Table ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO structure *************************************************************************** */ struct atom_ext_display_path { - uint16_t device_tag; //A bit vector to show what devices are supported - uint16_t device_acpi_enum; //16bit device ACPI id. + uint16_t device_tag; //A bit vector to show what devices are supported + uint16_t device_acpi_enum; //16bit device ACPI id. uint16_t connectorobjid; //A physical connector for displays to plug in, using object connector definitions uint8_t auxddclut_index; //An index into external AUX/DDC channel LUT uint8_t hpdlut_index; //An index into external HPD pin LUT @@ -1217,7 +1217,7 @@ struct atom_ext_display_path uint8_t channelmapping; // if ucChannelMapping=0, using default one to one mapping uint8_t chpninvert; // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted uint16_t caps; - uint16_t reserved; + uint16_t reserved; }; //usCaps @@ -1235,7 +1235,7 @@ struct atom_external_display_connection_info struct atom_common_table_header table_header; uint8_t guid[16]; // a GUID is a 16 byte long string struct atom_ext_display_path path[7]; // total of fixed 7 entries. - uint8_t checksum; // a simple Checksum of the sum of whole structure equal to 0x0. + uint8_t checksum; // a simple Checksum of the sum of whole structure equal to 0x0. uint8_t stereopinid; // use for eDP panel uint8_t remotedisplayconfig; uint8_t edptolvdsrxid; @@ -1243,7 +1243,7 @@ struct atom_external_display_connection_info uint8_t reserved[3]; // for potential expansion }; -/* +/* *************************************************************************** Data Table integratedsysteminfo structure *************************************************************************** @@ -1287,7 +1287,7 @@ struct atom_14nm_dpphy_dvihdmi_tuningset { uint32_t max_symclk_in10khz; uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode - uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf + uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf uint16_t margindeemph; //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4 uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_en [23:22]tx_binary_ron_code_offset @@ -1303,16 +1303,16 @@ struct atom_14nm_dpphy_dp_setting{ }; struct atom_14nm_dpphy_dp_tuningset{ - uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf + uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf uint8_t version; uint16_t table_size; // size of atom_14nm_dpphy_dp_tuningset uint16_t reserved; struct atom_14nm_dpphy_dp_setting dptuning[10]; }; -struct atom_14nm_dig_transmitter_info_header_v4_0{ - struct atom_common_table_header table_header; - uint16_t pcie_phy_tmds_hdmi_macro_settings_offset; // offset of PCIEPhyTMDSHDMIMacroSettingsTbl +struct atom_14nm_dig_transmitter_info_header_v4_0{ + struct atom_common_table_header table_header; + uint16_t pcie_phy_tmds_hdmi_macro_settings_offset; // offset of PCIEPhyTMDSHDMIMacroSettingsTbl uint16_t uniphy_vs_emph_lookup_table_offset; // offset of UniphyVSEmphLookUpTbl uint16_t uniphy_xbar_settings_table_offset; // offset of UniphyXbarSettingsTbl }; @@ -1326,14 +1326,14 @@ struct atom_14nm_combphy_tmds_vs_set uint8_t common_seldeemph60__deemph_6db_4_val; uint8_t cmd_bus_global_for_tx_lane0__boostadj_val ; uint8_t common_zcalcode_ctrl__tx_driver_fifty_ohms_val; - uint8_t margin_deemph_lane0__deemph_sel_val; + uint8_t margin_deemph_lane0__deemph_sel_val; }; struct atom_DCN_dpphy_dvihdmi_tuningset { uint32_t max_symclk_in10khz; uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode - uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf + uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf uint8_t tx_eq_main; // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN) uint8_t tx_eq_pre; // map to RDPCSTX_PHY_FUSE0/1/2/3[11:6](EQ_PRE) uint8_t tx_eq_post; // map to RDPCSTX_PHY_FUSE0/1/2/3[17:12](EQ_POST) @@ -1351,7 +1351,7 @@ struct atom_DCN_dpphy_dp_setting{ }; struct atom_DCN_dpphy_dp_tuningset{ - uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf + uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf uint8_t version; uint16_t table_size; // size of atom_14nm_dpphy_dp_setting uint16_t reserved; @@ -1375,10 +1375,10 @@ struct atom_integrated_system_info_v1_11 { struct atom_common_table_header table_header; uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def - uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def - uint32_t system_config; + uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def + uint32_t system_config; uint32_t cpucapinfo; - uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1% + uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1% uint16_t gpuclk_ss_type; uint16_t lvds_ss_percentage; //unit of 0.001%, 1000 mean 1% uint16_t lvds_ss_rate_10hz; @@ -1424,10 +1424,10 @@ struct atom_integrated_system_info_v1_12 { struct atom_common_table_header table_header; uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def - uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def - uint32_t system_config; + uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def + uint32_t system_config; uint32_t cpucapinfo; - uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1% + uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1% uint16_t gpuclk_ss_type; uint16_t lvds_ss_percentage; //unit of 0.001%, 1000 mean 1% uint16_t lvds_ss_rate_10hz; @@ -1457,7 +1457,7 @@ struct atom_integrated_system_info_v1_12 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK5_tuningset; struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK8_tuningset; struct atom_DCN_dpphy_dp_tuningset rbr_tuningset; // rbr 1.62G dp tuning set - struct atom_DCN_dpphy_dp_tuningset hbr3_tuningset; // HBR3 dp tuning set + struct atom_DCN_dpphy_dp_tuningset hbr3_tuningset; // HBR3 dp tuning set struct atom_camera_data camera_info; struct atom_hdmi_retimer_redriver_set dp0_retimer_set; //for DP0 struct atom_hdmi_retimer_redriver_set dp1_retimer_set; //for DP1 @@ -1596,7 +1596,7 @@ enum atom_sysinfo_dpphy_override_def{ ATOM_ENABLE_HDMI_TUNINGSET = 0x02, ATOM_ENABLE_HDMI6G_TUNINGSET = 0x04, ATOM_ENABLE_DP_TUNINGSET = 0x08, - ATOM_ENABLE_DP_HBR3_TUNINGSET = 0x10, + ATOM_ENABLE_DP_HBR3_TUNINGSET = 0x10, }; //lvds_misc @@ -1645,15 +1645,15 @@ enum atom_dmi_t17_mem_type_def{ }; -// this Table is used starting from NL/AM, used by SBIOS and pass the IntegratedSystemInfoTable/PowerPlayInfoTable/SystemCameraInfoTable +// this Table is used starting from NL/AM, used by SBIOS and pass the IntegratedSystemInfoTable/PowerPlayInfoTable/SystemCameraInfoTable struct atom_fusion_system_info_v4 { struct atom_integrated_system_info_v1_11 sysinfo; // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition uint32_t powerplayinfo[256]; // Reserve 1024 bytes space for PowerPlayInfoTable -}; +}; -/* +/* *************************************************************************** Data Table gfx_info structure *************************************************************************** @@ -1674,10 +1674,10 @@ struct atom_gfx_info_v2_2 uint32_t regaddr_cp_dma_src_addr_hi; uint32_t regaddr_cp_dma_dst_addr; uint32_t regaddr_cp_dma_dst_addr_hi; - uint32_t regaddr_cp_dma_command; + uint32_t regaddr_cp_dma_command; uint32_t regaddr_cp_status; uint32_t regaddr_rlc_gpu_clock_32; - uint32_t rlc_gpu_timer_refclk; + uint32_t rlc_gpu_timer_refclk; }; struct atom_gfx_info_v2_3 { @@ -1814,7 +1814,7 @@ struct atom_gfx_info_v3_0 { uint32_t reserved[8]; }; -/* +/* *************************************************************************** Data Table smu_info structure *************************************************************************** @@ -1836,7 +1836,7 @@ struct atom_smu_info_v3_1 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid - uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event + uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid uint8_t fw_ctf_polarity; // GPIO polarity for CTF }; @@ -2446,8 +2446,8 @@ struct atom_smc_dpm_info_v4_5 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event - uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event - uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event + uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event + uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event uint8_t GthrGpio; // GPIO pin configured for GTHR Event uint8_t GthrPolarity; // replace GPIO polarity for GTHR @@ -2479,11 +2479,11 @@ struct atom_smc_dpm_info_v4_5 // Total board power uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power - uint16_t BoardPadding; + uint16_t BoardPadding; // Mvdd Svi2 Div Ratio Setting uint32_t MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16) - + uint32_t BoardReserved[9]; }; @@ -2696,7 +2696,7 @@ struct atom_smc_dpm_info_v4_9 //uint32_t GamingClk[6]; // SECTION: I2C Control - struct smudpm_i2c_controller_config_v3 I2cControllers[16]; + struct smudpm_i2c_controller_config_v3 I2cControllers[16]; uint8_t GpioScl; // GPIO Number for SCL Line, used only for CKSVII2C1 uint8_t GpioSda; // GPIO Number for SDA Line, used only for CKSVII2C1 @@ -2726,21 +2726,21 @@ struct atom_smc_dpm_info_v4_9 uint16_t Mem0MaxCurrent; // in Amps uint8_t Mem0Offset; // in Amps uint8_t Padding_TelemetryMem0; - + uint16_t Mem1MaxCurrent; // in Amps uint8_t Mem1Offset; // in Amps uint8_t Padding_TelemetryMem1; uint32_t MvddRatio; // This is used for MVDD Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16) - + // SECTION: GPIO Settings uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event - uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event - uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event + uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event + uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event uint8_t GthrGpio; // GPIO pin configured for GTHR Event uint8_t GthrPolarity; // replace GPIO polarity for GTHR @@ -2755,7 +2755,7 @@ struct atom_smc_dpm_info_v4_9 uint8_t LedSpare1[2]; // SECTION: Clock Spread Spectrum - + // GFXCLK PLL Spread Spectrum uint8_t PllGfxclkSpreadEnabled; // on or off uint8_t PllGfxclkSpreadPercent; // Q4.4 @@ -2765,7 +2765,7 @@ struct atom_smc_dpm_info_v4_9 uint8_t DfllGfxclkSpreadEnabled; // on or off uint8_t DfllGfxclkSpreadPercent; // Q4.4 uint16_t DfllGfxclkSpreadFreq; // kHz - + // UCLK Spread Spectrum uint8_t UclkSpreadEnabled; // on or off uint8_t UclkSpreadPercent; // Q4.4 @@ -2775,17 +2775,17 @@ struct atom_smc_dpm_info_v4_9 uint8_t FclkSpreadEnabled; // on or off uint8_t FclkSpreadPercent; // Q4.4 uint16_t FclkSpreadFreq; // kHz - + // Section: Memory Config - uint32_t MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask. - + uint32_t MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask. + uint8_t DramBitWidth; // For DRAM use only. See Dram Bit width type defines uint8_t PaddingMem1[3]; // Section: Total Board Power uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power - uint16_t BoardPowerPadding; - + uint16_t BoardPowerPadding; + // SECTION: XGMI Training uint8_t XgmiLinkSpeed [4]; uint8_t XgmiLinkWidth [4]; @@ -2852,7 +2852,7 @@ struct atom_smc_dpm_info_v4_10 uint32_t reserved[16]; }; -/* +/* *************************************************************************** Data Table asic_profiling_info structure *************************************************************************** @@ -2860,8 +2860,8 @@ struct atom_smc_dpm_info_v4_10 struct atom_asic_profiling_info_v4_1 { struct atom_common_table_header table_header; - uint32_t maxvddc; - uint32_t minvddc; + uint32_t maxvddc; + uint32_t minvddc; uint32_t avfs_meannsigma_acontant0; uint32_t avfs_meannsigma_acontant1; uint32_t avfs_meannsigma_acontant2; @@ -2877,7 +2877,7 @@ struct atom_asic_profiling_info_v4_1 uint32_t avfsgb_fuse_table_cksoff_m1; uint32_t avfsgb_fuse_table_cksoff_m2; uint32_t avfsgb_fuse_table_cksoff_b; - uint32_t avfsgb_fuse_table_ckson_m1; + uint32_t avfsgb_fuse_table_ckson_m1; uint32_t avfsgb_fuse_table_ckson_m2; uint32_t avfsgb_fuse_table_ckson_b; uint16_t max_voltage_0_25mv; @@ -2966,7 +2966,7 @@ struct atom_asic_profiling_info_v4_2 { uint32_t acg_phyclk2gfxclk_c; }; -/* +/* *************************************************************************** Data Table multimedia_info structure *************************************************************************** @@ -2981,13 +2981,13 @@ struct atom_multimedia_info_v2_1 uint16_t uvd_enc_max_input_width_pixels; uint16_t uvd_enc_max_input_height_pixels; uint16_t vce_enc_max_input_width_pixels; - uint16_t vce_enc_max_input_height_pixels; + uint16_t vce_enc_max_input_height_pixels; uint32_t uvd_enc_max_bandwidth; // 16x16 pixels/sec, codec independent uint32_t vce_enc_max_bandwidth; // 16x16 pixels/sec, codec independent }; -/* +/* *************************************************************************** Data Table umc_info structure *************************************************************************** @@ -3071,7 +3071,7 @@ enum atom_umc_config1_def { UMC_CONFIG1__ENABLE_ECC_CAPABLE = 0x00010000, }; -/* +/* *************************************************************************** Data Table vram_info structure *************************************************************************** @@ -3089,12 +3089,12 @@ struct atom_vram_module_v9 { uint8_t channel_num; // Number of mem. channels supported in this module uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 - uint8_t tunningset_id; // MC phy registers set per. + uint8_t tunningset_id; // MC phy registers set per. uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) uint8_t hbm_ven_rev_id; // hbm_ven_rev_id uint8_t vram_rsd2; // reserved - char dram_pnstring[20]; // part number end with '0'. + char dram_pnstring[20]; // part number end with '0'. }; struct atom_vram_info_header_v2_3 { @@ -3189,12 +3189,12 @@ union atom_umc_reg_setting_id_config_access struct atom_umc_reg_setting_data_block{ union atom_umc_reg_setting_id_config_access block_id; - uint32_t u32umc_reg_data[1]; + uint32_t u32umc_reg_data[1]; }; struct atom_umc_init_reg_block{ uint16_t umc_reg_num; - uint16_t reserved; + uint16_t reserved; union atom_umc_register_addr_info_access umc_reg_list[1]; //for allocation purpose, the real number come from umc_reg_num; struct atom_umc_reg_setting_data_block umc_reg_setting_list[1]; }; @@ -3381,7 +3381,7 @@ struct atom_vram_info_header_v2_6 { uint8_t mc_phy_tile_num; struct atom_vram_module_v9 vram_module[16]; }; -/* +/* *************************************************************************** Data Table voltageobject_info structure *************************************************************************** @@ -3394,18 +3394,18 @@ struct atom_i2c_data_entry struct atom_voltage_object_header_v4{ uint8_t voltage_type; //enum atom_voltage_type - uint8_t voltage_mode; //enum atom_voltage_object_mode + uint8_t voltage_mode; //enum atom_voltage_object_mode uint16_t object_size; //Size of Object }; // atom_voltage_object_header_v4.voltage_mode -enum atom_voltage_object_mode +enum atom_voltage_object_mode { VOLTAGE_OBJ_GPIO_LUT = 0, //VOLTAGE and GPIO Lookup table ->atom_gpio_voltage_object_v4 VOLTAGE_OBJ_VR_I2C_INIT_SEQ = 3, //VOLTAGE REGULATOR INIT sequece through I2C -> atom_i2c_voltage_object_v4 VOLTAGE_OBJ_PHASE_LUT = 4, //Set Vregulator Phase lookup table ->atom_gpio_voltage_object_v4 VOLTAGE_OBJ_SVID2 = 7, //Indicate voltage control by SVID2 ->atom_svid2_voltage_object_v4 - VOLTAGE_OBJ_EVV = 8, + VOLTAGE_OBJ_EVV = 8, VOLTAGE_OBJ_MERGED_POWER = 9, }; @@ -3415,9 +3415,9 @@ struct atom_i2c_voltage_object_v4 uint8_t regulator_id; //Indicate Voltage Regulator Id uint8_t i2c_id; uint8_t i2c_slave_addr; - uint8_t i2c_control_offset; + uint8_t i2c_control_offset; uint8_t i2c_flag; // Bit0: 0 - One byte data; 1 - Two byte data - uint8_t i2c_speed; // =0, use default i2c speed, otherwise use it in unit of kHz. + uint8_t i2c_speed; // =0, use default i2c speed, otherwise use it in unit of kHz. uint8_t reserved[2]; struct atom_i2c_data_entry i2cdatalut[1]; // end with 0xff }; @@ -3439,10 +3439,10 @@ struct atom_voltage_gpio_map_lut struct atom_gpio_voltage_object_v4 { struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_GPIO_LUT or VOLTAGE_OBJ_PHASE_LUT - uint8_t gpio_control_id; // default is 0 which indicate control through CG VID mode + uint8_t gpio_control_id; // default is 0 which indicate control through CG VID mode uint8_t gpio_entry_num; // indiate the entry numbers of Votlage/Gpio value Look up table uint8_t phase_delay_us; // phase delay in unit of micro second - uint8_t reserved; + uint8_t reserved; uint32_t gpio_mask_val; // GPIO Mask value struct atom_voltage_gpio_map_lut voltage_gpio_lut[1]; }; @@ -3452,10 +3452,10 @@ struct atom_svid2_voltage_object_v4 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_SVID2 uint8_t loadline_psi1; // bit4:0= loadline setting ( Core Loadline trim and offset trim ), bit5=0:PSI1_L disable =1: PSI1_L enable uint8_t psi0_l_vid_thresd; // VR PSI0_L VID threshold - uint8_t psi0_enable; // + uint8_t psi0_enable; uint8_t maxvstep; uint8_t telemetry_offset; - uint8_t telemetry_gain; + uint8_t telemetry_gain; uint16_t reserved1; }; @@ -3475,22 +3475,22 @@ union atom_voltage_object_v4{ struct atom_voltage_objects_info_v4_1 { - struct atom_common_table_header table_header; + struct atom_common_table_header table_header; union atom_voltage_object_v4 voltage_object[1]; //Info for Voltage control }; -/* +/* *************************************************************************** - All Command Function structure definition - *************************************************************************** -*/ + All Command Function structure definition + *************************************************************************** +*/ -/* +/* *************************************************************************** Structures used by asic_init - *************************************************************************** -*/ + *************************************************************************** +*/ struct asic_init_engine_parameters { @@ -3530,11 +3530,11 @@ enum atom_asic_init_mem_flag b3DRAM_SELF_REFRESH_EXIT =0x20, }; -/* +/* *************************************************************************** Structures used by setengineclock - *************************************************************************** -*/ + *************************************************************************** +*/ struct set_engine_clock_parameters_v2_1 { @@ -3557,22 +3557,22 @@ enum atom_set_engine_mem_clock_flag b3STORE_DPM_TRAINGING = 0x40, //Applicable to memory clock change,when set, it store specific DPM mode training result }; -/* +/* *************************************************************************** Structures used by getengineclock - *************************************************************************** -*/ + *************************************************************************** +*/ struct get_engine_clock_parameter { uint32_t sclk_10khz; // current engine speed in 10KHz unit uint32_t reserved; }; -/* +/* *************************************************************************** Structures used by setmemoryclock - *************************************************************************** -*/ + *************************************************************************** +*/ struct set_memory_clock_parameters_v2_1 { uint32_t mclkfreqin10khz:24; @@ -3587,11 +3587,11 @@ struct set_memory_clock_ps_allocation_v2_1 }; -/* +/* *************************************************************************** Structures used by getmemoryclock - *************************************************************************** -*/ + *************************************************************************** +*/ struct get_memory_clock_parameter { uint32_t mclk_10khz; // current engine speed in 10KHz unit @@ -3600,11 +3600,11 @@ struct get_memory_clock_parameter -/* +/* *************************************************************************** Structures used by setvoltage - *************************************************************************** -*/ + *************************************************************************** +*/ struct set_voltage_parameters_v1_4 { @@ -3628,14 +3628,14 @@ struct set_voltage_ps_allocation_v1_4 }; -/* +/* *************************************************************************** Structures used by computegpuclockparam - *************************************************************************** -*/ + *************************************************************************** +*/ //ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag -enum atom_gpu_clock_type +enum atom_gpu_clock_type { COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK =0x00, COMPUTE_GPUCLK_INPUT_FLAG_GFXCLK =0x01, @@ -3644,7 +3644,7 @@ enum atom_gpu_clock_type struct compute_gpu_clock_input_parameter_v1_8 { - uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock + uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock uint32_t gpu_clock_type:8; //Input indicate clock type: enum atom_gpu_clock_type uint32_t reserved[5]; }; @@ -3652,7 +3652,7 @@ struct compute_gpu_clock_input_parameter_v1_8 struct compute_gpu_clock_output_parameter_v1_8 { - uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock + uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock uint32_t dfs_did:8; //return parameter: DFS divider which is used to program to register directly uint32_t pll_fb_mult; //Feedback Multiplier, bit 8:0 int, bit 15:12 post_div, bit 31:16 frac uint32_t pll_ss_fbsmult; // Spread FB Mult: bit 8:0 int, bit 31:16 frac @@ -3664,11 +3664,11 @@ struct compute_gpu_clock_output_parameter_v1_8 -/* +/* *************************************************************************** Structures used by ReadEfuseValue - *************************************************************************** -*/ + *************************************************************************** +*/ struct read_efuse_input_parameters_v3_1 { @@ -3685,20 +3685,20 @@ union read_efuse_value_parameters_v3_1 }; -/* +/* *************************************************************************** Structures used by getsmuclockinfo - *************************************************************************** -*/ + *************************************************************************** +*/ struct atom_get_smu_clock_info_parameters_v3_1 { - uint8_t syspll_id; // 0= syspll0, 1=syspll1, 2=syspll2 + uint8_t syspll_id; // 0= syspll0, 1=syspll1, 2=syspll2 uint8_t clk_id; // atom_smu9_syspll0_clock_id (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ ) uint8_t command; // enum of atom_get_smu_clock_info_command uint8_t dfsdid; // =0: get DFS DID from register, >0, give DFS divider, (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ ) }; -enum atom_get_smu_clock_info_command +enum atom_get_smu_clock_info_command { GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ = 0, GET_SMU_CLOCK_INFO_V3_1_GET_PLLVCO_FREQ = 1, @@ -3819,13 +3819,13 @@ struct atom_get_smu_clock_info_output_parameters_v3_1 -/* +/* *************************************************************************** Structures used by dynamicmemorysettings - *************************************************************************** -*/ + *************************************************************************** +*/ -enum atom_dynamic_memory_setting_command +enum atom_dynamic_memory_setting_command { COMPUTE_MEMORY_PLL_PARAM = 1, COMPUTE_ENGINE_PLL_PARAM = 2, @@ -3857,11 +3857,11 @@ union dynamic_memory_settings_parameters_v2_1 -/* +/* *************************************************************************** Structures used by memorytraining - *************************************************************************** -*/ + *************************************************************************** +*/ enum atom_umc6_0_ucode_function_call_enum_id { @@ -3879,24 +3879,24 @@ struct memory_training_parameters_v2_1 }; -/* +/* *************************************************************************** Structures used by setpixelclock - *************************************************************************** -*/ + *************************************************************************** +*/ struct set_pixel_clock_parameter_v1_7 { - uint32_t pixclk_100hz; // target the pixel clock to drive the CRTC timing in unit of 100Hz. + uint32_t pixclk_100hz; // target the pixel clock to drive the CRTC timing in unit of 100Hz. uint8_t pll_id; // ATOM_PHY_PLL0/ATOM_PHY_PLL1/ATOM_PPLL0 - uint8_t encoderobjid; // ASIC encoder id defined in objectId.h, - // indicate which graphic encoder will be used. - uint8_t encoder_mode; // Encoder mode: + uint8_t encoderobjid; // ASIC encoder id defined in objectId.h, + // indicate which graphic encoder will be used. + uint8_t encoder_mode; // Encoder mode: uint8_t miscinfo; // enum atom_set_pixel_clock_v1_7_misc_info uint8_t crtc_id; // enum of atom_crtc_def uint8_t deep_color_ratio; // HDMI panel bit depth: enum atom_set_pixel_clock_v1_7_deepcolor_ratio - uint8_t reserved1[2]; + uint8_t reserved1[2]; uint32_t reserved2; }; @@ -3911,7 +3911,7 @@ enum atom_set_pixel_clock_v1_7_misc_info PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN = 0x00, PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_PCIE = 0x10, PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK = 0x20, - PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_REFPAD = 0x30, + PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_REFPAD = 0x30, PIXEL_CLOCK_V7_MISC_ATOMIC_UPDATE = 0x40, PIXEL_CLOCK_V7_MISC_FORCE_SS_DIS = 0x80, }; @@ -3919,22 +3919,22 @@ enum atom_set_pixel_clock_v1_7_misc_info /* deep_color_ratio */ enum atom_set_pixel_clock_v1_7_deepcolor_ratio { - PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO - PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4 - PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2 - PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1 + PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO + PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4 + PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2 + PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1 }; -/* +/* *************************************************************************** Structures used by setdceclock - *************************************************************************** -*/ + *************************************************************************** +*/ -// SetDCEClock input parameter for DCE11.2( ELM and BF ) and above +// SetDCEClock input parameter for DCE11.2( ELM and BF ) and above struct set_dce_clock_parameters_v2_1 { - uint32_t dceclk_10khz; // target DCE frequency in unit of 10KHZ, return real DISPCLK/DPREFCLK frequency. + uint32_t dceclk_10khz; // target DCE frequency in unit of 10KHZ, return real DISPCLK/DPREFCLK frequency. uint8_t dceclktype; // =0: DISPCLK =1: DPREFCLK =2: PIXCLK uint8_t dceclksrc; // ATOM_PLL0 or ATOM_GCK_DFS or ATOM_FCH_CLK or ATOM_COMBOPHY_PLLx uint8_t dceclkflag; // Bit [1:0] = PPLL ref clock source ( when ucDCEClkSrc= ATOM_PPLL0 ) @@ -3946,10 +3946,10 @@ enum atom_set_dce_clock_clock_type { DCE_CLOCK_TYPE_DISPCLK = 0, DCE_CLOCK_TYPE_DPREFCLK = 1, - DCE_CLOCK_TYPE_PIXELCLK = 2, // used by VBIOS internally, called by SetPixelClock + DCE_CLOCK_TYPE_PIXELCLK = 2, // used by VBIOS internally, called by SetPixelClock }; -//ucDCEClkFlag when ucDCEClkType == DPREFCLK +//ucDCEClkFlag when ucDCEClkType == DPREFCLK enum atom_set_dce_clock_dprefclk_flag { DCE_CLOCK_FLAG_PLL_REFCLK_SRC_MASK = 0x03, @@ -3959,14 +3959,14 @@ enum atom_set_dce_clock_dprefclk_flag DCE_CLOCK_FLAG_PLL_REFCLK_SRC_XTALIN = 0x03, }; -//ucDCEClkFlag when ucDCEClkType == PIXCLK +//ucDCEClkFlag when ucDCEClkType == PIXCLK enum atom_set_dce_clock_pixclk_flag { DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_MASK = 0x03, - DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO - DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4 - DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2 - DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1 + DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO + DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4 + DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2 + DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1 DCE_CLOCK_FLAG_PIXCLK_YUV420_MODE = 0x04, }; @@ -3977,9 +3977,9 @@ struct set_dce_clock_ps_allocation_v2_1 }; -/****************************************************************************/ +/****************************************************************************/ // Structures used by BlankCRTC -/****************************************************************************/ +/****************************************************************************/ struct blank_crtc_parameters { uint8_t crtc_id; // enum atom_crtc_def @@ -3994,20 +3994,20 @@ enum atom_blank_crtc_command ATOM_BLANKING_OFF = 0, }; -/****************************************************************************/ +/****************************************************************************/ // Structures used by enablecrtc -/****************************************************************************/ +/****************************************************************************/ struct enable_crtc_parameters { uint8_t crtc_id; // enum atom_crtc_def - uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE + uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE uint8_t padding[2]; }; -/****************************************************************************/ +/****************************************************************************/ // Structure used by EnableDispPowerGating -/****************************************************************************/ +/****************************************************************************/ struct enable_disp_power_gating_parameters_v2_1 { uint8_t disp_pipe_id; // ATOM_CRTC1, ATOM_CRTC2, ... @@ -4015,15 +4015,15 @@ struct enable_disp_power_gating_parameters_v2_1 uint8_t padding[2]; }; -struct enable_disp_power_gating_ps_allocation +struct enable_disp_power_gating_ps_allocation { struct enable_disp_power_gating_parameters_v2_1 param; uint32_t ulReserved[4]; }; -/****************************************************************************/ +/****************************************************************************/ // Structure used in setcrtc_usingdtdtiming -/****************************************************************************/ +/****************************************************************************/ struct set_crtc_using_dtd_timing_parameters { uint16_t h_size; @@ -4034,7 +4034,7 @@ struct set_crtc_using_dtd_timing_parameters uint16_t h_syncwidth; uint16_t v_syncoffset; uint16_t v_syncwidth; - uint16_t modemiscinfo; + uint16_t modemiscinfo; uint8_t h_border; uint8_t v_border; uint8_t crtc_id; // enum atom_crtc_def @@ -4043,9 +4043,9 @@ struct set_crtc_using_dtd_timing_parameters }; -/****************************************************************************/ +/****************************************************************************/ // Structures used by processi2cchanneltransaction -/****************************************************************************/ +/****************************************************************************/ struct process_i2c_channel_transaction_parameters { uint8_t i2cspeed_khz; @@ -4077,9 +4077,9 @@ enum atom_process_i2c_status }; -/****************************************************************************/ +/****************************************************************************/ // Structures used by processauxchanneltransaction -/****************************************************************************/ +/****************************************************************************/ struct process_aux_channel_transaction_parameters_v1_2 { @@ -4095,9 +4095,9 @@ struct process_aux_channel_transaction_parameters_v1_2 }; -/****************************************************************************/ +/****************************************************************************/ // Structures used by selectcrtc_source -/****************************************************************************/ +/****************************************************************************/ struct select_crtc_source_parameters_v2_3 { @@ -4108,9 +4108,9 @@ struct select_crtc_source_parameters_v2_3 }; -/****************************************************************************/ +/****************************************************************************/ // Structures used by digxencodercontrol -/****************************************************************************/ +/****************************************************************************/ // ucAction: enum atom_dig_encoder_control_action @@ -4126,8 +4126,8 @@ enum atom_dig_encoder_control_action ATOM_ENCODER_CMD_DP_VIDEO_ON = 0x0d, ATOM_ENCODER_CMD_SETUP_PANEL_MODE = 0x10, ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN4 = 0x14, - ATOM_ENCODER_CMD_STREAM_SETUP = 0x0F, - ATOM_ENCODER_CMD_LINK_SETUP = 0x11, + ATOM_ENCODER_CMD_STREAM_SETUP = 0x0F, + ATOM_ENCODER_CMD_LINK_SETUP = 0x11, ATOM_ENCODER_CMD_ENCODER_BLANK = 0x12, }; @@ -4157,7 +4157,7 @@ struct dig_encoder_stream_setup_parameters_v1_5 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid uint8_t action; // = ATOM_ENOCODER_CMD_STREAM_SETUP uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI - uint8_t lanenum; // Lane number + uint8_t lanenum; // Lane number uint32_t pclk_10khz; // Pixel Clock in 10Khz uint8_t bitpercolor; uint8_t dplinkrate_270mhz;//= DP link rate/270Mhz, =6: 1.62G = 10: 2.7G, =20: 5.4Ghz, =30: 8.1Ghz etc @@ -4167,12 +4167,12 @@ struct dig_encoder_stream_setup_parameters_v1_5 struct dig_encoder_link_setup_parameters_v1_5 { uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid - uint8_t action; // = ATOM_ENOCODER_CMD_LINK_SETUP + uint8_t action; // = ATOM_ENOCODER_CMD_LINK_SETUP uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI - uint8_t lanenum; // Lane number + uint8_t lanenum; // Lane number uint8_t symclk_10khz; // Symbol Clock in 10Khz uint8_t hpd_sel; - uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable, + uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable, uint8_t reserved[2]; }; @@ -4181,15 +4181,15 @@ struct dp_panel_mode_set_parameters_v1_5 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid uint8_t action; // = ATOM_ENCODER_CMD_DPLINK_SETUP uint8_t panelmode; // enum atom_dig_encoder_control_panelmode - uint8_t reserved1; + uint8_t reserved1; uint32_t reserved2[2]; }; -struct dig_encoder_generic_cmd_parameters_v1_5 +struct dig_encoder_generic_cmd_parameters_v1_5 { uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid uint8_t action; // = rest of generic encoder command which does not carry any parameters - uint8_t reserved1[2]; + uint8_t reserved1[2]; uint32_t reserved2[2]; }; @@ -4201,11 +4201,11 @@ union dig_encoder_control_parameters_v1_5 struct dp_panel_mode_set_parameters_v1_5 dppanel_param; }; -/* +/* *************************************************************************** Structures used by dig1transmittercontrol - *************************************************************************** -*/ + *************************************************************************** +*/ struct dig_transmitter_control_parameters_v1_6 { uint8_t phyid; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF @@ -4214,10 +4214,10 @@ struct dig_transmitter_control_parameters_v1_6 uint8_t digmode; // enum atom_encode_mode_def uint8_t dplaneset; // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "DP_LANE_SET__xDB_y_zV" } mode_laneset; - uint8_t lanenum; // Lane number 1, 2, 4, 8 + uint8_t lanenum; // Lane number 1, 2, 4, 8 uint32_t symclk_10khz; // Symbol Clock in 10Khz uint8_t hpdsel; // =1: HPD1, =2: HPD2, .... =6: HPD6, =0: HPD is not assigned - uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable, + uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable, uint8_t connobj_id; // Connector Object Id defined in ObjectId.h uint8_t reserved; uint32_t reserved1; @@ -4280,29 +4280,29 @@ enum atom_dig_transmitter_control_dplaneset DP_LANE_SET__0DB_0_6V = 0x01, DP_LANE_SET__0DB_0_8V = 0x02, DP_LANE_SET__0DB_1_2V = 0x03, - DP_LANE_SET__3_5DB_0_4V = 0x08, + DP_LANE_SET__3_5DB_0_4V = 0x08, DP_LANE_SET__3_5DB_0_6V = 0x09, DP_LANE_SET__3_5DB_0_8V = 0x0a, DP_LANE_SET__6DB_0_4V = 0x10, DP_LANE_SET__6DB_0_6V = 0x11, - DP_LANE_SET__9_5DB_0_4V = 0x18, + DP_LANE_SET__9_5DB_0_4V = 0x18, }; -/****************************************************************************/ +/****************************************************************************/ // Structures used by ExternalEncoderControl V2.4 -/****************************************************************************/ +/****************************************************************************/ struct external_encoder_control_parameters_v2_4 { - uint16_t pixelclock_10khz; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT - uint8_t config; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT - uint8_t action; // + uint16_t pixelclock_10khz; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT + uint8_t config; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT + uint8_t action; // uint8_t encodermode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT - uint8_t lanenum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT + uint8_t lanenum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT uint8_t bitpercolor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP - uint8_t hpd_id; + uint8_t hpd_id; }; @@ -4326,7 +4326,7 @@ enum external_encoder_control_v2_4_config_def EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ = 0x00, EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ = 0x01, EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ = 0x02, - EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_3_24GHZ = 0x03, + EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_3_24GHZ = 0x03, EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MAKS = 0x70, EXTERNAL_ENCODER_CONFIG_V3_ENCODER1 = 0x00, EXTERNAL_ENCODER_CONFIG_V3_ENCODER2 = 0x10, @@ -4340,12 +4340,12 @@ struct external_encoder_control_ps_allocation_v2_4 }; -/* +/* *************************************************************************** AMD ACPI Table - - *************************************************************************** -*/ + + *************************************************************************** +*/ struct amd_acpi_description_header{ uint32_t signature; @@ -4392,13 +4392,13 @@ struct gop_lib1_content { -/* +/* *************************************************************************** Scratch Register definitions - Each number below indicates which scratch regiser request, Active and + Each number below indicates which scratch regiser request, Active and Connect all share the same definitions as display_device_tag defines - *************************************************************************** -*/ + *************************************************************************** +*/ enum scratch_register_def{ ATOM_DEVICE_CONNECT_INFO_DEF = 0, @@ -4480,12 +4480,12 @@ enum scratch_pre_os_mode_info_bits_def{ -/* +/* *************************************************************************** ATOM firmware ID header file !! Please keep it at end of the atomfirmware.h !! - *************************************************************************** -*/ + *************************************************************************** +*/ #include "atomfirmwareid.h" #pragma pack() diff --git a/sys/dev/pci/drm/amd/include/atomfirmwareid.h b/sys/dev/pci/drm/amd/include/atomfirmwareid.h index e6256efd0..a64fb1173 100644 --- a/sys/dev/pci/drm/amd/include/atomfirmwareid.h +++ b/sys/dev/pci/drm/amd/include/atomfirmwareid.h @@ -1,12 +1,12 @@ /****************************************************************************\ -* +* * File Name atomfirmwareid.h * * Description ATOM BIOS command/data table ID definition header file * * Copyright 2016 Advanced Micro Devices, Inc. * -* Permission is hereby granted, free of charge, to any person obtaining a copy of this software +* Permission is hereby granted, free of charge, to any person obtaining a copy of this software * and associated documentation files (the "Software"), to deal in the Software without restriction, * including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, diff --git a/sys/dev/pci/drm/amd/include/displayobject.h b/sys/dev/pci/drm/amd/include/displayobject.h index 67e23ff9c..687be3437 100644 --- a/sys/dev/pci/drm/amd/include/displayobject.h +++ b/sys/dev/pci/drm/amd/include/displayobject.h @@ -1,14 +1,14 @@ /****************************************************************************\ -* +* * Module Name displayobjectsoc15.h -* Project -* Device +* Project +* Device * * Description Contains the common definitions for display objects for SoC15 products. * * Copyright 2014 Advanced Micro Devices, Inc. * -* Permission is hereby granted, free of charge, to any person obtaining a copy of this software +* Permission is hereby granted, free of charge, to any person obtaining a copy of this software * and associated documentation files (the "Software"), to deal in the Software without restriction, * including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, @@ -35,7 +35,7 @@ /**************************************************** -* Display Object Type Definition +* Display Object Type Definition *****************************************************/ enum display_object_type{ DISPLAY_OBJECT_TYPE_NONE =0x00, @@ -45,7 +45,7 @@ DISPLAY_OBJECT_TYPE_CONNECTOR =0x03 }; /**************************************************** -* Encorder Object Type Definition +* Encorder Object Type Definition *****************************************************/ enum encoder_object_type{ ENCODER_OBJECT_ID_NONE =0x00, @@ -56,11 +56,11 @@ ENCODER_OBJECT_ID_INTERNAL_UNIPHY2 =0x03, /**************************************************** -* Connector Object ID Definition +* Connector Object ID Definition *****************************************************/ enum connector_object_type{ -CONNECTOR_OBJECT_ID_NONE =0x00, +CONNECTOR_OBJECT_ID_NONE =0x00, CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D =0x01, CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D =0x02, CONNECTOR_OBJECT_ID_HDMI_TYPE_A =0x03, @@ -72,12 +72,12 @@ CONNECTOR_OBJECT_ID_OPM =0x07 /**************************************************** -* Protection Object ID Definition +* Protection Object ID Definition *****************************************************/ //No need /**************************************************** -* Object ENUM ID Definition +* Object ENUM ID Definition *****************************************************/ enum object_enum_id{ @@ -90,7 +90,7 @@ OBJECT_ENUM_ID6 =0x06 }; /**************************************************** -*Object ID Bit definition +*Object ID Bit definition *****************************************************/ enum object_id_bit{ OBJECT_ID_MASK =0x00FF, diff --git a/sys/dev/pci/drm/amd/include/navi10_ip_offset.h b/sys/dev/pci/drm/amd/include/navi10_ip_offset.h index d6824bb61..3a4723c4a 100644 --- a/sys/dev/pci/drm/amd/include/navi10_ip_offset.h +++ b/sys/dev/pci/drm/amd/include/navi10_ip_offset.h @@ -28,7 +28,7 @@ struct IP_BASE_INSTANCE { unsigned int segment[MAX_SEGMENT]; }; - + struct IP_BASE { struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; } __maybe_unused; diff --git a/sys/dev/pci/drm/amd/include/pptable.h b/sys/dev/pci/drm/amd/include/pptable.h index 0b6a057e0..0e54e1317 100644 --- a/sys/dev/pci/drm/amd/include/pptable.h +++ b/sys/dev/pci/drm/amd/include/pptable.h @@ -133,7 +133,7 @@ typedef struct _ATOM_PPLIB_EXTENDEDHEADER USHORT usUVDTableOffset; //points to ATOM_PPLIB_UVD_Table USHORT usSAMUTableOffset; //points to ATOM_PPLIB_SAMU_Table USHORT usPPMTableOffset; //points to ATOM_PPLIB_PPM_Table - USHORT usACPTableOffset; //points to ATOM_PPLIB_ACP_Table + USHORT usACPTableOffset; //points to ATOM_PPLIB_ACP_Table /* points to ATOM_PPLIB_POWERTUNE_Table */ USHORT usPowerTuneTableOffset; /* points to ATOM_PPLIB_CLOCK_Voltage_Dependency_Table for sclkVddgfxTable */ @@ -223,14 +223,14 @@ typedef struct _ATOM_PPLIB_POWERPLAYTABLE3 typedef struct _ATOM_PPLIB_POWERPLAYTABLE4 { ATOM_PPLIB_POWERPLAYTABLE3 basicTable3; - ULONG ulGoldenPPID; // PPGen use only + ULONG ulGoldenPPID; // PPGen use only ULONG ulGoldenRevision; // PPGen use only USHORT usVddcDependencyOnSCLKOffset; USHORT usVddciDependencyOnMCLKOffset; USHORT usVddcDependencyOnMCLKOffset; USHORT usMaxClockVoltageOnDCOffset; USHORT usVddcPhaseShedLimitsTableOffset; // Points to ATOM_PPLIB_PhaseSheddingLimits_Table - USHORT usMvddDependencyOnMCLKOffset; + USHORT usMvddDependencyOnMCLKOffset; } ATOM_PPLIB_POWERPLAYTABLE4, *LPATOM_PPLIB_POWERPLAYTABLE4; typedef struct _ATOM_PPLIB_POWERPLAYTABLE5 @@ -376,21 +376,21 @@ typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO UCHAR ucMaxHTLinkWidth; // From SBIOS - {2, 4, 8, 16} UCHAR ucMinHTLinkWidth; // From SBIOS - {2, 4, 8, 16}. Effective only if CDLW enabled. Minimum down stream width could USHORT usHTLinkFreq; // See definition ATOM_PPLIB_RS780_HTLINKFREQ_xxx or in MHz(>=200). - ULONG ulFlags; + ULONG ulFlags; } ATOM_PPLIB_RS780_CLOCK_INFO; -#define ATOM_PPLIB_RS780_VOLTAGE_NONE 0 -#define ATOM_PPLIB_RS780_VOLTAGE_LOW 1 -#define ATOM_PPLIB_RS780_VOLTAGE_HIGH 2 -#define ATOM_PPLIB_RS780_VOLTAGE_VARIABLE 3 +#define ATOM_PPLIB_RS780_VOLTAGE_NONE 0 +#define ATOM_PPLIB_RS780_VOLTAGE_LOW 1 +#define ATOM_PPLIB_RS780_VOLTAGE_HIGH 2 +#define ATOM_PPLIB_RS780_VOLTAGE_VARIABLE 3 #define ATOM_PPLIB_RS780_SPMCLK_NONE 0 // We cannot change the side port memory clock, leave it as it is. #define ATOM_PPLIB_RS780_SPMCLK_LOW 1 #define ATOM_PPLIB_RS780_SPMCLK_HIGH 2 -#define ATOM_PPLIB_RS780_HTLINKFREQ_NONE 0 -#define ATOM_PPLIB_RS780_HTLINKFREQ_LOW 1 -#define ATOM_PPLIB_RS780_HTLINKFREQ_HIGH 2 +#define ATOM_PPLIB_RS780_HTLINKFREQ_NONE 0 +#define ATOM_PPLIB_RS780_HTLINKFREQ_LOW 1 +#define ATOM_PPLIB_RS780_HTLINKFREQ_HIGH 2 typedef struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO { @@ -432,14 +432,14 @@ typedef struct _ATOM_PPLIB_CI_CLOCK_INFO USHORT usMemoryClockLow; UCHAR ucMemoryClockHigh; - + UCHAR ucPCIEGen; USHORT usPCIELane; } ATOM_PPLIB_CI_CLOCK_INFO; typedef struct _ATOM_PPLIB_SUMO_CLOCK_INFO{ USHORT usEngineClockLow; //clockfrequency & 0xFFFF. The unit is in 10khz - UCHAR ucEngineClockHigh; //clockfrequency >> 16. + UCHAR ucEngineClockHigh; //clockfrequency >> 16. UCHAR vddcIndex; //2-bit vddc index; USHORT tdpLimit; //please initalize to 0 @@ -464,10 +464,10 @@ typedef struct _ATOM_PPLIB_CZ_CLOCK_INFO { typedef struct _ATOM_PPLIB_STATE_V2 { - //number of valid dpm levels in this state; Driver uses it to calculate the whole + //number of valid dpm levels in this state; Driver uses it to calculate the whole //size of the state: sizeof(ATOM_PPLIB_STATE_V2) + (ucNumDPMLevels - 1) * sizeof(UCHAR) UCHAR ucNumDPMLevels; - + //a index to the array of nonClockInfos UCHAR nonClockInfoIndex; /** @@ -477,9 +477,9 @@ typedef struct _ATOM_PPLIB_STATE_V2 } ATOM_PPLIB_STATE_V2; typedef struct _StateArray{ - //how many states we have + //how many states we have UCHAR ucNumEntries; - + ATOM_PPLIB_STATE_V2 states[1]; }StateArray; @@ -487,10 +487,10 @@ typedef struct _StateArray{ typedef struct _ClockInfoArray{ //how many clock levels we have UCHAR ucNumEntries; - + //sizeof(ATOM_PPLIB_CLOCK_INFO) UCHAR ucEntrySize; - + UCHAR clockInfo[1]; }ClockInfoArray; @@ -500,7 +500,7 @@ typedef struct _NonClockInfoArray{ UCHAR ucNumEntries; //sizeof(ATOM_PPLIB_NONCLOCK_INFO) UCHAR ucEntrySize; - + ATOM_PPLIB_NONCLOCK_INFO nonClockInfo[1]; }NonClockInfoArray; @@ -722,7 +722,7 @@ typedef struct _ATOM_PPLIB_PPM_Table ULONG ulPlatformTDC; ULONG ulSmallACPlatformTDC; ULONG ulApuTDP; - ULONG ulDGpuTDP; + ULONG ulDGpuTDP; ULONG ulDGpuUlvPower; ULONG ulTjmax; } ATOM_PPLIB_PPM_Table; diff --git a/sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h b/sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h index 6456bea5d..5cf62a929 100644 --- a/sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h +++ b/sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h @@ -365,7 +365,7 @@ typedef struct { uint16_t FanMaximumRpm; uint16_t FanTargetTemperature; uint16_t FanTargetGfxclk; - uint8_t FanZeroRpmEnable; + uint8_t FanZeroRpmEnable; uint8_t FanTachEdgePerRev; @@ -659,8 +659,8 @@ typedef struct { uint8_t Gfx_IdleHystLimit; uint8_t Gfx_FPS; uint8_t Gfx_MinActiveFreqType; - uint8_t Gfx_BoosterFreqType; - uint8_t Gfx_UseRlcBusy; + uint8_t Gfx_BoosterFreqType; + uint8_t Gfx_UseRlcBusy; uint16_t Gfx_MinActiveFreq; uint16_t Gfx_BoosterFreq; uint16_t Gfx_PD_Data_time_constant; @@ -674,7 +674,7 @@ typedef struct { uint8_t Soc_IdleHystLimit; uint8_t Soc_FPS; uint8_t Soc_MinActiveFreqType; - uint8_t Soc_BoosterFreqType; + uint8_t Soc_BoosterFreqType; uint8_t Soc_UseRlcBusy; uint16_t Soc_MinActiveFreq; uint16_t Soc_BoosterFreq; @@ -690,7 +690,7 @@ typedef struct { uint8_t Mem_FPS; uint8_t Mem_MinActiveFreqType; uint8_t Mem_BoosterFreqType; - uint8_t Mem_UseRlcBusy; + uint8_t Mem_UseRlcBusy; uint16_t Mem_MinActiveFreq; uint16_t Mem_BoosterFreq; uint16_t Mem_PD_Data_time_constant; diff --git a/sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h index adcf99148..d3b79f211 100644 --- a/sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h +++ b/sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h @@ -1312,8 +1312,8 @@ struct pptable_funcs { * @get_ecc_table: message SMU to get ECC INFO table. */ ssize_t (*get_ecc_info)(struct smu_context *smu, void *table); - - + + /** * @stb_collect_info: Collects Smart Trace Buffers data. */ diff --git a/sys/dev/pci/drm/drm_drv.c b/sys/dev/pci/drm/drm_drv.c index 940830493..02b0e50c7 100644 --- a/sys/dev/pci/drm/drm_drv.c +++ b/sys/dev/pci/drm/drm_drv.c @@ -90,7 +90,7 @@ DEFINE_STATIC_SRCU(drm_unplug_srcu); * Some functions are only called once on init regardless of how many times * drm attaches. In linux this is handled via module_init()/module_exit() */ -int drm_refcnt; +int drm_refcnt; struct drm_softc { struct device sc_dev; @@ -1225,7 +1225,7 @@ drm_attach_pci(const struct drm_driver *driver, struct pci_attach_args *pa, sc = (struct drm_softc *)config_found_sm(dev, &arg, drmprint, drmsubmatch); if (sc == NULL) return NULL; - + return sc->sc_drm; } @@ -1522,7 +1522,7 @@ const struct pci_device_id * drm_find_description(int vendor, int device, const struct pci_device_id *idlist) { int i = 0; - + for (i = 0; idlist[i].vendor != 0; i++) { if ((idlist[i].vendor == vendor) && (idlist[i].device == device || @@ -1546,7 +1546,7 @@ struct drm_file * drm_find_file_by_minor(struct drm_device *dev, int minor) { struct drm_file key; - + key.fminor = minor; return (SPLAY_FIND(drm_file_tree, &dev->files, &key)); } @@ -1886,7 +1886,7 @@ drm_dmamem_alloc(bus_dma_tag_t dmat, bus_size_t size, bus_size_t alignment, struct drm_dmamem *mem; size_t strsize; /* - * segs is the last member of the struct since we modify the size + * segs is the last member of the struct since we modify the size * to allow extra segments if more than one are allowed. */ strsize = sizeof(*mem) + (sizeof(bus_dma_segment_t) * (nsegments - 1)); @@ -1904,7 +1904,7 @@ drm_dmamem_alloc(bus_dma_tag_t dmat, bus_size_t size, bus_size_t alignment, &mem->nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO) != 0) goto destroy; - if (bus_dmamem_map(dmat, mem->segs, mem->nsegs, size, + if (bus_dmamem_map(dmat, mem->segs, mem->nsegs, size, &mem->kva, BUS_DMA_NOWAIT | mapflags) != 0) goto free; diff --git a/sys/dev/pci/drm/drm_gem.c b/sys/dev/pci/drm/drm_gem.c index b91420bf2..fb701923f 100644 --- a/sys/dev/pci/drm/drm_gem.c +++ b/sys/dev/pci/drm/drm_gem.c @@ -102,7 +102,7 @@ drm_fault(struct uvm_faultinfo *ufi, vaddr_t vaddr, vm_page_t *pps, * we do not allow device mappings to be mapped copy-on-write * so we kill any attempt to do so here. */ - + if (UVM_ET_ISCOPYONWRITE(entry)) { uvmfault_unlockall(ufi, ufi->entry->aref.ar_amap, uobj); return(VM_PAGER_ERROR); @@ -144,7 +144,7 @@ drm_fault(struct uvm_faultinfo *ufi, vaddr_t vaddr, vm_page_t *pps, return (ret); } -boolean_t +boolean_t drm_flush(struct uvm_object *uobj, voff_t start, voff_t stop, int flags) { return (TRUE); @@ -309,10 +309,10 @@ int drm_gem_object_init(struct drm_device *dev, printf("%s size too big %lu\n", __func__, size); return -ENOMEM; } - + obj->uao = uao_create(size, 0); uvm_obj_init(&obj->uobj, &drm_pgops, 1); - + return 0; } diff --git a/sys/dev/pci/drm/drm_linux.c b/sys/dev/pci/drm/drm_linux.c index bcec033e2..f97ba022d 100644 --- a/sys/dev/pci/drm/drm_linux.c +++ b/sys/dev/pci/drm/drm_linux.c @@ -251,7 +251,7 @@ kthread_run(int (*func)(void *), void *data, const char *name) thread->func = func; thread->data = data; thread->flags = 0; - + if (kthread_create(kthread_func, thread, &thread->proc, name)) { free(thread, M_DRM, sizeof(*thread)); return ERR_PTR(-ENOMEM); @@ -272,7 +272,7 @@ kthread_create_worker(unsigned int flags, const char *fmt, ...) vsnprintf(name, sizeof(name), fmt, ap); va_end(ap); w->tq = taskq_create(name, 1, IPL_HIGH, 0); - + return w; } @@ -281,7 +281,7 @@ kthread_destroy_worker(struct kthread_worker *worker) { taskq_destroy(worker->tq); free(worker, M_DRM, sizeof(*worker)); - + } void @@ -551,7 +551,7 @@ __free_pages(struct vm_page *page, unsigned int order) { struct pglist mlist; int i; - + TAILQ_INIT(&mlist); for (i = 0; i < (1 << order); i++) TAILQ_INSERT_TAIL(&mlist, &page[i], pageq); @@ -623,7 +623,7 @@ void kunmap_atomic(void *addr) { KASSERT(kmap_atomic_inuse); - + pmap_kremove(kmap_atomic_va, PAGE_SIZE); kmap_atomic_inuse = 0; } @@ -1193,7 +1193,7 @@ retry: int i2c_transfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) { - int ret; + int ret; if (adap->lock_ops) adap->lock_ops->lock_bus(adap, 0); @@ -1497,7 +1497,7 @@ backlight_device_register(const char *name, void *kdev, void *data, bd->data = data; task_set(&bd->task, backlight_do_update_status, bd); - + return bd; } @@ -1720,7 +1720,7 @@ dma_fence_wait(struct dma_fence *fence, bool intr) ret = dma_fence_wait_timeout(fence, intr, MAX_SCHEDULE_TIMEOUT); if (ret < 0) return ret; - + return 0; } @@ -1880,7 +1880,7 @@ dma_fence_default_wait(struct dma_fence *fence, bool intr, signed long timeout) list_del(&cb.base.node); out: mtx_leave(fence->lock); - + return ret; } @@ -1926,7 +1926,7 @@ dma_fence_wait_any_timeout(struct dma_fence **fences, uint32_t count, cb = mallocarray(count, sizeof(*cb), M_DRM, M_WAITOK|M_CANFAIL|M_ZERO); if (cb == NULL) return -ENOMEM; - + for (i = 0; i < count; i++) { struct dma_fence *fence = fences[i]; cb[i].proc = curproc; @@ -2022,7 +2022,7 @@ dma_fence_array_cb_func(struct dma_fence *f, struct dma_fence_cb *cb) struct dma_fence_array_cb *array_cb = container_of(cb, struct dma_fence_array_cb, cb); struct dma_fence_array *dfa = array_cb->array; - + if (atomic_dec_and_test(&dfa->num_pending)) timeout_add(&dfa->to, 1); else @@ -2046,7 +2046,7 @@ dma_fence_array_enable_signaling(struct dma_fence *fence) return false; } } - + return true; } @@ -2526,7 +2526,7 @@ pcie_get_speed_cap(struct pci_dev *pdev) tag = pdev->tag; if (!pci_get_capability(pc, tag, PCI_CAP_PCIEXPRESS, - &pos, NULL)) + &pos, NULL)) return PCI_SPEED_UNKNOWN; id = pci_conf_read(pc, tag, PCI_ID_REG); @@ -2582,7 +2582,7 @@ pcie_get_width_cap(struct pci_dev *pdev) int bus, device, function; if (!pci_get_capability(pc, tag, PCI_CAP_PCIEXPRESS, - &pos, NULL)) + &pos, NULL)) return PCIE_LNK_WIDTH_UNKNOWN; id = pci_conf_read(pc, tag, PCI_ID_REG); @@ -2607,13 +2607,13 @@ pcie_aspm_enabled(struct pci_dev *pdev) pcireg_t lcsr; if (!pci_get_capability(pc, tag, PCI_CAP_PCIEXPRESS, - &pos, NULL)) + &pos, NULL)) return false; lcsr = pci_conf_read(pc, tag, pos + PCI_PCIE_LCSR); if ((lcsr & (PCI_PCIE_LCSR_ASPM_L0S | PCI_PCIE_LCSR_ASPM_L1)) != 0) return true; - + return false; } @@ -2896,7 +2896,7 @@ interval_tree_iter_first(struct rb_root_cached *root, unsigned long start, void interval_tree_remove(struct interval_tree_node *node, - struct rb_root_cached *root) + struct rb_root_cached *root) { rb_erase_cached(&node->rb, root); } @@ -3021,7 +3021,7 @@ fput(struct file *fp) { if (fp->f_type != DTYPE_SYNC) return; - + FRELE(fp, curproc); } diff --git a/sys/dev/pci/drm/drm_lock.c b/sys/dev/pci/drm/drm_lock.c index 1efbd5389..168c977ca 100644 --- a/sys/dev/pci/drm/drm_lock.c +++ b/sys/dev/pci/drm/drm_lock.c @@ -223,7 +223,7 @@ int drm_legacy_lock(struct drm_device *dev, void *data, ret ? "interrupted" : "has lock"); if (ret) return ret; - /* don't set the block all signals on the master process for now + /* don't set the block all signals on the master process for now * really probably not the correct answer but lets us debug xkb * xserver for now */ if (!drm_is_current_master(file_priv)) { diff --git a/sys/dev/pci/drm/drm_managed.c b/sys/dev/pci/drm/drm_managed.c index 5f5176672..003a1e112 100644 --- a/sys/dev/pci/drm/drm_managed.c +++ b/sys/dev/pci/drm/drm_managed.c @@ -95,7 +95,7 @@ drmm_kfree(struct drm_device *dev, void *p) } } mtx_leave(&dev->managed.lock); - + if (m != NULL) { free(m->p, M_DRM, m->size); free(m, M_DRM, sizeof(*m)); diff --git a/sys/dev/pci/drm/drm_mm.c b/sys/dev/pci/drm/drm_mm.c index 17c3fffcd..b3b1a355c 100644 --- a/sys/dev/pci/drm/drm_mm.c +++ b/sys/dev/pci/drm/drm_mm.c @@ -174,7 +174,7 @@ drm_mm_interval_tree_iter_first(const struct rb_root_cached *root, static void drm_mm_interval_tree_remove(struct drm_mm_node *node, - struct rb_root_cached *root) + struct rb_root_cached *root) { rb_erase_cached(&node->rb, root); } diff --git a/sys/dev/pci/drm/i915/gt/agp_intel_gtt.c b/sys/dev/pci/drm/i915/gt/agp_intel_gtt.c index 5b3d56e7d..0a52e575f 100644 --- a/sys/dev/pci/drm/i915/gt/agp_intel_gtt.c +++ b/sys/dev/pci/drm/i915/gt/agp_intel_gtt.c @@ -177,7 +177,7 @@ intel_gmch_gtt_get(u64 *gtt_total, { struct inteldrm_softc *dev_priv = (void *)inteldrm_cd.cd_devs[0]; struct agp_info *ai = &dev_priv->drm.agp->info; - + *gtt_total = ai->ai_aperture_size; *mappable_base = ai->ai_aperture_base; *mappable_end = ai->ai_aperture_size; diff --git a/sys/dev/pci/drm/i915/gt/shmem_utils.c b/sys/dev/pci/drm/i915/gt/shmem_utils.c index d41ffb782..193f110f1 100644 --- a/sys/dev/pci/drm/i915/gt/shmem_utils.c +++ b/sys/dev/pci/drm/i915/gt/shmem_utils.c @@ -228,7 +228,7 @@ static int __uao_rw(struct uvm_object *uao, loff_t off, unsigned int this = min_t(size_t, PAGE_SIZE - offset_in_page(off), len); void *vaddr = kmap(page); - + if (write) { memcpy(vaddr + offset_in_page(off), ptr, this); set_page_dirty(page); diff --git a/sys/dev/pci/drm/include/linux/atomic.h b/sys/dev/pci/drm/include/linux/atomic.h index fb785a0c9..3e13af4dc 100644 --- a/sys/dev/pci/drm/include/linux/atomic.h +++ b/sys/dev/pci/drm/include/linux/atomic.h @@ -2,7 +2,7 @@ /** * \file drm_atomic.h * Atomic operations used in the DRM which may or may not be provided by the OS. - * + * * \author Eric Anholt */ @@ -298,7 +298,7 @@ __test_and_set_bit(u_int b, volatile void *p) volatile u_int *ptr = (volatile u_int *)p; unsigned int prev = ptr[b >> 5]; ptr[b >> 5] |= m; - + return (prev & m) != 0; } @@ -428,7 +428,7 @@ find_next_bit(const volatile void *p, int max, int b) #define wmb() __membar("dsb sy") #define mb() __membar("dsb sy") #elif defined(__mips64__) -#define rmb() mips_sync() +#define rmb() mips_sync() #define wmb() mips_sync() #define mb() mips_sync() #elif defined(__powerpc64__) diff --git a/sys/dev/pci/drm/include/linux/capability.h b/sys/dev/pci/drm/include/linux/capability.h index c91b233d9..5accf04f7 100644 --- a/sys/dev/pci/drm/include/linux/capability.h +++ b/sys/dev/pci/drm/include/linux/capability.h @@ -12,8 +12,8 @@ #define CAP_SYS_NICE 0x2 static inline bool -capable(int cap) -{ +capable(int cap) +{ switch (cap) { case CAP_SYS_ADMIN: case CAP_SYS_NICE: @@ -21,7 +21,7 @@ capable(int cap) default: panic("unhandled capability"); } -} +} static inline bool perfmon_capable(void) diff --git a/sys/dev/pci/drm/include/linux/dma-buf.h b/sys/dev/pci/drm/include/linux/dma-buf.h index 32f05c309..f789e8d20 100644 --- a/sys/dev/pci/drm/include/linux/dma-buf.h +++ b/sys/dev/pci/drm/include/linux/dma-buf.h @@ -61,7 +61,7 @@ struct dma_buf_export_info { struct dma_resv *resv; }; -#define DEFINE_DMA_BUF_EXPORT_INFO(x) struct dma_buf_export_info x +#define DEFINE_DMA_BUF_EXPORT_INFO(x) struct dma_buf_export_info x struct dma_buf *dma_buf_export(const struct dma_buf_export_info *); diff --git a/sys/dev/pci/drm/include/linux/file.h b/sys/dev/pci/drm/include/linux/file.h index f59981db1..e27bfaddf 100644 --- a/sys/dev/pci/drm/include/linux/file.h +++ b/sys/dev/pci/drm/include/linux/file.h @@ -4,7 +4,7 @@ #define _LINUX_FILE_H /* both for printf */ -#include +#include #include void fd_install(int, struct file *); diff --git a/sys/dev/pci/drm/include/linux/interrupt.h b/sys/dev/pci/drm/include/linux/interrupt.h index b555183c9..13a154522 100644 --- a/sys/dev/pci/drm/include/linux/interrupt.h +++ b/sys/dev/pci/drm/include/linux/interrupt.h @@ -106,7 +106,7 @@ tasklet_hi_schedule(struct tasklet_struct *ts) task_add(taskletq, &ts->task); } -static inline void +static inline void tasklet_disable_nosync(struct tasklet_struct *ts) { atomic_inc(&ts->count); diff --git a/sys/dev/pci/drm/include/linux/io.h b/sys/dev/pci/drm/include/linux/io.h index 08e20aa0c..201772580 100644 --- a/sys/dev/pci/drm/include/linux/io.h +++ b/sys/dev/pci/drm/include/linux/io.h @@ -119,7 +119,7 @@ static inline u32 ioread32(const volatile void __iomem *addr) { uint32_t val; - + iobarrier(); val = lemtoh32(addr); rmb(); diff --git a/sys/dev/pci/drm/include/linux/pci.h b/sys/dev/pci/drm/include/linux/pci.h index 3f8de6b86..1021bb7ee 100644 --- a/sys/dev/pci/drm/include/linux/pci.h +++ b/sys/dev/pci/drm/include/linux/pci.h @@ -135,7 +135,7 @@ pci_read_config_dword(struct pci_dev *pdev, int reg, u32 *val) { *val = pci_conf_read(pdev->pc, pdev->tag, reg); return 0; -} +} static inline int pci_read_config_word(struct pci_dev *pdev, int reg, u16 *val) @@ -145,7 +145,7 @@ pci_read_config_word(struct pci_dev *pdev, int reg, u16 *val) v = pci_conf_read(pdev->pc, pdev->tag, (reg & ~0x2)); *val = (v >> ((reg & 0x2) * 8)); return 0; -} +} static inline int pci_read_config_byte(struct pci_dev *pdev, int reg, u8 *val) @@ -155,14 +155,14 @@ pci_read_config_byte(struct pci_dev *pdev, int reg, u8 *val) v = pci_conf_read(pdev->pc, pdev->tag, (reg & ~0x3)); *val = (v >> ((reg & 0x3) * 8)); return 0; -} +} static inline int pci_write_config_dword(struct pci_dev *pdev, int reg, u32 val) { pci_conf_write(pdev->pc, pdev->tag, reg, val); return 0; -} +} static inline int pci_write_config_word(struct pci_dev *pdev, int reg, u16 val) @@ -174,7 +174,7 @@ pci_write_config_word(struct pci_dev *pdev, int reg, u16 val) v |= (val << ((reg & 0x2) * 8)); pci_conf_write(pdev->pc, pdev->tag, (reg & ~0x2), v); return 0; -} +} static inline int pci_write_config_byte(struct pci_dev *pdev, int reg, u8 val) @@ -319,7 +319,7 @@ static inline int pcie_set_readrq(struct pci_dev *pdev, int rrq) { uint16_t val; - + pcie_capability_read_word(pdev, PCI_PCIE_DCSR, &val); val &= ~PCI_PCIE_DCSR_MPS; val |= (ffs(rrq) - 8) << 12; diff --git a/sys/dev/pci/drm/include/linux/rbtree.h b/sys/dev/pci/drm/include/linux/rbtree.h index 39d013afd..40cbdf7fb 100644 --- a/sys/dev/pci/drm/include/linux/rbtree.h +++ b/sys/dev/pci/drm/include/linux/rbtree.h @@ -99,7 +99,7 @@ __rb_deepest_left(struct rb_node *node) else node = RB_RIGHT(node, __entry); } - return parent; + return parent; } static inline struct rb_node * diff --git a/sys/dev/pci/drm/include/linux/scatterlist.h b/sys/dev/pci/drm/include/linux/scatterlist.h index b2c0cb50d..afbb0180a 100644 --- a/sys/dev/pci/drm/include/linux/scatterlist.h +++ b/sys/dev/pci/drm/include/linux/scatterlist.h @@ -77,7 +77,7 @@ static inline bool __sg_page_iter_next(struct sg_page_iter *iter) { iter->sg_pgoffset++; - while (iter->__nents > 0 && + while (iter->__nents > 0 && iter->sg_pgoffset >= (iter->sg->length / PAGE_SIZE)) { iter->sg_pgoffset -= (iter->sg->length / PAGE_SIZE); iter->sg++; diff --git a/sys/dev/pci/drm/include/linux/seqlock.h b/sys/dev/pci/drm/include/linux/seqlock.h index e3dabf2c9..f2d0f9dd8 100644 --- a/sys/dev/pci/drm/include/linux/seqlock.h +++ b/sys/dev/pci/drm/include/linux/seqlock.h @@ -91,7 +91,7 @@ typedef struct { static inline void seqlock_init(seqlock_t *sl, int wantipl) -{ +{ sl->seq = 0; mtx_init(&sl->lock, wantipl); } diff --git a/sys/dev/pci/drm/include/linux/string.h b/sys/dev/pci/drm/include/linux/string.h index f76ddf6f6..6dc172235 100644 --- a/sys/dev/pci/drm/include/linux/string.h +++ b/sys/dev/pci/drm/include/linux/string.h @@ -74,7 +74,7 @@ match_string(const char * const *array, size_t n, const char *str) for (i = 0; i < n; i++) { if (array[i] == NULL) break; - if (!strcmp(array[i], str)) + if (!strcmp(array[i], str)) return i; } diff --git a/sys/dev/pci/drm/include/linux/swap.h b/sys/dev/pci/drm/include/linux/swap.h index dcfb9c9d1..7a16f8006 100644 --- a/sys/dev/pci/drm/include/linux/swap.h +++ b/sys/dev/pci/drm/include/linux/swap.h @@ -30,11 +30,11 @@ static inline long get_nr_swap_pages(void) -{ +{ return uvmexp.swpages - uvmexp.swpginuse; } -/* +/* * XXX For now, we don't want the shrinker to be too aggressive, so * pretend we're not called from the pagedaemon even if we are. */ diff --git a/sys/dev/pci/drm/include/linux/types.h b/sys/dev/pci/drm/include/linux/types.h index 6b3de73cd..de79e778b 100644 --- a/sys/dev/pci/drm/include/linux/types.h +++ b/sys/dev/pci/drm/include/linux/types.h @@ -30,12 +30,12 @@ typedef uint32_t u32; typedef int64_t s64; typedef uint64_t u64; -typedef uint16_t __le16; -typedef uint16_t __be16; -typedef uint32_t __le32; +typedef uint16_t __le16; +typedef uint16_t __be16; +typedef uint32_t __le32; typedef uint32_t __be32; -typedef uint64_t __le64; -typedef uint64_t __be64; +typedef uint64_t __le64; +typedef uint64_t __be64; typedef bus_addr_t dma_addr_t; typedef paddr_t phys_addr_t; diff --git a/sys/dev/pci/drm/include/linux/wait.h b/sys/dev/pci/drm/include/linux/wait.h index 758c0b1e5..7983854a9 100644 --- a/sys/dev/pci/drm/include/linux/wait.h +++ b/sys/dev/pci/drm/include/linux/wait.h @@ -221,7 +221,7 @@ wake_up(wait_queue_head_t *wqh) wait_queue_entry_t *wqe; wait_queue_entry_t *tmp; mtx_enter(&wqh->lock); - + list_for_each_entry_safe(wqe, tmp, &wqh->head, entry) { KASSERT(wqe->func != NULL); if (wqe->func != NULL) @@ -255,7 +255,7 @@ wake_up_all_locked(wait_queue_head_t *wqh) .private = curproc, \ .func = autoremove_wake_function, \ .entry = LIST_HEAD_INIT((name).entry), \ - } + } static inline void prepare_to_wait(wait_queue_head_t *wqh, wait_queue_entry_t *wqe, int state) diff --git a/sys/dev/pci/drm/include/linux/ww_mutex.h b/sys/dev/pci/drm/include/linux/ww_mutex.h index d2b9b3834..d5b1ac263 100644 --- a/sys/dev/pci/drm/include/linux/ww_mutex.h +++ b/sys/dev/pci/drm/include/linux/ww_mutex.h @@ -209,7 +209,7 @@ static inline int ww_mutex_lock(struct ww_mutex *lock, struct ww_acquire_ctx *ctx) { return __ww_mutex_lock(lock, ctx, false, false); } - + static inline void ww_mutex_lock_slow(struct ww_mutex *lock, struct ww_acquire_ctx *ctx) { (void)__ww_mutex_lock(lock, ctx, true, false); @@ -219,7 +219,7 @@ static inline int ww_mutex_lock_interruptible(struct ww_mutex *lock, struct ww_acquire_ctx *ctx) { return __ww_mutex_lock(lock, ctx, false, true); } - + static inline int __must_check ww_mutex_lock_slow_interruptible(struct ww_mutex *lock, struct ww_acquire_ctx *ctx) { return __ww_mutex_lock(lock, ctx, true, true); diff --git a/sys/dev/pci/drm/include/uapi/drm/radeon_drm.h b/sys/dev/pci/drm/include/uapi/drm/radeon_drm.h index 490a59cc4..e38d07eb0 100644 --- a/sys/dev/pci/drm/include/uapi/drm/radeon_drm.h +++ b/sys/dev/pci/drm/include/uapi/drm/radeon_drm.h @@ -233,7 +233,7 @@ typedef union { # define R300_WAIT_3D 0x2 /* these two defines are DOING IT WRONG - however * we have userspace which relies on using these. - * The wait interface is backwards compat new + * The wait interface is backwards compat new * code should use the NEW_WAIT defines below * THESE ARE NOT BIT FIELDS */ diff --git a/sys/dev/pci/drm/linux_sort.c b/sys/dev/pci/drm/linux_sort.c index 402295335..e7497a4c7 100644 --- a/sys/dev/pci/drm/linux_sort.c +++ b/sys/dev/pci/drm/linux_sort.c @@ -56,7 +56,7 @@ static __inline void swapfunc(char *, char *, size_t, int); static __inline void swapfunc(char *a, char *b, size_t n, int swaptype) { - if (swaptype <= 1) + if (swaptype <= 1) swapcode(long, a, b, n) else swapcode(char, a, b, n) @@ -167,7 +167,7 @@ loop: SWAPINIT(a, es); void sort(void *a, size_t n, size_t es, int (*cmp)(const void *, const void *), - void *x) + void *x) { KASSERT(x == NULL); qsort(a, n, es, cmp); diff --git a/sys/dev/pci/drm/radeon/ObjectID.h b/sys/dev/pci/drm/radeon/ObjectID.h index 06192698b..bf5b73388 100644 --- a/sys/dev/pci/drm/radeon/ObjectID.h +++ b/sys/dev/pci/drm/radeon/ObjectID.h @@ -1,5 +1,5 @@ /* -* Copyright 2006-2007 Advanced Micro Devices, Inc. +* Copyright 2006-2007 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -37,13 +37,13 @@ #define GRAPH_OBJECT_TYPE_CONNECTOR 0x3 #define GRAPH_OBJECT_TYPE_ROUTER 0x4 /* deleted */ -#define GRAPH_OBJECT_TYPE_DISPLAY_PATH 0x6 +#define GRAPH_OBJECT_TYPE_DISPLAY_PATH 0x6 #define GRAPH_OBJECT_TYPE_GENERIC 0x7 /****************************************************/ /* Encoder Object ID Definition */ /****************************************************/ -#define ENCODER_OBJECT_ID_NONE 0x00 +#define ENCODER_OBJECT_ID_NONE 0x00 /* Radeon Class Display Hardware */ #define ENCODER_OBJECT_ID_INTERNAL_LVDS 0x01 @@ -96,7 +96,7 @@ /****************************************************/ /* Connector Object ID Definition */ /****************************************************/ -#define CONNECTOR_OBJECT_ID_NONE 0x00 +#define CONNECTOR_OBJECT_ID_NONE 0x00 #define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I 0x01 #define CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I 0x02 #define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D 0x03 @@ -156,7 +156,7 @@ #define RESERVED1_ID_MASK 0x0800 #define OBJECT_TYPE_MASK 0x7000 #define RESERVED2_ID_MASK 0x8000 - + #define OBJECT_ID_SHIFT 0x00 #define ENUM_ID_SHIFT 0x08 #define OBJECT_TYPE_SHIFT 0x0C @@ -177,14 +177,14 @@ /* Encoder Object ID definition - Shared with BIOS */ /****************************************************/ /* -#define ENCODER_INTERNAL_LVDS_ENUM_ID1 0x2101 +#define ENCODER_INTERNAL_LVDS_ENUM_ID1 0x2101 #define ENCODER_INTERNAL_TMDS1_ENUM_ID1 0x2102 #define ENCODER_INTERNAL_TMDS2_ENUM_ID1 0x2103 #define ENCODER_INTERNAL_DAC1_ENUM_ID1 0x2104 #define ENCODER_INTERNAL_DAC2_ENUM_ID1 0x2105 #define ENCODER_INTERNAL_SDVOA_ENUM_ID1 0x2106 #define ENCODER_INTERNAL_SDVOB_ENUM_ID1 0x2107 -#define ENCODER_SIL170B_ENUM_ID1 0x2108 +#define ENCODER_SIL170B_ENUM_ID1 0x2108 #define ENCODER_CH7303_ENUM_ID1 0x2109 #define ENCODER_CH7301_ENUM_ID1 0x210A #define ENCODER_INTERNAL_DVO1_ENUM_ID1 0x210B @@ -198,8 +198,8 @@ #define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1 0x2113 #define ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1 0x2114 #define ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1 0x2115 -#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 0x2116 -#define ENCODER_SI178_ENUM_ID1 0x2117 +#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 0x2116 +#define ENCODER_SI178_ENUM_ID1 0x2117 #define ENCODER_MVPU_FPGA_ENUM_ID1 0x2118 #define ENCODER_INTERNAL_DDI_ENUM_ID1 0x2119 #define ENCODER_VT1625_ENUM_ID1 0x211A @@ -314,7 +314,7 @@ #define ENCODER_SI178_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - ENCODER_OBJECT_ID_SI178 << OBJECT_ID_SHIFT) + ENCODER_OBJECT_ID_SI178 << OBJECT_ID_SHIFT) #define ENCODER_MVPU_FPGA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ @@ -322,7 +322,7 @@ #define ENCODER_INTERNAL_DDI_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - ENCODER_OBJECT_ID_INTERNAL_DDI << OBJECT_ID_SHIFT) + ENCODER_OBJECT_ID_INTERNAL_DDI << OBJECT_ID_SHIFT) #define ENCODER_VT1625_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ @@ -350,7 +350,7 @@ #define ENCODER_INTERNAL_KLDSCP_LVTMA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA << OBJECT_ID_SHIFT) + ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA << OBJECT_ID_SHIFT) #define ENCODER_INTERNAL_UNIPHY1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ diff --git a/sys/dev/pci/drm/radeon/atombios.h b/sys/dev/pci/drm/radeon/atombios.h index da35a970f..85ae68ba5 100644 --- a/sys/dev/pci/drm/radeon/atombios.h +++ b/sys/dev/pci/drm/radeon/atombios.h @@ -1,5 +1,5 @@ /* - * Copyright 2006-2007 Advanced Micro Devices, Inc. + * Copyright 2006-2007 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -21,7 +21,7 @@ */ -/****************************************************************************/ +/****************************************************************************/ /*Portion I: Definitions shared between VBIOS and Driver */ /****************************************************************************/ @@ -42,7 +42,7 @@ #endif #ifdef _H2INC - #ifndef ULONG + #ifndef ULONG typedef unsigned long ULONG; #endif @@ -50,12 +50,12 @@ typedef unsigned char UCHAR; #endif - #ifndef USHORT + #ifndef USHORT typedef unsigned short USHORT; #endif #endif - -#define ATOM_DAC_A 0 + +#define ATOM_DAC_A 0 #define ATOM_DAC_B 1 #define ATOM_EXT_DAC 2 @@ -81,7 +81,7 @@ #define ATOM_EXT_CLOCK 10 #define ATOM_PPLL_INVALID 0xFF -#define ENCODER_REFCLK_SRC_P1PLL 0 +#define ENCODER_REFCLK_SRC_P1PLL 0 #define ENCODER_REFCLK_SRC_P2PLL 1 #define ENCODER_REFCLK_SRC_DCPLL 2 #define ENCODER_REFCLK_SRC_EXTCLK 3 @@ -90,10 +90,10 @@ #define ATOM_SCALER1 0 #define ATOM_SCALER2 1 -#define ATOM_SCALER_DISABLE 0 -#define ATOM_SCALER_CENTER 1 -#define ATOM_SCALER_EXPANSION 2 -#define ATOM_SCALER_MULTI_EX 3 +#define ATOM_SCALER_DISABLE 0 +#define ATOM_SCALER_CENTER 1 +#define ATOM_SCALER_EXPANSION 2 +#define ATOM_SCALER_MULTI_EX 3 #define ATOM_DISABLE 0 #define ATOM_ENABLE 1 @@ -137,7 +137,7 @@ #define ATOM_DAC2_CV ATOM_DAC1_CV #define ATOM_DAC2_NTSC ATOM_DAC1_NTSC #define ATOM_DAC2_PAL ATOM_DAC1_PAL - + #define ATOM_PM_ON 0 #define ATOM_PM_STANDBY 1 #define ATOM_PM_SUSPEND 2 @@ -173,7 +173,7 @@ #define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 3 //sizeof( ATOM_FIREGL_FLAG_STRING ) #define ATOM_FAKE_DESKTOP_STRING "DSK" //Flag used to enable mobile ASIC on Desktop -#define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING +#define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING #define ATOM_M54T_FLAG_STRING "M54T" //Flag used to enable M54T Support #define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING 4 //sizeof( ATOM_M54T_FLAG_STRING ) @@ -194,7 +194,7 @@ #define OFFSET_TO_GET_ATOMBIOS_STRINGS_START 0x006e /* Common header for all ROM Data tables. - Every table pointed _ATOM_MASTER_DATA_TABLE has this common header. + Every table pointed _ATOM_MASTER_DATA_TABLE has this common header. And the pointer actually points to this header. */ typedef struct _ATOM_COMMON_TABLE_HEADER @@ -205,13 +205,13 @@ typedef struct _ATOM_COMMON_TABLE_HEADER /*Image can't be updated, while Driver needs to carry the new table! */ }ATOM_COMMON_TABLE_HEADER; -/****************************************************************************/ +/****************************************************************************/ // Structure stores the ROM header. -/****************************************************************************/ +/****************************************************************************/ typedef struct _ATOM_ROM_HEADER { ATOM_COMMON_TABLE_HEADER sHeader; - UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios, + UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios, atombios should init it as "ATOM", don't change the position */ USHORT usBiosRuntimeSegmentAddress; USHORT usProtectedModeInfoOffset; @@ -223,7 +223,7 @@ typedef struct _ATOM_ROM_HEADER USHORT usIoBaseAddress; USHORT usSubsystemVendorID; USHORT usSubsystemID; - USHORT usPCI_InfoOffset; + USHORT usPCI_InfoOffset; USHORT usMasterCommandTableOffset; /*Offset for SW to get all command table offsets, Don't change the position */ USHORT usMasterDataTableOffset; /*Offset for SW to get all data table offsets, Don't change the position */ UCHAR ucExtendedFunctionCode; @@ -237,9 +237,9 @@ typedef struct _ATOM_ROM_HEADER #define USHORT void* #endif -/****************************************************************************/ -// Structures used in Command.mtb -/****************************************************************************/ +/****************************************************************************/ +// Structures used in Command.mtb +/****************************************************************************/ typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{ USHORT ASIC_Init; //Function Table, used by various SW components,latest version 1.1 USHORT GetDisplaySurfaceSize; //Atomic Table, Used by Bios when enabling HW ICON @@ -253,50 +253,50 @@ typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{ USHORT GPIOPinControl; //Atomic Table, only used by Bios USHORT SetEngineClock; //Function Table,directly used by various SW components,latest version 1.1 USHORT SetMemoryClock; //Function Table,directly used by various SW components,latest version 1.1 - USHORT SetPixelClock; //Function Table,directly used by various SW components,latest version 1.2 + USHORT SetPixelClock; //Function Table,directly used by various SW components,latest version 1.2 USHORT EnableDispPowerGating; //Atomic Table, indirectly used by various SW components,called from ASIC_Init USHORT ResetMemoryDLL; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock USHORT ResetMemoryDevice; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock USHORT MemoryPLLInit; //Atomic Table, used only by Bios - USHORT AdjustDisplayPll; //Atomic Table, used by various SW componentes. - USHORT AdjustMemoryController; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock + USHORT AdjustDisplayPll; //Atomic Table, used by various SW componentes. + USHORT AdjustMemoryController; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock USHORT EnableASIC_StaticPwrMgt; //Atomic Table, only used by Bios - USHORT SetUniphyInstance; //Atomic Table, only used by Bios - USHORT DAC_LoadDetection; //Atomic Table, directly used by various SW components,latest version 1.2 + USHORT SetUniphyInstance; //Atomic Table, only used by Bios + USHORT DAC_LoadDetection; //Atomic Table, directly used by various SW components,latest version 1.2 USHORT LVTMAEncoderControl; //Atomic Table,directly used by various SW components,latest version 1.3 - USHORT HW_Misc_Operation; //Atomic Table, directly used by various SW components,latest version 1.1 - USHORT DAC1EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1 - USHORT DAC2EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1 - USHORT DVOOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 - USHORT CV1OutputControl; //Atomic Table, Atomic Table, Obsolete from Ry6xx, use DAC2 Output instead + USHORT HW_Misc_Operation; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT DAC1EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT DAC2EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT DVOOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT CV1OutputControl; //Atomic Table, Atomic Table, Obsolete from Ry6xx, use DAC2 Output instead USHORT GetConditionalGoldenSetting; //Only used by Bios USHORT TVEncoderControl; //Function Table,directly used by various SW components,latest version 1.1 USHORT PatchMCSetting; //only used by BIOS USHORT MC_SEQ_Control; //only used by BIOS USHORT Gfx_Harvesting; //Atomic Table, Obsolete from Ry6xx, Now only used by BIOS for GFX harvesting USHORT EnableScaler; //Atomic Table, used only by Bios - USHORT BlankCRTC; //Atomic Table, directly used by various SW components,latest version 1.1 - USHORT EnableCRTC; //Atomic Table, directly used by various SW components,latest version 1.1 - USHORT GetPixelClock; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT BlankCRTC; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT EnableCRTC; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT GetPixelClock; //Atomic Table, directly used by various SW components,latest version 1.1 USHORT EnableVGA_Render; //Function Table,directly used by various SW components,latest version 1.1 USHORT GetSCLKOverMCLKRatio; //Atomic Table, only used by Bios USHORT SetCRTC_Timing; //Atomic Table, directly used by various SW components,latest version 1.1 - USHORT SetCRTC_OverScan; //Atomic Table, used by various SW components,latest version 1.1 + USHORT SetCRTC_OverScan; //Atomic Table, used by various SW components,latest version 1.1 USHORT SetCRTC_Replication; //Atomic Table, used only by Bios - USHORT SelectCRTC_Source; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT SelectCRTC_Source; //Atomic Table, directly used by various SW components,latest version 1.1 USHORT EnableGraphSurfaces; //Atomic Table, used only by Bios USHORT UpdateCRTC_DoubleBufferRegisters; //Atomic Table, used only by Bios USHORT LUT_AutoFill; //Atomic Table, only used by Bios USHORT EnableHW_IconCursor; //Atomic Table, only used by Bios - USHORT GetMemoryClock; //Atomic Table, directly used by various SW components,latest version 1.1 - USHORT GetEngineClock; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT GetMemoryClock; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT GetEngineClock; //Atomic Table, directly used by various SW components,latest version 1.1 USHORT SetCRTC_UsingDTDTiming; //Atomic Table, directly used by various SW components,latest version 1.1 USHORT ExternalEncoderControl; //Atomic Table, directly used by various SW components,latest version 2.1 USHORT LVTMAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 USHORT VRAM_BlockDetectionByStrap; //Atomic Table, used only by Bios - USHORT MemoryCleanUp; //Atomic Table, only used by Bios + USHORT MemoryCleanUp; //Atomic Table, only used by Bios USHORT ProcessI2cChannelTransaction; //Function Table,only used by Bios - USHORT WriteOneByteToHWAssistedI2C; //Function Table,indirectly used by various SW components + USHORT WriteOneByteToHWAssistedI2C; //Function Table,indirectly used by various SW components USHORT ReadHWAssistedI2CStatus; //Atomic Table, indirectly used by various SW components USHORT SpeedFanControl; //Function Table,indirectly used by various SW components,called from ASIC_Init USHORT PowerConnectorDetection; //Atomic Table, directly used by various SW components,latest version 1.1 @@ -318,22 +318,22 @@ typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{ USHORT DIG1EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1 USHORT DIG2EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1 USHORT DIG1TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1 - USHORT DIG2TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1 + USHORT DIG2TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1 USHORT ProcessAuxChannelTransaction; //Function Table,only used by Bios USHORT DPEncoderService; //Function Table,only used by Bios USHORT GetVoltageInfo; //Function Table,only used by Bios since SI -}ATOM_MASTER_LIST_OF_COMMAND_TABLES; +}ATOM_MASTER_LIST_OF_COMMAND_TABLES; -// For backward compatible +// For backward compatible #define ReadEDIDFromHWAssistedI2C ProcessI2cChannelTransaction #define DPTranslatorControl DIG2EncoderControl #define UNIPHYTransmitterControl DIG1TransmitterControl #define LVTMATransmitterControl DIG2TransmitterControl #define SetCRTC_DPM_State GetConditionalGoldenSetting -#define ASIC_StaticPwrMgtStatusChange SetUniphyInstance +#define ASIC_StaticPwrMgtStatusChange SetUniphyInstance #define HPDInterruptService ReadHWAssistedI2CStatus #define EnableVGA_Access GetSCLKOverMCLKRatio -#define EnableYUV GetDispObjectInfo +#define EnableYUV GetDispObjectInfo #define DynamicClockGating EnableDispPowerGating #define SetupHWAssistedI2CStatus ComputeMemoryClockParam @@ -348,18 +348,18 @@ typedef struct _ATOM_MASTER_COMMAND_TABLE ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables; }ATOM_MASTER_COMMAND_TABLE; -/****************************************************************************/ +/****************************************************************************/ // Structures used in every command table -/****************************************************************************/ +/****************************************************************************/ typedef struct _ATOM_TABLE_ATTRIBUTE { #if ATOM_BIG_ENDIAN USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag - USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), - USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), + USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), + USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), #else - USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), - USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), + USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), + USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag #endif }ATOM_TABLE_ATTRIBUTE; @@ -370,45 +370,45 @@ typedef union _ATOM_TABLE_ATTRIBUTE_ACCESS USHORT susAccess; }ATOM_TABLE_ATTRIBUTE_ACCESS; -/****************************************************************************/ +/****************************************************************************/ // Common header for all command tables. -// Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header. +// Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header. // And the pointer actually points to this header. -/****************************************************************************/ +/****************************************************************************/ typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER { ATOM_COMMON_TABLE_HEADER CommonHeader; - ATOM_TABLE_ATTRIBUTE TableAttribute; + ATOM_TABLE_ATTRIBUTE TableAttribute; }ATOM_COMMON_ROM_COMMAND_TABLE_HEADER; -/****************************************************************************/ +/****************************************************************************/ // Structures used by ComputeMemoryEnginePLLTable -/****************************************************************************/ +/****************************************************************************/ #define COMPUTE_MEMORY_PLL_PARAM 1 #define COMPUTE_ENGINE_PLL_PARAM 2 #define ADJUST_MC_SETTING_PARAM 3 -/****************************************************************************/ +/****************************************************************************/ // Structures used by AdjustMemoryControllerTable -/****************************************************************************/ +/****************************************************************************/ typedef struct _ATOM_ADJUST_MEMORY_CLOCK_FREQ { #if ATOM_BIG_ENDIAN - ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block + ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0] ULONG ulClockFreq:24; #else ULONG ulClockFreq:24; ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0] - ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block + ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block #endif }ATOM_ADJUST_MEMORY_CLOCK_FREQ; #define POINTER_RETURN_FLAG 0x80 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS { - ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div - UCHAR ucAction; //0:reserved //1:Memory //2:Engine + ULONG ulClock; //When return, it's the re-calculated clock based on given Fb_div Post_Div and ref_div + UCHAR ucAction; //0:reserved //1:Memory //2:Engine UCHAR ucReserved; //may expand to return larger Fbdiv later UCHAR ucFbDiv; //return value UCHAR ucPostDiv; //return value @@ -416,7 +416,7 @@ typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 { - ULONG ulClock; //When return, [23:0] return real clock + ULONG ulClock; //When return, [23:0] return real clock UCHAR ucAction; //0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register USHORT usFbDiv; //return Feedback value to be written to register UCHAR ucPostDiv; //return post div to be written to register @@ -428,14 +428,14 @@ typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 #define USE_NON_BUS_CLOCK_MASK 0x01000000 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) #define USE_MEMORY_SELF_REFRESH_MASK 0x02000000 //Only applicable to memory clock change, when set, using memory self refresh during clock transition #define SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04000000 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change -#define FIRST_TIME_CHANGE_CLOCK 0x08000000 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup +#define FIRST_TIME_CHANGE_CLOCK 0x08000000 //Applicable to both memory and engine clock change, when set, it means this is 1st time to change clock after ASIC bootup #define SKIP_SW_PROGRAM_PLL 0x10000000 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL #define USE_SS_ENABLED_PIXEL_CLOCK USE_NON_BUS_CLOCK_MASK #define b3USE_NON_BUS_CLOCK_MASK 0x01 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) #define b3USE_MEMORY_SELF_REFRESH 0x02 //Only applicable to memory clock change, when set, using memory self refresh during clock transition #define b3SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change -#define b3FIRST_TIME_CHANGE_CLOCK 0x08 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup +#define b3FIRST_TIME_CHANGE_CLOCK 0x08 //Applicable to both memory and engine clock change,i when set, it means this is 1st time to change clock after ASIC bootup #define b3SKIP_SW_PROGRAM_PLL 0x10 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL typedef struct _ATOM_COMPUTE_CLOCK_FREQ @@ -451,8 +451,8 @@ typedef struct _ATOM_COMPUTE_CLOCK_FREQ typedef struct _ATOM_S_MPLL_FB_DIVIDER { - USHORT usFbDivFrac; - USHORT usFbDiv; + USHORT usFbDivFrac; + USHORT usFbDiv; }ATOM_S_MPLL_FB_DIVIDER; typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 @@ -463,9 +463,9 @@ typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 ULONG ulClockParams; //ULONG access for BE ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter }; - UCHAR ucRefDiv; //Output Parameter - UCHAR ucPostDiv; //Output Parameter - UCHAR ucCntlFlag; //Output Parameter + UCHAR ucRefDiv; //Output Parameter + UCHAR ucPostDiv; //Output Parameter + UCHAR ucCntlFlag; //Output Parameter UCHAR ucReserved; }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3; @@ -481,9 +481,9 @@ typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 { #if ATOM_BIG_ENDIAN ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register directly - ULONG ulClock:24; //Input= target clock, output = actual clock + ULONG ulClock:24; //Input= target clock, output = actual clock #else - ULONG ulClock:24; //Input= target clock, output = actual clock + ULONG ulClock:24; //Input= target clock, output = actual clock ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register directly #endif }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4; @@ -496,14 +496,14 @@ typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 ULONG ulClockParams; //ULONG access for BE ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter }; - UCHAR ucRefDiv; //Output Parameter - UCHAR ucPostDiv; //Output Parameter + UCHAR ucRefDiv; //Output Parameter + UCHAR ucPostDiv; //Output Parameter union { UCHAR ucCntlFlag; //Output Flags UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0) mode }; - UCHAR ucReserved; + UCHAR ucReserved; }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5; @@ -522,14 +522,14 @@ typedef struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 { COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock; //Output Parameter: ucPostDiv=DFS divider ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter: PLL FB divider - UCHAR ucPllRefDiv; //Output Parameter: PLL ref divider - UCHAR ucPllPostDiv; //Output Parameter: PLL post divider + UCHAR ucPllRefDiv; //Output Parameter: PLL ref divider + UCHAR ucPllPostDiv; //Output Parameter: PLL post divider UCHAR ucPllCntlFlag; //Output Flags: control flag - UCHAR ucReserved; + UCHAR ucReserved; }COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6; //ucPllCntlFlag -#define SPLL_CNTL_FLAG_VCO_MODE_MASK 0x03 +#define SPLL_CNTL_FLAG_VCO_MODE_MASK 0x03 // ucInputFlag @@ -540,22 +540,22 @@ typedef struct _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 { union { - ULONG ulClock; + ULONG ulClock; ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS) }; - UCHAR ucDllSpeed; //Output + UCHAR ucDllSpeed; //Output UCHAR ucPostDiv; //Output union{ UCHAR ucInputFlag; //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode - UCHAR ucPllCntlFlag; //Output: + UCHAR ucPllCntlFlag; //Output: }; - UCHAR ucBWCntl; + UCHAR ucBWCntl; }COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1; // definition of ucInputFlag #define MPLL_INPUT_FLAG_STROBE_MODE_EN 0x01 // definition of ucPllCntlFlag -#define MPLL_CNTL_FLAG_VCO_MODE_MASK 0x03 +#define MPLL_CNTL_FLAG_VCO_MODE_MASK 0x03 #define MPLL_CNTL_FLAG_BYPASS_DQ_PLL 0x04 #define MPLL_CNTL_FLAG_QDR_ENABLE 0x08 #define MPLL_CNTL_FLAG_AD_HALF_RATE 0x10 @@ -576,9 +576,9 @@ typedef struct _DYNAMICE_ENGINE_SETTINGS_PARAMETER ULONG ulReserved; }DYNAMICE_ENGINE_SETTINGS_PARAMETER; -/****************************************************************************/ +/****************************************************************************/ // Structures used by SetEngineClockTable -/****************************************************************************/ +/****************************************************************************/ typedef struct _SET_ENGINE_CLOCK_PARAMETERS { ULONG ulTargetEngineClock; //In 10Khz unit @@ -590,9 +590,9 @@ typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; }SET_ENGINE_CLOCK_PS_ALLOCATION; -/****************************************************************************/ +/****************************************************************************/ // Structures used by SetMemoryClockTable -/****************************************************************************/ +/****************************************************************************/ typedef struct _SET_MEMORY_CLOCK_PARAMETERS { ULONG ulTargetMemoryClock; //In 10Khz unit @@ -604,9 +604,9 @@ typedef struct _SET_MEMORY_CLOCK_PS_ALLOCATION COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; }SET_MEMORY_CLOCK_PS_ALLOCATION; -/****************************************************************************/ +/****************************************************************************/ // Structures used by ASIC_Init.ctb -/****************************************************************************/ +/****************************************************************************/ typedef struct _ASIC_INIT_PARAMETERS { ULONG ulDefaultEngineClock; //In 10Khz unit @@ -619,29 +619,29 @@ typedef struct _ASIC_INIT_PS_ALLOCATION SET_ENGINE_CLOCK_PS_ALLOCATION sReserved; //Caller doesn't need to init this structure }ASIC_INIT_PS_ALLOCATION; -/****************************************************************************/ +/****************************************************************************/ // Structure used by DynamicClockGatingTable.ctb -/****************************************************************************/ -typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS +/****************************************************************************/ +typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS { UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE UCHAR ucPadding[3]; }DYNAMIC_CLOCK_GATING_PARAMETERS; #define DYNAMIC_CLOCK_GATING_PS_ALLOCATION DYNAMIC_CLOCK_GATING_PARAMETERS -/****************************************************************************/ +/****************************************************************************/ // Structure used by EnableDispPowerGatingTable.ctb -/****************************************************************************/ -typedef struct _ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 +/****************************************************************************/ +typedef struct _ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 { UCHAR ucDispPipeId; // ATOM_CRTC1, ATOM_CRTC2, ... UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE UCHAR ucPadding[2]; }ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1; -/****************************************************************************/ +/****************************************************************************/ // Structure used by EnableASIC_StaticPwrMgtTable.ctb -/****************************************************************************/ +/****************************************************************************/ typedef struct _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS { UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE @@ -649,9 +649,9 @@ typedef struct _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS }ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS; #define ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS -/****************************************************************************/ +/****************************************************************************/ // Structures used by DAC_LoadDetectionTable.ctb -/****************************************************************************/ +/****************************************************************************/ typedef struct _DAC_LOAD_DETECTION_PARAMETERS { USHORT usDeviceID; //{ATOM_DEVICE_CRTx_SUPPORT,ATOM_DEVICE_TVx_SUPPORT,ATOM_DEVICE_CVx_SUPPORT} @@ -668,10 +668,10 @@ typedef struct _DAC_LOAD_DETECTION_PS_ALLOCATION ULONG Reserved[2];// Don't set this one, allocation for EXT DAC }DAC_LOAD_DETECTION_PS_ALLOCATION; -/****************************************************************************/ +/****************************************************************************/ // Structures used by DAC1EncoderControlTable.ctb and DAC2EncoderControlTable.ctb -/****************************************************************************/ -typedef struct _DAC_ENCODER_CONTROL_PARAMETERS +/****************************************************************************/ +typedef struct _DAC_ENCODER_CONTROL_PARAMETERS { USHORT usPixelClock; // in 10KHz; for bios convenient UCHAR ucDacStandard; // See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0) @@ -682,28 +682,28 @@ typedef struct _DAC_ENCODER_CONTROL_PARAMETERS #define DAC_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PARAMETERS -/****************************************************************************/ +/****************************************************************************/ // Structures used by DIG1EncoderControlTable // DIG2EncoderControlTable // ExternalEncoderControlTable -/****************************************************************************/ +/****************************************************************************/ typedef struct _DIG_ENCODER_CONTROL_PARAMETERS { USHORT usPixelClock; // in 10KHz; for bios convenient - UCHAR ucConfig; + UCHAR ucConfig; // [2] Link Select: // =0: PHY linkA if bfLane<3 // =1: PHY linkB if bfLanes<3 // =0: PHY linkA+B if bfLanes=3 // [3] Transmitter Sel // =0: UNIPHY or PCIEPHY - // =1: LVTMA - UCHAR ucAction; // =0: turn off encoder - // =1: turn on encoder + // =1: LVTMA + UCHAR ucAction; // =0: turn off encoder + // =1: turn on encoder UCHAR ucEncoderMode; - // =0: DP encoder - // =1: LVDS encoder - // =2: DVI encoder + // =0: DP encoder + // =1: LVDS encoder + // =2: DVI encoder // =3: HDMI encoder // =4: SDVO encoder UCHAR ucLaneNum; // how many lanes to enable @@ -768,11 +768,11 @@ typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2 { USHORT usPixelClock; // in 10KHz; for bios convenient ATOM_DIG_ENCODER_CONFIG_V2 acConfig; - UCHAR ucAction; + UCHAR ucAction; UCHAR ucEncoderMode; - // =0: DP encoder - // =1: LVDS encoder - // =2: DVI encoder + // =0: DP encoder + // =1: LVDS encoder + // =2: DVI encoder // =3: HDMI encoder // =4: SDVO encoder UCHAR ucLaneNum; // how many lanes to enable @@ -843,12 +843,12 @@ typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V3 { USHORT usPixelClock; // in 10KHz; for bios convenient ATOM_DIG_ENCODER_CONFIG_V3 acConfig; - UCHAR ucAction; + UCHAR ucAction; union { UCHAR ucEncoderMode; - // =0: DP encoder - // =1: LVDS encoder - // =2: DVI encoder + // =0: DP encoder + // =1: LVDS encoder + // =2: DVI encoder // =3: HDMI encoder // =4: SDVO encoder // =5: DP audio @@ -864,7 +864,7 @@ typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V3 //ucTableFormatRevision=1 //ucTableContentRevision=4 -// start from NI +// start from NI // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver typedef struct _ATOM_DIG_ENCODER_CONFIG_V4 { @@ -902,12 +902,12 @@ typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V4 ATOM_DIG_ENCODER_CONFIG_V4 acConfig; UCHAR ucConfig; }; - UCHAR ucAction; + UCHAR ucAction; union { UCHAR ucEncoderMode; - // =0: DP encoder - // =1: LVDS encoder - // =2: DVI encoder + // =0: DP encoder + // =1: LVDS encoder + // =2: DVI encoder // =3: HDMI encoder // =4: SDVO encoder // =5: DP audio @@ -921,9 +921,9 @@ typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V4 UCHAR ucHPD_ID; // HPD ID (1-6). =0 means to skip HDP programming. New comparing to previous version }DIG_ENCODER_CONTROL_PARAMETERS_V4; -// define ucBitPerColor: +// define ucBitPerColor: #define PANEL_BPC_UNDEFINE 0x00 -#define PANEL_6BIT_PER_COLOR 0x01 +#define PANEL_6BIT_PER_COLOR 0x01 #define PANEL_8BIT_PER_COLOR 0x02 #define PANEL_10BIT_PER_COLOR 0x03 #define PANEL_12BIT_PER_COLOR 0x04 @@ -934,11 +934,11 @@ typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V4 #define DP_PANEL_MODE_INTERNAL_DP2_MODE 0x01 #define DP_PANEL_MODE_INTERNAL_DP1_MODE 0x11 -/****************************************************************************/ +/****************************************************************************/ // Structures used by UNIPHYTransmitterControlTable // LVTMATransmitterControlTable // DVOOutputControlTable -/****************************************************************************/ +/****************************************************************************/ typedef struct _ATOM_DP_VS_MODE { UCHAR ucLaneSel; @@ -954,36 +954,36 @@ typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS ATOM_DP_VS_MODE asMode; // DP Voltage swing mode }; UCHAR ucConfig; - // [0]=0: 4 lane Link, - // =1: 8 lane Link ( Dual Links TMDS ) - // [1]=0: InCoherent mode - // =1: Coherent Mode + // [0]=0: 4 lane Link, + // =1: 8 lane Link ( Dual Links TMDS ) + // [1]=0: InCoherent mode + // =1: Coherent Mode // [2] Link Select: // =0: PHY linkA if bfLane<3 // =1: PHY linkB if bfLanes<3 - // =0: PHY linkA+B if bfLanes=3 + // =0: PHY linkA+B if bfLanes=3 // [5:4]PCIE lane Sel // =0: lane 0~3 or 0~7 // =1: lane 4~7 // =2: lane 8~11 or 8~15 - // =3: lane 12~15 - UCHAR ucAction; // =0: turn off encoder - // =1: turn on encoder + // =3: lane 12~15 + UCHAR ucAction; // =0: turn off encoder + // =1: turn on encoder UCHAR ucReserved[4]; }DIG_TRANSMITTER_CONTROL_PARAMETERS; -#define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PARAMETERS +#define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PARAMETERS //ucInitInfo -#define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK 0x00ff +#define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK 0x00ff -//ucConfig +//ucConfig #define ATOM_TRANSMITTER_CONFIG_8LANE_LINK 0x01 #define ATOM_TRANSMITTER_CONFIG_COHERENT 0x02 #define ATOM_TRANSMITTER_CONFIG_LINK_SEL_MASK 0x04 #define ATOM_TRANSMITTER_CONFIG_LINKA 0x00 #define ATOM_TRANSMITTER_CONFIG_LINKB 0x04 -#define ATOM_TRANSMITTER_CONFIG_LINKA_B 0x00 +#define ATOM_TRANSMITTER_CONFIG_LINKA_B 0x00 #define ATOM_TRANSMITTER_CONFIG_LINKB_A 0x04 #define ATOM_TRANSMITTER_CONFIG_ENCODER_SEL_MASK 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE @@ -1025,7 +1025,7 @@ typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V2 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) // =1 Dig Transmitter 2 ( Uniphy CD ) // =2 Dig Transmitter 3 ( Uniphy EF ) - UCHAR ucReserved:1; + UCHAR ucReserved:1; UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E @@ -1040,14 +1040,14 @@ typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V2 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector - UCHAR ucReserved:1; + UCHAR ucReserved:1; UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) // =1 Dig Transmitter 2 ( Uniphy CD ) // =2 Dig Transmitter 3 ( Uniphy EF ) #endif }ATOM_DIG_TRANSMITTER_CONFIG_V2; -//ucConfig +//ucConfig //Bit0 #define ATOM_TRANSMITTER_CONFIG_V2_DUAL_LINK_CONNECTOR 0x01 @@ -1126,7 +1126,7 @@ typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 UCHAR ucReserved[3]; }DIG_TRANSMITTER_CONTROL_PARAMETERS_V3; -//ucConfig +//ucConfig //Bit0 #define ATOM_TRANSMITTER_CONFIG_V3_DUAL_LINK_CONNECTOR 0x01 @@ -1156,17 +1156,17 @@ typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER3 0x80 //EF -/****************************************************************************/ +/****************************************************************************/ // Structures used by UNIPHYTransmitterControlTable V1.4 // ASIC Families: NI // ucTableFormatRevision=1 // ucTableContentRevision=4 -/****************************************************************************/ +/****************************************************************************/ typedef struct _ATOM_DP_VS_MODE_V4 { UCHAR ucLaneSel; union - { + { UCHAR ucLaneSet; struct { #if ATOM_BIG_ENDIAN @@ -1179,9 +1179,9 @@ typedef struct _ATOM_DP_VS_MODE_V4 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4 #endif }; - }; + }; }ATOM_DP_VS_MODE_V4; - + typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V4 { #if ATOM_BIG_ENDIAN @@ -1220,24 +1220,24 @@ typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 ATOM_DIG_TRANSMITTER_CONFIG_V4 acConfig; UCHAR ucConfig; }; - UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX + UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX UCHAR ucLaneNum; UCHAR ucReserved[3]; }DIG_TRANSMITTER_CONTROL_PARAMETERS_V4; -//ucConfig +//ucConfig //Bit0 #define ATOM_TRANSMITTER_CONFIG_V4_DUAL_LINK_CONNECTOR 0x01 //Bit1 #define ATOM_TRANSMITTER_CONFIG_V4_COHERENT 0x02 //Bit2 #define ATOM_TRANSMITTER_CONFIG_V4_LINK_SEL_MASK 0x04 -#define ATOM_TRANSMITTER_CONFIG_V4_LINKA 0x00 +#define ATOM_TRANSMITTER_CONFIG_V4_LINKA 0x00 #define ATOM_TRANSMITTER_CONFIG_V4_LINKB 0x04 // Bit3 #define ATOM_TRANSMITTER_CONFIG_V4_ENCODER_SEL_MASK 0x08 -#define ATOM_TRANSMITTER_CONFIG_V4_DIG1_ENCODER 0x00 -#define ATOM_TRANSMITTER_CONFIG_V4_DIG2_ENCODER 0x08 +#define ATOM_TRANSMITTER_CONFIG_V4_DIG1_ENCODER 0x00 +#define ATOM_TRANSMITTER_CONFIG_V4_DIG2_ENCODER 0x08 // Bit5:4 #define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SEL_MASK 0x30 #define ATOM_TRANSMITTER_CONFIG_V4_P1PLL 0x00 @@ -1256,13 +1256,13 @@ typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V5 #if ATOM_BIG_ENDIAN UCHAR ucReservd1:1; UCHAR ucHPDSel:3; - UCHAR ucPhyClkSrcId:2; - UCHAR ucCoherentMode:1; + UCHAR ucPhyClkSrcId:2; + UCHAR ucCoherentMode:1; UCHAR ucReserved:1; #else UCHAR ucReserved:1; - UCHAR ucCoherentMode:1; - UCHAR ucPhyClkSrcId:2; + UCHAR ucCoherentMode:1; + UCHAR ucPhyClkSrcId:2; UCHAR ucHPDSel:3; UCHAR ucReservd1:1; #endif @@ -1280,14 +1280,14 @@ typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig; UCHAR ucConfig; }; - UCHAR ucDigEncoderSel; // indicate DIG front end encoder + UCHAR ucDigEncoderSel; // indicate DIG front end encoder UCHAR ucDPLaneSet; UCHAR ucReserved; UCHAR ucReserved1; }DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5; //ucPhyId -#define ATOM_PHY_ID_UNIPHYA 0 +#define ATOM_PHY_ID_UNIPHYA 0 #define ATOM_PHY_ID_UNIPHYB 1 #define ATOM_PHY_ID_UNIPHYC 2 #define ATOM_PHY_ID_UNIPHYD 3 @@ -1317,12 +1317,12 @@ typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 #define DP_LANE_SET__0DB_0_6V 0x01 #define DP_LANE_SET__0DB_0_8V 0x02 #define DP_LANE_SET__0DB_1_2V 0x03 -#define DP_LANE_SET__3_5DB_0_4V 0x08 +#define DP_LANE_SET__3_5DB_0_4V 0x08 #define DP_LANE_SET__3_5DB_0_6V 0x09 #define DP_LANE_SET__3_5DB_0_8V 0x0a #define DP_LANE_SET__6DB_0_4V 0x10 #define DP_LANE_SET__6DB_0_6V 0x11 -#define DP_LANE_SET__9_5DB_0_4V 0x18 +#define DP_LANE_SET__9_5DB_0_4V 0x18 // ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig; // Bit1 @@ -1334,7 +1334,7 @@ typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 #define ATOM_TRANSMITTER_CONFIG_V5_P1PLL 0x00 #define ATOM_TRANSMITTER_CONFIG_V5_P2PLL 0x04 -#define ATOM_TRANSMITTER_CONFIG_V5_P0PLL 0x08 +#define ATOM_TRANSMITTER_CONFIG_V5_P0PLL 0x08 #define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT 0x0c // Bit6:4 #define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_MASK 0x70 @@ -1351,25 +1351,25 @@ typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 #define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION_V1_5 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 -/****************************************************************************/ +/****************************************************************************/ // Structures used by ExternalEncoderControlTable V1.3 // ASIC Families: Evergreen, Llano, NI // ucTableFormatRevision=1 // ucTableContentRevision=3 -/****************************************************************************/ +/****************************************************************************/ typedef struct _EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 { union{ - USHORT usPixelClock; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT + USHORT usPixelClock; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT USHORT usConnectorId; // connector id, valid when ucAction = INIT }; - UCHAR ucConfig; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT - UCHAR ucAction; // + UCHAR ucConfig; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT + UCHAR ucAction; // UCHAR ucEncoderMode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT - UCHAR ucLaneNum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT + UCHAR ucLaneNum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT UCHAR ucBitPerColor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP - UCHAR ucReserved; + UCHAR ucReserved; }EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3; // ucAction @@ -1399,29 +1399,29 @@ typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 }EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3; -/****************************************************************************/ +/****************************************************************************/ // Structures used by DAC1OuputControlTable // DAC2OuputControlTable // LVTMAOutputControlTable (Before DEC30) // TMDSAOutputControlTable (Before DEC30) -/****************************************************************************/ +/****************************************************************************/ typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS { UCHAR ucAction; // Possible input:ATOM_ENABLE||ATOMDISABLE // When the display is LCD, in addition to above: // ATOM_LCD_BLOFF|| ATOM_LCD_BLON ||ATOM_LCD_BL_BRIGHTNESS_CONTROL||ATOM_LCD_SELFTEST_START|| // ATOM_LCD_SELFTEST_STOP - + UCHAR aucPadding[3]; // padding to DWORD aligned }DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS; #define DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS -#define CRT1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS +#define CRT1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS #define CRT1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION -#define CRT2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS +#define CRT2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS #define CRT2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION #define CV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS @@ -1443,9 +1443,9 @@ typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS #define DVO_OUTPUT_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PS_ALLOCATION #define DVO_OUTPUT_CONTROL_PARAMETERS_V3 DIG_TRANSMITTER_CONTROL_PARAMETERS -/****************************************************************************/ +/****************************************************************************/ // Structures used by BlankCRTCTable -/****************************************************************************/ +/****************************************************************************/ typedef struct _BLANK_CRTC_PARAMETERS { UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 @@ -1456,22 +1456,22 @@ typedef struct _BLANK_CRTC_PARAMETERS }BLANK_CRTC_PARAMETERS; #define BLANK_CRTC_PS_ALLOCATION BLANK_CRTC_PARAMETERS -/****************************************************************************/ +/****************************************************************************/ // Structures used by EnableCRTCTable // EnableCRTCMemReqTable // UpdateCRTC_DoubleBufferRegistersTable -/****************************************************************************/ +/****************************************************************************/ typedef struct _ENABLE_CRTC_PARAMETERS { UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 - UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE + UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE UCHAR ucPadding[2]; }ENABLE_CRTC_PARAMETERS; #define ENABLE_CRTC_PS_ALLOCATION ENABLE_CRTC_PARAMETERS -/****************************************************************************/ +/****************************************************************************/ // Structures used by SetCRTC_OverScanTable -/****************************************************************************/ +/****************************************************************************/ typedef struct _SET_CRTC_OVERSCAN_PARAMETERS { USHORT usOverscanRight; // right @@ -1483,9 +1483,9 @@ typedef struct _SET_CRTC_OVERSCAN_PARAMETERS }SET_CRTC_OVERSCAN_PARAMETERS; #define SET_CRTC_OVERSCAN_PS_ALLOCATION SET_CRTC_OVERSCAN_PARAMETERS -/****************************************************************************/ +/****************************************************************************/ // Structures used by SetCRTC_ReplicationTable -/****************************************************************************/ +/****************************************************************************/ typedef struct _SET_CRTC_REPLICATION_PARAMETERS { UCHAR ucH_Replication; // horizontal replication @@ -1495,9 +1495,9 @@ typedef struct _SET_CRTC_REPLICATION_PARAMETERS }SET_CRTC_REPLICATION_PARAMETERS; #define SET_CRTC_REPLICATION_PS_ALLOCATION SET_CRTC_REPLICATION_PARAMETERS -/****************************************************************************/ +/****************************************************************************/ // Structures used by SelectCRTC_SourceTable -/****************************************************************************/ +/****************************************************************************/ typedef struct _SELECT_CRTC_SOURCE_PARAMETERS { UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 @@ -1515,7 +1515,7 @@ typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V2 }SELECT_CRTC_SOURCE_PARAMETERS_V2; //ucEncoderID -//#define ASIC_INT_DAC1_ENCODER_ID 0x00 +//#define ASIC_INT_DAC1_ENCODER_ID 0x00 //#define ASIC_INT_TV_ENCODER_ID 0x02 //#define ASIC_INT_DIG1_ENCODER_ID 0x03 //#define ASIC_INT_DAC2_ENCODER_ID 0x04 @@ -1534,10 +1534,10 @@ typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V2 //#define ATOM_ENCODER_MODE_CV 14 //#define ATOM_ENCODER_MODE_CRT 15 -/****************************************************************************/ +/****************************************************************************/ // Structures used by SetPixelClockTable -// GetPixelClockTable -/****************************************************************************/ +// GetPixelClockTable +/****************************************************************************/ //Major revision=1., Minor revision=1 typedef struct _PIXEL_CLOCK_PARAMETERS { @@ -1545,7 +1545,7 @@ typedef struct _PIXEL_CLOCK_PARAMETERS // 0 means disable PPLL USHORT usRefDiv; // Reference divider USHORT usFbDiv; // feedback divider - UCHAR ucPostDiv; // post divider + UCHAR ucPostDiv; // post divider UCHAR ucFracFbDiv; // fractional feedback divider UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER @@ -1565,7 +1565,7 @@ typedef struct _PIXEL_CLOCK_PARAMETERS_V2 // 0 means disable PPLL USHORT usRefDiv; // Reference divider USHORT usFbDiv; // feedback divider - UCHAR ucPostDiv; // post divider + UCHAR ucPostDiv; // post divider UCHAR ucFracFbDiv; // fractional feedback divider UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER @@ -1612,7 +1612,7 @@ typedef struct _PIXEL_CLOCK_PARAMETERS_V3 // 0 means disable PPLL. For VGA PPLL,make sure this value is not 0. USHORT usRefDiv; // Reference divider USHORT usFbDiv; // feedback divider - UCHAR ucPostDiv; // post divider + UCHAR ucPostDiv; // post divider UCHAR ucFracFbDiv; // fractional feedback divider UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 UCHAR ucTransmitterId; // graphic encoder id defined in objectId.h @@ -1631,25 +1631,25 @@ typedef struct _PIXEL_CLOCK_PARAMETERS_V3 typedef struct _PIXEL_CLOCK_PARAMETERS_V5 { - UCHAR ucCRTC; // ATOM_CRTC1~6, indicate the CRTC controller to + UCHAR ucCRTC; // ATOM_CRTC1~6, indicate the CRTC controller to // drive the pixel clock. not used for DCPLL case. union{ UCHAR ucReserved; UCHAR ucFracFbDiv; // [gphan] temporary to prevent build problem. remove it after driver code is changed. }; USHORT usPixelClock; // target the pixel clock to drive the CRTC timing - // 0 means disable PPLL/DCPLL. - USHORT usFbDiv; // feedback divider integer part. - UCHAR ucPostDiv; // post divider. + // 0 means disable PPLL/DCPLL. + USHORT usFbDiv; // feedback divider integer part. + UCHAR ucPostDiv; // post divider. UCHAR ucRefDiv; // Reference divider UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL - UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h, - // indicate which graphic encoder will be used. - UCHAR ucEncoderMode; // Encoder mode: - UCHAR ucMiscInfo; // bit[0]= Force program PPLL - // bit[1]= when VGA timing is used. + UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h, + // indicate which graphic encoder will be used. + UCHAR ucEncoderMode; // Encoder mode: + UCHAR ucMiscInfo; // bit[0]= Force program PPLL + // bit[1]= when VGA timing is used. // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp - // bit[4]= RefClock source for PPLL. + // bit[4]= RefClock source for PPLL. // =0: XTLAIN( default mode ) // =1: other external clock source, which is pre-defined // by VBIOS depend on the feature required. @@ -1669,14 +1669,14 @@ typedef struct _PIXEL_CLOCK_PARAMETERS_V5 typedef struct _CRTC_PIXEL_CLOCK_FREQ { #if ATOM_BIG_ENDIAN - ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to + ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to // drive the pixel clock. not used for DCPLL case. - ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing. + ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing. // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version. #else - ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing. + ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing. // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version. - ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to + ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to // drive the pixel clock. not used for DCPLL case. #endif }CRTC_PIXEL_CLOCK_FREQ; @@ -1684,22 +1684,22 @@ typedef struct _CRTC_PIXEL_CLOCK_FREQ typedef struct _PIXEL_CLOCK_PARAMETERS_V6 { union{ - CRTC_PIXEL_CLOCK_FREQ ulCrtcPclkFreq; // pixel clock and CRTC id frequency + CRTC_PIXEL_CLOCK_FREQ ulCrtcPclkFreq; // pixel clock and CRTC id frequency ULONG ulDispEngClkFreq; // dispclk frequency }; - USHORT usFbDiv; // feedback divider integer part. - UCHAR ucPostDiv; // post divider. + USHORT usFbDiv; // feedback divider integer part. + UCHAR ucPostDiv; // post divider. UCHAR ucRefDiv; // Reference divider UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL - UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h, - // indicate which graphic encoder will be used. - UCHAR ucEncoderMode; // Encoder mode: - UCHAR ucMiscInfo; // bit[0]= Force program PPLL - // bit[1]= when VGA timing is used. + UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h, + // indicate which graphic encoder will be used. + UCHAR ucEncoderMode; // Encoder mode: + UCHAR ucMiscInfo; // bit[0]= Force program PPLL + // bit[1]= when VGA timing is used. // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp - // bit[4]= RefClock source for PPLL. + // bit[4]= RefClock source for PPLL. // =0: XTLAIN( default mode ) - // =1: other external clock source, which is pre-defined + // =1: other external clock source, which is pre-defined // by VBIOS depend on the feature required. // bit[7:5]: reserved. ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 ) @@ -1711,9 +1711,9 @@ typedef struct _PIXEL_CLOCK_PARAMETERS_V6 #define PIXEL_CLOCK_V6_MISC_HDMI_BPP_MASK 0x0c #define PIXEL_CLOCK_V6_MISC_HDMI_24BPP 0x00 #define PIXEL_CLOCK_V6_MISC_HDMI_36BPP 0x04 -#define PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6 0x08 //for V6, the correct defintion for 36bpp should be 2 for 36bpp(2:1) +#define PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6 0x08 //for V6, the correct definition for 36bpp should be 2 for 36bpp(2:1) #define PIXEL_CLOCK_V6_MISC_HDMI_30BPP 0x08 -#define PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6 0x04 //for V6, the correct defintion for 30bpp should be 1 for 36bpp(5:4) +#define PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6 0x04 //for V6, the correct definition for 30bpp should be 1 for 36bpp(5:4) #define PIXEL_CLOCK_V6_MISC_HDMI_48BPP 0x0c #define PIXEL_CLOCK_V6_MISC_REF_DIV_SRC 0x10 #define PIXEL_CLOCK_V6_MISC_GEN_DPREFCLK 0x40 @@ -1735,9 +1735,9 @@ typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3 PIXEL_CLOCK_PARAMETERS_V5 sDispClkInput; }GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3; -/****************************************************************************/ +/****************************************************************************/ // Structures used by AdjustDisplayPllTable -/****************************************************************************/ +/****************************************************************************/ typedef struct _ADJUST_DISPLAY_PLL_PARAMETERS { USHORT usPixelClock; @@ -1782,21 +1782,21 @@ typedef struct _ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 ULONG ulDispPllFreq; // return display PPLL freq which is used to generate the pixclock, and related idclk, symclk etc UCHAR ucRefDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider and post_div ( if it is not given ) UCHAR ucPostDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider - UCHAR ucReserved[2]; + UCHAR ucReserved[2]; }ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3; typedef struct _ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 { - union + union { ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 sInput; ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 sOutput; }; } ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3; -/****************************************************************************/ +/****************************************************************************/ // Structures used by EnableYUVTable -/****************************************************************************/ +/****************************************************************************/ typedef struct _ENABLE_YUV_PARAMETERS { UCHAR ucEnable; // ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB) @@ -1805,27 +1805,27 @@ typedef struct _ENABLE_YUV_PARAMETERS }ENABLE_YUV_PARAMETERS; #define ENABLE_YUV_PS_ALLOCATION ENABLE_YUV_PARAMETERS -/****************************************************************************/ +/****************************************************************************/ // Structures used by GetMemoryClockTable -/****************************************************************************/ +/****************************************************************************/ typedef struct _GET_MEMORY_CLOCK_PARAMETERS { ULONG ulReturnMemoryClock; // current memory speed in 10KHz unit } GET_MEMORY_CLOCK_PARAMETERS; #define GET_MEMORY_CLOCK_PS_ALLOCATION GET_MEMORY_CLOCK_PARAMETERS -/****************************************************************************/ +/****************************************************************************/ // Structures used by GetEngineClockTable -/****************************************************************************/ +/****************************************************************************/ typedef struct _GET_ENGINE_CLOCK_PARAMETERS { ULONG ulReturnEngineClock; // current engine speed in 10KHz unit } GET_ENGINE_CLOCK_PARAMETERS; #define GET_ENGINE_CLOCK_PS_ALLOCATION GET_ENGINE_CLOCK_PARAMETERS -/****************************************************************************/ +/****************************************************************************/ // Following Structures and constant may be obsolete -/****************************************************************************/ +/****************************************************************************/ //Maxium 8 bytes,the data read in will be placed in the parameter space. //Read operaion successeful when the paramter space is non-zero, otherwise read operation failed typedef struct _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS @@ -1850,7 +1850,7 @@ typedef struct _WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS { USHORT usPrescale; //Ratio between Engine clock and I2C clock USHORT usByteOffset; //Write to which byte - //Upper portion of usByteOffset is Format of data + //Upper portion of usByteOffset is Format of data //1bytePS+offsetPS //2bytesPS+offsetPS //blockID+offsetPS @@ -1876,18 +1876,18 @@ typedef struct _SET_UP_HW_I2C_DATA_PARAMETERS #define SPEED_FAN_CONTROL_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS -/****************************************************************************/ +/****************************************************************************/ // Structures used by PowerConnectorDetectionTable -/****************************************************************************/ +/****************************************************************************/ typedef struct _POWER_CONNECTOR_DETECTION_PARAMETERS { UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected - UCHAR ucPwrBehaviorId; + UCHAR ucPwrBehaviorId; USHORT usPwrBudget; //how much power currently boot to in unit of watt }POWER_CONNECTOR_DETECTION_PARAMETERS; typedef struct POWER_CONNECTOR_DETECTION_PS_ALLOCATION -{ +{ UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected UCHAR ucReserved; USHORT usPwrBudget; //how much power currently boot to in unit of watt @@ -1896,12 +1896,12 @@ typedef struct POWER_CONNECTOR_DETECTION_PS_ALLOCATION /****************************LVDS SS Command Table Definitions**********************/ -/****************************************************************************/ +/****************************************************************************/ // Structures used by EnableSpreadSpectrumOnPPLLTable -/****************************************************************************/ +/****************************************************************************/ typedef struct _ENABLE_LVDS_SS_PARAMETERS { - USHORT usSpreadSpectrumPercentage; + USHORT usSpreadSpectrumPercentage; UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD UCHAR ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE @@ -1911,7 +1911,7 @@ typedef struct _ENABLE_LVDS_SS_PARAMETERS //ucTableFormatRevision=1,ucTableContentRevision=2 typedef struct _ENABLE_LVDS_SS_PARAMETERS_V2 { - USHORT usSpreadSpectrumPercentage; + USHORT usSpreadSpectrumPercentage; UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD UCHAR ucSpreadSpectrumStep; // UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE @@ -1935,12 +1935,12 @@ typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 { USHORT usSpreadSpectrumPercentage; - UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread. - // Bit[1]: 1-Ext. 0-Int. + UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread. + // Bit[1]: 1-Ext. 0-Int. // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL // Bits[7:4] reserved UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE - USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8] + USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8] USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC }ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2; @@ -1960,15 +1960,15 @@ typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 { USHORT usSpreadSpectrumAmountFrac; // SS_AMOUNT_DSFRAC New in DCE5.0 - UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread. - // Bit[1]: 1-Ext. 0-Int. + UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread. + // Bit[1]: 1-Ext. 0-Int. // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL // Bits[7:4] reserved UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE - USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8] + USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8] USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC }ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3; - + #define ATOM_PPLL_SS_TYPE_V3_DOWN_SPREAD 0x00 #define ATOM_PPLL_SS_TYPE_V3_CENTRE_SPREAD 0x01 #define ATOM_PPLL_SS_TYPE_V3_EXT_SPREAD 0x02 @@ -1989,14 +1989,14 @@ typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 typedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION { PIXEL_CLOCK_PARAMETERS sPCLKInput; - ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved;//Caller doesn't need to init this portion + ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved;//Caller doesn't need to init this portion }SET_PIXEL_CLOCK_PS_ALLOCATION; #define ENABLE_VGA_RENDER_PS_ALLOCATION SET_PIXEL_CLOCK_PS_ALLOCATION -/****************************************************************************/ +/****************************************************************************/ // Structures used by ### -/****************************************************************************/ +/****************************************************************************/ typedef struct _MEMORY_TRAINING_PARAMETERS { ULONG ulTargetMemoryClock; //In 10Khz unit @@ -2007,11 +2007,11 @@ typedef struct _MEMORY_TRAINING_PARAMETERS /****************************LVDS and other encoder command table definitions **********************/ -/****************************************************************************/ +/****************************************************************************/ // Structures used by LVDSEncoderControlTable (Before DCE30) // LVTMAEncoderControlTable (Before DCE30) // TMDSAEncoderControlTable (Before DCE30) -/****************************************************************************/ +/****************************************************************************/ typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS { USHORT usPixelClock; // in 10KHz; for bios convenient @@ -2024,7 +2024,7 @@ typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS }LVDS_ENCODER_CONTROL_PARAMETERS; #define LVDS_ENCODER_CONTROL_PS_ALLOCATION LVDS_ENCODER_CONTROL_PARAMETERS - + #define TMDS1_ENCODER_CONTROL_PARAMETERS LVDS_ENCODER_CONTROL_PARAMETERS #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION TMDS1_ENCODER_CONTROL_PARAMETERS @@ -2064,10 +2064,10 @@ typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2 }LVDS_ENCODER_CONTROL_PARAMETERS_V2; #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 - + #define TMDS1_ENCODER_CONTROL_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2 - + #define TMDS2_ENCODER_CONTROL_PARAMETERS_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS2_ENCODER_CONTROL_PARAMETERS_V2 @@ -2080,18 +2080,18 @@ typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2 #define TMDS2_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS2_ENCODER_CONTROL_PARAMETERS_V3 -/****************************************************************************/ +/****************************************************************************/ // Structures used by ### -/****************************************************************************/ +/****************************************************************************/ typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS -{ +{ UCHAR ucEnable; // Enable or Disable External TMDS encoder UCHAR ucMisc; // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB} UCHAR ucPadding[2]; }ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS; typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION -{ +{ ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS sXTmdsEncoder; WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion }ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION; @@ -2099,7 +2099,7 @@ typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION #define ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2 -{ +{ ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 sXTmdsEncoder; WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion }ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2; @@ -2110,9 +2110,9 @@ typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; }EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION; -/****************************************************************************/ +/****************************************************************************/ // Structures used by DVOEncoderControlTable -/****************************************************************************/ +/****************************************************************************/ //ucTableFormatRevision=1,ucTableContentRevision=3 //ucDVOConfig: @@ -2126,7 +2126,7 @@ typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3 { - USHORT usPixelClock; + USHORT usPixelClock; UCHAR ucDVOConfig; UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT UCHAR ucReseved[4]; @@ -2135,7 +2135,7 @@ typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3 typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V1_4 { - USHORT usPixelClock; + USHORT usPixelClock; UCHAR ucDVOConfig; UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT UCHAR ucBitPerColor; //please refer to definition of PANEL_xBIT_PER_COLOR @@ -2145,7 +2145,7 @@ typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V1_4 //ucTableFormatRevision=1 -//ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for +//ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for // bit1=0: non-coherent mode // =1: coherent mode @@ -2192,9 +2192,9 @@ typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V1_4 #define PANEL_ENCODER_75FRC_E 0x00 #define PANEL_ENCODER_75FRC_F 0x80 -/****************************************************************************/ +/****************************************************************************/ // Structures used by SetVoltageTable -/****************************************************************************/ +/****************************************************************************/ #define SET_VOLTAGE_TYPE_ASIC_VDDC 1 #define SET_VOLTAGE_TYPE_ASIC_MVDDC 2 #define SET_VOLTAGE_TYPE_ASIC_MVDDQ 3 @@ -2215,13 +2215,13 @@ typedef struct _SET_VOLTAGE_PARAMETERS UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ UCHAR ucVoltageMode; // To set all, to set source A or source B or ... UCHAR ucVoltageIndex; // An index to tell which voltage level - UCHAR ucReserved; + UCHAR ucReserved; }SET_VOLTAGE_PARAMETERS; typedef struct _SET_VOLTAGE_PARAMETERS_V2 { UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ - UCHAR ucVoltageMode; // Not used, maybe use for state machine for differen power mode + UCHAR ucVoltageMode; // Not used, maybe use for state machine for different power mode USHORT usVoltageLevel; // real voltage level }SET_VOLTAGE_PARAMETERS_V2; @@ -2245,9 +2245,9 @@ typedef struct _SET_VOLTAGE_PARAMETERS_V1_3 #define ATOM_SET_VOLTAGE_PHASE 4 //Set Vregulator Phase, only for SVID/PVID regulator #define ATOM_GET_MAX_VOLTAGE 6 //Get Max Voltage, not used from SetVoltageTable v1.3 #define ATOM_GET_VOLTAGE_LEVEL 6 //Get Voltage level from vitual voltage ID, not used for SetVoltage v1.4 -#define ATOM_GET_LEAKAGE_ID 8 //Get Leakage Voltage Id ( starting from SMU7x IP ), SetVoltage v1.4 +#define ATOM_GET_LEAKAGE_ID 8 //Get Leakage Voltage Id ( starting from SMU7x IP ), SetVoltage v1.4 -// define vitual voltage id in usVoltageLevel +// define virtual voltage id in usVoltageLevel #define ATOM_VIRTUAL_VOLTAGE_ID0 0xff01 #define ATOM_VIRTUAL_VOLTAGE_ID1 0xff02 #define ATOM_VIRTUAL_VOLTAGE_ID2 0xff03 @@ -2268,7 +2268,7 @@ typedef struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1 { UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info - USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id + USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id ULONG ulReserved; }GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1; @@ -2307,14 +2307,14 @@ typedef struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 { UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info - USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id + USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id ULONG ulSCLKFreq; // Input: when ucVoltageMode= ATOM_GET_VOLTAGE_EVV_VOLTAGE, DPM state SCLK frequency, Define in PPTable SCLK/Voltage dependence table }GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2; // New in GetVoltageInfo v1.2 ucVoltageMode -#define ATOM_GET_VOLTAGE_EVV_VOLTAGE 0x09 +#define ATOM_GET_VOLTAGE_EVV_VOLTAGE 0x09 -// New Added from CI Hawaii for EVV feature +// New Added from CI Hawaii for EVV feature typedef struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 { USHORT usVoltageLevel; // real voltage level in unit of mv @@ -2322,9 +2322,9 @@ typedef struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 ULONG ulReseved; }GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2; -/****************************************************************************/ +/****************************************************************************/ // Structures used by TVEncoderControlTable -/****************************************************************************/ +/****************************************************************************/ typedef struct _TV_ENCODER_CONTROL_PARAMETERS { USHORT usPixelClock; // in 10KHz; for bios convenient @@ -2335,28 +2335,28 @@ typedef struct _TV_ENCODER_CONTROL_PARAMETERS typedef struct _TV_ENCODER_CONTROL_PS_ALLOCATION { - TV_ENCODER_CONTROL_PARAMETERS sTVEncoder; + TV_ENCODER_CONTROL_PARAMETERS sTVEncoder; WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; // Don't set this one }TV_ENCODER_CONTROL_PS_ALLOCATION; //==============================Data Table Portion==================================== -/****************************************************************************/ +/****************************************************************************/ // Structure used in Data.mtb -/****************************************************************************/ +/****************************************************************************/ typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES { - USHORT UtilityPipeLine; // Offest for the utility to get parser info,Don't change this position! - USHORT MultimediaCapabilityInfo; // Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios + USHORT UtilityPipeLine; // Offest for the utility to get parser info, Don't change this position! + USHORT MultimediaCapabilityInfo; // Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios USHORT MultimediaConfigInfo; // Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios USHORT StandardVESA_Timing; // Only used by Bios USHORT FirmwareInfo; // Shared by various SW components,latest version 1.4 USHORT PaletteData; // Only used by BIOS - USHORT LCD_Info; // Shared by various SW components,latest version 1.3, was called LVDS_Info + USHORT LCD_Info; // Shared by various SW components,latest version 1.3, was called LVDS_Info USHORT DIGTransmitterInfo; // Internal used by VBIOS only version 3.1 - USHORT AnalogTV_Info; // Shared by various SW components,latest version 1.1 + USHORT AnalogTV_Info; // Shared by various SW components,latest version 1.1 USHORT SupportedDevicesInfo; // Will be obsolete from R600 - USHORT GPIO_I2C_Info; // Shared by various SW components,latest version 1.2 will be used from R600 + USHORT GPIO_I2C_Info; // Shared by various SW components,latest version 1.2 will be used from R600 USHORT VRAM_UsageByFirmware; // Shared by various SW components,latest version 1.3 will be used from R600 USHORT GPIO_Pin_LUT; // Shared by various SW components,latest version 1.1 USHORT VESA_ToInternalModeLUT; // Only used by Bios @@ -2383,22 +2383,22 @@ typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES }ATOM_MASTER_LIST_OF_DATA_TABLES; typedef struct _ATOM_MASTER_DATA_TABLE -{ - ATOM_COMMON_TABLE_HEADER sHeader; +{ + ATOM_COMMON_TABLE_HEADER sHeader; ATOM_MASTER_LIST_OF_DATA_TABLES ListOfDataTables; }ATOM_MASTER_DATA_TABLE; -// For backward compatible +// For backward compatible #define LVDS_Info LCD_Info #define DAC_Info PaletteData #define TMDS_Info DIGTransmitterInfo -/****************************************************************************/ +/****************************************************************************/ // Structure used in MultimediaCapabilityInfoTable -/****************************************************************************/ +/****************************************************************************/ typedef struct _ATOM_MULTIMEDIA_CAPABILITY_INFO { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; ULONG ulSignature; // HW info table signature string "$ATI" UCHAR ucI2C_Type; // I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2C pin, etc) UCHAR ucTV_OutInfo; // Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7) @@ -2406,9 +2406,9 @@ typedef struct _ATOM_MULTIMEDIA_CAPABILITY_INFO UCHAR ucHostPortInfo; // Provides host port configuration information }ATOM_MULTIMEDIA_CAPABILITY_INFO; -/****************************************************************************/ +/****************************************************************************/ // Structure used in MultimediaConfigInfoTable -/****************************************************************************/ +/****************************************************************************/ typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO { ATOM_COMMON_TABLE_HEADER sHeader; @@ -2428,20 +2428,20 @@ typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO }ATOM_MULTIMEDIA_CONFIG_INFO; -/****************************************************************************/ +/****************************************************************************/ // Structures used in FirmwareInfoTable -/****************************************************************************/ +/****************************************************************************/ // usBIOSCapability Definition: -// Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted; -// Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported; -// Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported; +// Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted; +// Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported; +// Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported; // Others: Reserved #define ATOM_BIOS_INFO_ATOM_FIRMWARE_POSTED 0x0001 #define ATOM_BIOS_INFO_DUAL_CRTC_SUPPORT 0x0002 #define ATOM_BIOS_INFO_EXTENDED_DESKTOP_SUPPORT 0x0004 -#define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT 0x0008 // (valid from v1.1 ~v1.4):=1: memclk SS enable, =0 memclk SS disable. -#define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT 0x0010 // (valid from v1.1 ~v1.4):=1: engclk SS enable, =0 engclk SS disable. +#define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT 0x0008 // (valid from v1.1 ~v1.4):=1: memclk SS enable, =0 memclk SS disable. +#define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT 0x0010 // (valid from v1.1 ~v1.4):=1: engclk SS enable, =0 engclk SS disable. #define ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU 0x0020 #define ATOM_BIOS_INFO_WMI_SUPPORT 0x0040 #define ATOM_BIOS_INFO_PPMODE_ASSIGNGED_BY_SYSTEM 0x0080 @@ -2505,7 +2505,7 @@ typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS typedef struct _ATOM_FIRMWARE_INFO { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; ULONG ulFirmwareRevision; ULONG ulDefaultEngineClock; //In 10Khz unit ULONG ulDefaultMemoryClock; //In 10Khz unit @@ -2530,8 +2530,8 @@ typedef struct _ATOM_FIRMWARE_INFO USHORT usMaxPixelClockPLL_Input; //In 10Khz unit USHORT usMinPixelClockPLL_Output; //In 10Khz unit, the definitions above can't change!!! ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; - USHORT usReferenceClock; //In 10Khz unit - USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit + USHORT usReferenceClock; //In 10Khz unit + USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit UCHAR ucDesign_ID; //Indicate what is the board design UCHAR ucMemoryModule_ID; //Indicate what is the board design @@ -2539,7 +2539,7 @@ typedef struct _ATOM_FIRMWARE_INFO typedef struct _ATOM_FIRMWARE_INFO_V1_2 { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; ULONG ulFirmwareRevision; ULONG ulDefaultEngineClock; //In 10Khz unit ULONG ulDefaultMemoryClock; //In 10Khz unit @@ -2566,8 +2566,8 @@ typedef struct _ATOM_FIRMWARE_INFO_V1_2 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; - USHORT usReferenceClock; //In 10Khz unit - USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit + USHORT usReferenceClock; //In 10Khz unit + USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit UCHAR ucDesign_ID; //Indicate what is the board design UCHAR ucMemoryModule_ID; //Indicate what is the board design @@ -2575,7 +2575,7 @@ typedef struct _ATOM_FIRMWARE_INFO_V1_2 typedef struct _ATOM_FIRMWARE_INFO_V1_3 { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; ULONG ulFirmwareRevision; ULONG ulDefaultEngineClock; //In 10Khz unit ULONG ulDefaultMemoryClock; //In 10Khz unit @@ -2603,8 +2603,8 @@ typedef struct _ATOM_FIRMWARE_INFO_V1_3 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; - USHORT usReferenceClock; //In 10Khz unit - USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit + USHORT usReferenceClock; //In 10Khz unit + USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit UCHAR ucDesign_ID; //Indicate what is the board design UCHAR ucMemoryModule_ID; //Indicate what is the board design @@ -2612,7 +2612,7 @@ typedef struct _ATOM_FIRMWARE_INFO_V1_3 typedef struct _ATOM_FIRMWARE_INFO_V1_4 { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; ULONG ulFirmwareRevision; ULONG ulDefaultEngineClock; //In 10Khz unit ULONG ulDefaultMemoryClock; //In 10Khz unit @@ -2641,8 +2641,8 @@ typedef struct _ATOM_FIRMWARE_INFO_V1_4 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; - USHORT usReferenceClock; //In 10Khz unit - USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit + USHORT usReferenceClock; //In 10Khz unit + USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit UCHAR ucDesign_ID; //Indicate what is the board design UCHAR ucMemoryModule_ID; //Indicate what is the board design @@ -2651,7 +2651,7 @@ typedef struct _ATOM_FIRMWARE_INFO_V1_4 //the structure below to be used from Cypress typedef struct _ATOM_FIRMWARE_INFO_V2_1 { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; ULONG ulFirmwareRevision; ULONG ulDefaultEngineClock; //In 10Khz unit ULONG ulDefaultMemoryClock; //In 10Khz unit @@ -2680,8 +2680,8 @@ typedef struct _ATOM_FIRMWARE_INFO_V2_1 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; - USHORT usCoreReferenceClock; //In 10Khz unit - USHORT usMemoryReferenceClock; //In 10Khz unit + USHORT usCoreReferenceClock; //In 10Khz unit + USHORT usMemoryReferenceClock; //In 10Khz unit USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock UCHAR ucMemoryModule_ID; //Indicate what is the board design UCHAR ucReserved4[3]; @@ -2692,17 +2692,17 @@ typedef struct _ATOM_FIRMWARE_INFO_V2_1 //ucTableContentRevision=2 typedef struct _ATOM_FIRMWARE_INFO_V2_2 { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; ULONG ulFirmwareRevision; ULONG ulDefaultEngineClock; //In 10Khz unit ULONG ulDefaultMemoryClock; //In 10Khz unit - ULONG ulSPLL_OutputFreq; //In 10Khz unit + ULONG ulSPLL_OutputFreq; //In 10Khz unit ULONG ulGPUPLL_OutputFreq; //In 10Khz unit ULONG ulReserved1; //Was ulMaxEngineClockPLL_Output; //In 10Khz unit* ULONG ulReserved2; //Was ulMaxMemoryClockPLL_Output; //In 10Khz unit* ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock ? - ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit. This is the frequency before DCDTO, corresponding to usBootUpVDDCVoltage. + ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit. This is the frequency before DCDTO, corresponding to usBootUpVDDCVoltage. UCHAR ucReserved3; //Was ucASICMaxTemperature; UCHAR ucMinAllowedBL_Level; USHORT usBootUpVDDCVoltage; //In MV unit @@ -2719,8 +2719,8 @@ typedef struct _ATOM_FIRMWARE_INFO_V2_2 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit USHORT usBootUpVDDCIVoltage; //In unit of mv; Was usMinPixelClockPLL_Output; ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; - USHORT usCoreReferenceClock; //In 10Khz unit - USHORT usMemoryReferenceClock; //In 10Khz unit + USHORT usCoreReferenceClock; //In 10Khz unit + USHORT usMemoryReferenceClock; //In 10Khz unit USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock UCHAR ucMemoryModule_ID; //Indicate what is the board design UCHAR ucReserved9[3]; @@ -2736,9 +2736,9 @@ typedef struct _ATOM_FIRMWARE_INFO_V2_2 #define REMOTE_DISPLAY_DISABLE 0x00 #define REMOTE_DISPLAY_ENABLE 0x01 -/****************************************************************************/ +/****************************************************************************/ // Structures used in IntegratedSystemInfoTable -/****************************************************************************/ +/****************************************************************************/ #define IGP_CAP_FLAG_DYNAMIC_CLOCK_EN 0x2 #define IGP_CAP_FLAG_AC_CARD 0x4 #define IGP_CAP_FLAG_SDVO_CARD 0x8 @@ -2746,7 +2746,7 @@ typedef struct _ATOM_FIRMWARE_INFO_V2_2 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; ULONG ulBootUpEngineClock; //in 10kHz unit ULONG ulBootUpMemoryClock; //in 10kHz unit ULONG ulMaxSystemMemoryClock; //in 10kHz unit @@ -2754,8 +2754,8 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO UCHAR ucNumberOfCyclesInPeriodHi; UCHAR ucLCDTimingSel; //=0:not valid.!=0 sel this timing descriptor from LCD EDID. USHORT usReserved1; - USHORT usInterNBVoltageLow; //An intermidiate PMW value to set the voltage - USHORT usInterNBVoltageHigh; //Another intermidiate PMW value to set the voltage + USHORT usInterNBVoltageLow; //An intermidiate PMW value to set the voltage + USHORT usInterNBVoltageHigh; //Another intermidiate PMW value to set the voltage ULONG ulReserved[2]; USHORT usFSBClock; //In MHz unit @@ -2769,22 +2769,22 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO UCHAR ucMaxNBVoltage; UCHAR ucMinNBVoltage; UCHAR ucMemoryType; //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved - UCHAR ucNumberOfCyclesInPeriod; //CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod + UCHAR ucNumberOfCyclesInPeriod; //CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod UCHAR ucStartingPWM_HighTime; //CG.FVTHROT_PWM_CTRL_REG0.StartingPWM_HighTime UCHAR ucHTLinkWidth; //16 bit vs. 8 bit - UCHAR ucMaxNBVoltageHigh; + UCHAR ucMaxNBVoltageHigh; UCHAR ucMinNBVoltageHigh; }ATOM_INTEGRATED_SYSTEM_INFO; /* Explanation on entries in ATOM_INTEGRATED_SYSTEM_INFO -ulBootUpMemoryClock: For Intel IGP,it's the UMA system memory clock +ulBootUpMemoryClock: For Intel IGP,it's the UMA system memory clock For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock ulMaxSystemMemoryClock: For Intel IGP,it's the Max freq from memory SPD if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 For AMD IGP,for now this can be 0 -ulMinSystemMemoryClock: For Intel IGP,it's 133MHz if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 +ulMinSystemMemoryClock: For Intel IGP,it's 133MHz if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 For AMD IGP,for now this can be 0 -usFSBClock: For Intel IGP,it's FSB Freq +usFSBClock: For Intel IGP,it's FSB Freq For AMD IGP,it's HT Link Speed usK8MemoryClock: For AMD IGP only. For RevF CPU, set it to 200 @@ -2795,8 +2795,8 @@ VC:Voltage Control ucMaxNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. ucMinNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all. -ucNumberOfCyclesInPeriod: Indicate how many cycles when PWM duty is 100%. low 8 bits of the value. -ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0 +ucNumberOfCyclesInPeriod: Indicate how many cycles when PWM duty is 100%. low 8 bits of the value. +ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0 ucMaxNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. ucMinNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all. @@ -2809,7 +2809,7 @@ usInterNBVoltageHigh: Voltage regulator dependent PWM value. The value makes t /* The following IGP table is introduced from RS780, which is supposed to be put by SBIOS in FB before IGP VBIOS starts VPOST; -Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data structure to get whatever they need. +Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data structure to get whatever they need. The enough reservation should allow us to never change table revisions. Whenever needed, a GPU SW component can use reserved portion for new data entries. SW components can access the IGP system infor structure in the same way as before @@ -2856,23 +2856,23 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 USHORT usFirmwareVersion; //0 means FW is not supported. Otherwise it's the FW version loaded by SBIOS and driver should enable FW. USHORT usFullT0Time; // Input to calculate minimum HT link change time required by NB P-State. Unit is 0.01us. ULONG ulReserved3[96]; //must be 0x0 -}ATOM_INTEGRATED_SYSTEM_INFO_V2; +}ATOM_INTEGRATED_SYSTEM_INFO_V2; /* ulBootUpEngineClock: Boot-up Engine Clock in 10Khz; ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not present,this could be equal to or less than maximum supported Sideport memory clock -ulSystemConfig: -Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode; +ulSystemConfig: +Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode; Bit[1]=1: system boots up at AMD overdrived state or user customized mode. In this case, driver will just stick to this boot-up mode. No other PowerPlay state =0: system boots up at driver control state. Power state depends on PowerPlay table. Bit[2]=1: PWM method is used on NB voltage control. =0: GPIO method is used. Bit[3]=1: Only one power state(Performance) will be supported. =0: Multiple power states supported from PowerPlay table. -Bit[4]=1: CLMC is supported and enabled on current system. - =0: CLMC is not supported or enabled on current system. SBIOS need to support HT link/freq change through ATIF interface. -Bit[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT width is determined by display requirement. +Bit[4]=1: CLMC is supported and enabled on current system. + =0: CLMC is not supported or enabled on current system. SBIOS need to support HT link/freq change through ATIF interface. +Bit[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT width is determined by display requirement. =0: CDLW is disabled. If CLMC is enabled case, Min HT width will be set equal to Max HT width. If CLMC disabled case, Max HT width will be applied. Bit[6]=1: High Voltage requested for all power states. In this case, voltage will be forced at 1.1v and powerplay table voltage drop/throttling request will be ignored. =0: Voltage settings is determined by powerplay table. @@ -2891,11 +2891,11 @@ ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full pan ulDDISlot1Config: Describes the PCIE lane configuration on this DDI PCIE slot (ADD2 card) or connector (Mobile design). [3:0] - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12) [7:4] - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station (bit 4=1 lane 3:0; bit 5=1 lane 7:4; bit 6=1 lane 11:8; bit 7=1 lane 15:12) - When a DDI connector is not "paired" (meaming two connections mutualexclusive on chassis or docking, only one of them can be connected at one time. + When a DDI connector is not "paired" (meaning two connections mutually exclusive on chassis or docking, only one of them can be connected at one time. in both chassis and docking, SBIOS has to duplicate the same PCIE lane info from chassis to docking or vice versa. For example: one DDI connector is only populated in docking with PCIE lane 8-11, but there is no paired connection on chassis, SBIOS has to copy bit 6 to bit 2. - [15:8] - Lane configuration attribute; + [15:8] - Lane configuration attribute; [23:16]- Connector type, possible value: CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D @@ -2910,7 +2910,7 @@ For IGP, Hypermemory is the only memory type showed in CCC. ucUMAChannelNumber: how many channels for the UMA; -ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin +ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin ucDockingPinBit: which bit in this register to read the pin status; ucDockingPinPolarity:Polarity of the pin when docked; @@ -2918,7 +2918,7 @@ ulCPUCapInfo: [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, [7:0]=4:Phara usNumberOfCyclesInPeriod:Indicate how many cycles when PWM duty is 100%. -usMaxNBVoltage:Max. voltage control value in either PWM or GPIO mode. +usMaxNBVoltage:Max. voltage control value in either PWM or GPIO mode. usMinNBVoltage:Min. voltage control value in either PWM or GPIO mode. GPIO mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=0 PWM mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=1 @@ -2927,14 +2927,14 @@ usMinNBVoltage:Min. voltage control value in either PWM or GPIO mode. usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value. ulHTLinkFreq: Bootup HT link Frequency in 10Khz. -usMinHTLinkWidth: Bootup minimum HT link width. If CDLW disabled, this is equal to usMaxHTLinkWidth. +usMinHTLinkWidth: Bootup minimum HT link width. If CDLW disabled, this is equal to usMaxHTLinkWidth. + If CDLW enabled, both upstream and downstream width should be the same during bootup. +usMaxHTLinkWidth: Bootup maximum HT link width. If CDLW disabled, this is equal to usMinHTLinkWidth. If CDLW enabled, both upstream and downstream width should be the same during bootup. -usMaxHTLinkWidth: Bootup maximum HT link width. If CDLW disabled, this is equal to usMinHTLinkWidth. - If CDLW enabled, both upstream and downstream width should be the same during bootup. -usUMASyncStartDelay: Memory access latency, required for watermark calculation +usUMASyncStartDelay: Memory access latency, required for watermark calculation usUMADataReturnTime: Memory access latency, required for watermark calculation -usLinkStatusZeroTime:Memory access latency required for watermark calculation, set this to 0x0 for K8 CPU, set a proper value in 0.01 the unit of us +usLinkStatusZeroTime:Memory access latency required for watermark calculation, set this to 0x0 for K8 CPU, set a proper value in 0.01 the unit of us for Griffin or Greyhound. SBIOS needs to convert to actual time by: if T0Ttime [5:4]=00b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.1us (0.0 to 1.5us) if T0Ttime [5:4]=01b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.5us (0.0 to 7.5us) @@ -2942,7 +2942,7 @@ for Griffin or Greyhound. SBIOS needs to convert to actual time by: if T0Ttime [5:4]=11b, and T0Ttime [3:0]=0x0 to 0xa, then usLinkStatusZeroTime=T0Ttime [3:0]*20us (0.0 to 200us) ulHighVoltageHTLinkFreq: HT link frequency for power state with low voltage. If boot up runs in HT1, this must be 0. - This must be less than or equal to ulHTLinkFreq(bootup frequency). + This must be less than or equal to ulHTLinkFreq(bootup frequency). ulLowVoltageHTLinkFreq: HT link frequency for power state with low voltage or voltage scaling 1.0v~1.1v. If boot up runs in HT1, this must be 0. This must be less than or equal to ulHighVoltageHTLinkFreq. @@ -2952,7 +2952,7 @@ usMinUpStreamHTLinkWidth: Asymmetric link width support in the future, to rep usMinDownStreamHTLinkWidth: same as above. */ -// ATOM_INTEGRATED_SYSTEM_INFO::ulCPUCapInfo - CPU type definition +// ATOM_INTEGRATED_SYSTEM_INFO::ulCPUCapInfo - CPU type definition #define INTEGRATED_SYSTEM_INFO__UNKNOWN_CPU 0 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__GRIFFIN 1 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__GREYHOUND 2 @@ -2964,7 +2964,7 @@ usMinDownStreamHTLinkWidth: same as above. #define SYSTEM_CONFIG_POWEREXPRESS_ENABLE 0x00000001 #define SYSTEM_CONFIG_RUN_AT_OVERDRIVE_ENGINE 0x00000002 -#define SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE 0x00000004 +#define SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE 0x00000004 #define SYSTEM_CONFIG_PERFORMANCE_POWERSTATE_ONLY 0x00000008 #define SYSTEM_CONFIG_CLMC_ENABLED 0x00000010 #define SYSTEM_CONFIG_CDLW_ENABLED 0x00000020 @@ -2993,7 +2993,7 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 { ATOM_COMMON_TABLE_HEADER sHeader; ULONG ulBootUpEngineClock; //in 10kHz unit - ULONG ulDentistVCOFreq; //Dentist VCO clock in 10kHz unit, the source of GPU SCLK, LCLK, UCLK and VCLK. + ULONG ulDentistVCOFreq; //Dentist VCO clock in 10kHz unit, the source of GPU SCLK, LCLK, UCLK and VCLK. ULONG ulLClockFreq; //GPU Lclk freq in 10kHz unit, have relationship with NCLK in NorthBridge ULONG ulBootUpUMAClock; //in 10kHz unit ULONG ulReserved1[8]; //must be 0x0 for the reserved @@ -3021,7 +3021,7 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 ULONG ulCSR_M3_ARB_CNTL_UVD[10]; //arrays with values for CSR M3 arbiter for UVD playback ULONG ulCSR_M3_ARB_CNTL_FS3D[10];//arrays with values for CSR M3 arbiter for Full Screen 3D applications ULONG ulReserved6[61]; //must be 0x0 -}ATOM_INTEGRATED_SYSTEM_INFO_V5; +}ATOM_INTEGRATED_SYSTEM_INFO_V5; #define ATOM_CRT_INT_ENCODER1_INDEX 0x00000000 #define ATOM_LCD_INT_ENCODER1_INDEX 0x00000001 @@ -3039,7 +3039,7 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 #define ATOM_DFP_INT_ENCODER4_INDEX 0x0000000D // define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSelTable -#define ASIC_INT_DAC1_ENCODER_ID 0x00 +#define ASIC_INT_DAC1_ENCODER_ID 0x00 #define ASIC_INT_TV_ENCODER_ID 0x02 #define ASIC_INT_DIG1_ENCODER_ID 0x03 #define ASIC_INT_DAC2_ENCODER_ID 0x04 @@ -3056,15 +3056,15 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 //define Encoder attribute #define ATOM_ANALOG_ENCODER 0 -#define ATOM_DIGITAL_ENCODER 1 -#define ATOM_DP_ENCODER 2 +#define ATOM_DIGITAL_ENCODER 1 +#define ATOM_DP_ENCODER 2 #define ATOM_ENCODER_ENUM_MASK 0x70 #define ATOM_ENCODER_ENUM_ID1 0x00 #define ATOM_ENCODER_ENUM_ID2 0x10 #define ATOM_ENCODER_ENUM_ID3 0x20 #define ATOM_ENCODER_ENUM_ID4 0x30 -#define ATOM_ENCODER_ENUM_ID5 0x40 +#define ATOM_ENCODER_ENUM_ID5 0x40 #define ATOM_ENCODER_ENUM_ID6 0x50 #define ATOM_DEVICE_CRT1_INDEX 0x00000000 @@ -3162,8 +3162,8 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 // Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported // Bit 10 = 0 - no DFP4 support= 1- DFP4 is supported // Bit 11 = 0 - no DFP5 support= 1- DFP5 is supported -// -// +// +// /****************************************************************************/ /* Structure used in MclkSS_InfoTable */ @@ -3196,11 +3196,11 @@ typedef union _ATOM_I2C_ID_CONFIG_ACCESS ATOM_I2C_ID_CONFIG sbfAccess; UCHAR ucAccess; }ATOM_I2C_ID_CONFIG_ACCESS; - -/****************************************************************************/ + +/****************************************************************************/ // Structure used in GPIO_I2C_InfoTable -/****************************************************************************/ +/****************************************************************************/ typedef struct _ATOM_GPIO_I2C_ASSIGMENT { USHORT usClkMaskRegisterIndex; @@ -3225,20 +3225,20 @@ typedef struct _ATOM_GPIO_I2C_ASSIGMENT }ATOM_GPIO_I2C_ASSIGMENT; typedef struct _ATOM_GPIO_I2C_INFO -{ +{ ATOM_COMMON_TABLE_HEADER sHeader; ATOM_GPIO_I2C_ASSIGMENT asGPIO_Info[ATOM_MAX_SUPPORTED_DEVICE]; }ATOM_GPIO_I2C_INFO; -/****************************************************************************/ +/****************************************************************************/ // Common Structure used in other structures -/****************************************************************************/ +/****************************************************************************/ #ifndef _H2INC - + //Please don't add or expand this bitfield structure below, this one will retire soon.! typedef struct _ATOM_MODE_MISC_INFO -{ +{ #if ATOM_BIG_ENDIAN USHORT Reserved:6; USHORT RGB888:1; @@ -3262,23 +3262,23 @@ typedef struct _ATOM_MODE_MISC_INFO USHORT Interlace:1; USHORT DoubleClock:1; USHORT RGB888:1; - USHORT Reserved:6; + USHORT Reserved:6; #endif }ATOM_MODE_MISC_INFO; - + typedef union _ATOM_MODE_MISC_INFO_ACCESS -{ +{ ATOM_MODE_MISC_INFO sbfAccess; USHORT usAccess; }ATOM_MODE_MISC_INFO_ACCESS; - + #else - + typedef union _ATOM_MODE_MISC_INFO_ACCESS -{ +{ USHORT usAccess; }ATOM_MODE_MISC_INFO_ACCESS; - + #endif // usModeMiscInfo- @@ -3296,7 +3296,7 @@ typedef union _ATOM_MODE_MISC_INFO_ACCESS //usRefreshRate- #define ATOM_REFRESH_43 43 #define ATOM_REFRESH_47 47 -#define ATOM_REFRESH_56 56 +#define ATOM_REFRESH_56 56 #define ATOM_REFRESH_60 60 #define ATOM_REFRESH_65 65 #define ATOM_REFRESH_70 70 @@ -3315,29 +3315,29 @@ typedef union _ATOM_MODE_MISC_INFO_ACCESS // VESA_HSYNC_WIDTH = VESA_HSYNC_TIME = EDID_HSPW // VESA_BORDER = EDID_BORDER -/****************************************************************************/ +/****************************************************************************/ // Structure used in SetCRTC_UsingDTDTimingTable -/****************************************************************************/ +/****************************************************************************/ typedef struct _SET_CRTC_USING_DTD_TIMING_PARAMETERS { USHORT usH_Size; USHORT usH_Blanking_Time; USHORT usV_Size; - USHORT usV_Blanking_Time; + USHORT usV_Blanking_Time; USHORT usH_SyncOffset; USHORT usH_SyncWidth; USHORT usV_SyncOffset; USHORT usV_SyncWidth; - ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; + ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; UCHAR ucH_Border; // From DFP EDID UCHAR ucV_Border; - UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 + UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 UCHAR ucPadding[3]; }SET_CRTC_USING_DTD_TIMING_PARAMETERS; -/****************************************************************************/ +/****************************************************************************/ // Structure used in SetCRTC_TimingTable -/****************************************************************************/ +/****************************************************************************/ typedef struct _SET_CRTC_TIMING_PARAMETERS { USHORT usH_Total; // horizontal total @@ -3358,11 +3358,11 @@ typedef struct _SET_CRTC_TIMING_PARAMETERS }SET_CRTC_TIMING_PARAMETERS; #define SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION SET_CRTC_TIMING_PARAMETERS -/****************************************************************************/ +/****************************************************************************/ // Structure used in StandardVESA_TimingTable -// AnalogTV_InfoTable +// AnalogTV_InfoTable // ComponentVideoInfoTable -/****************************************************************************/ +/****************************************************************************/ typedef struct _ATOM_MODE_TIMING { USHORT usCRTC_H_Total; @@ -3390,7 +3390,7 @@ typedef struct _ATOM_DTD_FORMAT USHORT usHActive; USHORT usHBlanking_Time; USHORT usVActive; - USHORT usVBlanking_Time; + USHORT usVBlanking_Time; USHORT usHSyncOffset; USHORT usHSyncWidth; USHORT usVSyncOffset; @@ -3404,10 +3404,10 @@ typedef struct _ATOM_DTD_FORMAT UCHAR ucRefreshRate; }ATOM_DTD_FORMAT; -/****************************************************************************/ -// Structure used in LVDS_InfoTable +/****************************************************************************/ +// Structure used in LVDS_InfoTable // * Need a document to describe this table -/****************************************************************************/ +/****************************************************************************/ #define SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 #define SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 #define SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 @@ -3417,7 +3417,7 @@ typedef struct _ATOM_DTD_FORMAT //ucTableContentRevision=1 typedef struct _ATOM_LVDS_INFO { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; ATOM_DTD_FORMAT sLCDTiming; USHORT usModePatchTableOffset; USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. @@ -3437,7 +3437,7 @@ typedef struct _ATOM_LVDS_INFO //ucTableContentRevision=2 typedef struct _ATOM_LVDS_INFO_V12 { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; ATOM_DTD_FORMAT sLCDTiming; USHORT usExtInfoTableOffset; USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. @@ -3453,15 +3453,15 @@ typedef struct _ATOM_LVDS_INFO_V12 UCHAR ucSS_Id; USHORT usLCDVenderID; USHORT usLCDProductID; - UCHAR ucLCDPanel_SpecialHandlingCap; + UCHAR ucLCDPanel_SpecialHandlingCap; UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable UCHAR ucReserved[2]; }ATOM_LVDS_INFO_V12; //Definitions for ucLCDPanel_SpecialHandlingCap: -//Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. -//Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL +//Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. +//Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL #define LCDPANEL_CAP_READ_EDID 0x1 //If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together @@ -3486,21 +3486,21 @@ typedef struct _ATOM_LVDS_INFO_V12 #define PANEL_COLOR_BIT_DEPTH_MASK 0x70 -// Bit7:{=0:Random Dithering disabled;1 Random Dithering enabled} +// Bit7:{=0:Random Dithering disabled;1 Random Dithering enabled} #define PANEL_RANDOM_DITHER 0x80 #define PANEL_RANDOM_DITHER_MASK 0x80 -#define ATOM_LVDS_INFO_LAST ATOM_LVDS_INFO_V12 // no need to change this +#define ATOM_LVDS_INFO_LAST ATOM_LVDS_INFO_V12 // no need to change this -/****************************************************************************/ +/****************************************************************************/ // Structures used by LCD_InfoTable V1.3 Note: previous version was called ATOM_LVDS_INFO_V12 // ASIC Families: NI // ucTableFormatRevision=1 // ucTableContentRevision=3 -/****************************************************************************/ +/****************************************************************************/ typedef struct _ATOM_LCD_INFO_V13 { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; ATOM_DTD_FORMAT sLCDTiming; USHORT usExtInfoTableOffset; USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. @@ -3509,18 +3509,18 @@ typedef struct _ATOM_LCD_INFO_V13 // Bit0: {=0:single, =1:dual}, // Bit1: {=0:LDI format for RGB888, =1 FPDI format for RGB888} // was {=0:666RGB, =1:888RGB}, // Bit3:2: {Grey level} - // Bit6:4 Color Bit Depth definition (see below definition in EDID V1.4 @BYTE 14h) - // Bit7 Reserved. was for ATOM_PANEL_MISC_API_ENABLED, still need it? + // Bit6:4 Color Bit Depth definition (see below definition in EDID V1.4 @BYTE 14h) + // Bit7 Reserved. was for ATOM_PANEL_MISC_API_ENABLED, still need it? UCHAR ucPanelDefaultRefreshRate; UCHAR ucPanelIdentification; UCHAR ucSS_Id; USHORT usLCDVenderID; USHORT usLCDProductID; - UCHAR ucLCDPanel_SpecialHandlingCap; // Reorganized in V13 + UCHAR ucLCDPanel_SpecialHandlingCap; // Reorganized in V13 // Bit0: Once DAL sees this CAP is set, it will read EDID from LCD on its own // Bit1: See LCDPANEL_CAP_DRR_SUPPORTED // Bit2: a quick reference whether an embadded panel (LCD1 ) is LVDS (0) or eDP (1) - // Bit7-3: Reserved + // Bit7-3: Reserved UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable USHORT usBacklightPWM; // Backlight PWM in Hz. New in _V13 @@ -3539,13 +3539,13 @@ typedef struct _ATOM_LCD_INFO_V13 UCHAR ucDPCD_MAX_LANE_COUNT; // dpcd 02h UCHAR ucDPCD_MAX_DOWNSPREAD; // dpcd 03h - USHORT usMaxPclkFreqInSingleLink; // Max PixelClock frequency in single link mode. + USHORT usMaxPclkFreqInSingleLink; // Max PixelClock frequency in single link mode. UCHAR uceDPToLVDSRxId; UCHAR ucLcdReservd; ULONG ulReserved[2]; -}ATOM_LCD_INFO_V13; +}ATOM_LCD_INFO_V13; -#define ATOM_LCD_INFO_LAST ATOM_LCD_INFO_V13 +#define ATOM_LCD_INFO_LAST ATOM_LCD_INFO_V13 //Definitions for ucLCD_Misc #define ATOM_PANEL_MISC_V13_DUAL 0x00000001 @@ -3566,11 +3566,11 @@ typedef struct _ATOM_LCD_INFO_V13 // 1 0 1 - 14 Bits per Primary Color // 1 1 0 - 16 Bits per Primary Color // 1 1 1 - Reserved - + //Definitions for ucLCDPanel_SpecialHandlingCap: -//Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. -//Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL +//Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. +//Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL #define LCDPANEL_CAP_V13_READ_EDID 0x1 // = LCDPANEL_CAP_READ_EDID no change comparing to previous version //If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together @@ -3582,9 +3582,9 @@ typedef struct _ATOM_LCD_INFO_V13 #define LCDPANEL_CAP_V13_eDP 0x4 // = LCDPANEL_CAP_eDP no change comparing to previous version //uceDPToLVDSRxId -#define eDP_TO_LVDS_RX_DISABLE 0x00 // no eDP->LVDS translator chip +#define eDP_TO_LVDS_RX_DISABLE 0x00 // no eDP->LVDS translator chip #define eDP_TO_LVDS_COMMON_ID 0x01 // common eDP->LVDS translator chip without AMD SW init -#define eDP_TO_LVDS_RT_ID 0x02 // RT tanslator which require AMD SW init +#define eDP_TO_LVDS_RT_ID 0x02 // RT translator which require AMD SW init typedef struct _ATOM_PATCH_RECORD_MODE { @@ -3639,7 +3639,7 @@ typedef struct _ATOM_PANEL_RESOLUTION_PATCH_RECORD //ucTableContentRevision=2 typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT { - USHORT usSpreadSpectrumPercentage; + USHORT usSpreadSpectrumPercentage; UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Bit2=1: PCIE REFCLK SS =0 iternal PPLL SS Others:TBD UCHAR ucSS_Step; UCHAR ucSS_Delay; @@ -3649,8 +3649,8 @@ typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT }ATOM_SPREAD_SPECTRUM_ASSIGNMENT; #define ATOM_MAX_SS_ENTRY 16 -#define ATOM_DP_SS_ID1 0x0f1 // SS ID for internal DP stream at 2.7Ghz. if ATOM_DP_SS_ID2 does not exist in SS_InfoTable, it is used for internal DP stream at 1.62Ghz as well. -#define ATOM_DP_SS_ID2 0x0f2 // SS ID for internal DP stream at 1.62Ghz, if it exists in SS_InfoTable. +#define ATOM_DP_SS_ID1 0x0f1 // SS ID for internal DP stream at 2.7Ghz. if ATOM_DP_SS_ID2 does not exist in SS_InfoTable, it is used for internal DP stream at 1.62Ghz as well. +#define ATOM_DP_SS_ID2 0x0f2 // SS ID for internal DP stream at 1.62Ghz, if it exists in SS_InfoTable. #define ATOM_LVLINK_2700MHz_SS_ID 0x0f3 // SS ID for LV link translator chip at 2.7Ghz #define ATOM_LVLINK_1620MHz_SS_ID 0x0f4 // SS ID for LV link translator chip at 1.62Ghz @@ -3662,18 +3662,18 @@ typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT #define ATOM_INTERNAL_SS_MASK 0x00000000 #define ATOM_EXTERNAL_SS_MASK 0x00000002 #define EXEC_SS_STEP_SIZE_SHIFT 2 -#define EXEC_SS_DELAY_SHIFT 4 +#define EXEC_SS_DELAY_SHIFT 4 #define ACTIVEDATA_TO_BLON_DELAY_SHIFT 4 typedef struct _ATOM_SPREAD_SPECTRUM_INFO -{ +{ ATOM_COMMON_TABLE_HEADER sHeader; ATOM_SPREAD_SPECTRUM_ASSIGNMENT asSS_Info[ATOM_MAX_SS_ENTRY]; }ATOM_SPREAD_SPECTRUM_INFO; -/****************************************************************************/ +/****************************************************************************/ // Structure used in AnalogTV_InfoTable (Top level) -/****************************************************************************/ +/****************************************************************************/ //ucTVBootUpDefaultStd definition: //ATOM_TV_NTSC 1 @@ -3700,9 +3700,9 @@ typedef struct _ATOM_SPREAD_SPECTRUM_INFO typedef struct _ATOM_ANALOG_TV_INFO { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; UCHAR ucTV_SupportedStandard; - UCHAR ucTV_BootUpDefaultStandard; + UCHAR ucTV_BootUpDefaultStandard; UCHAR ucExt_TV_ASIC_ID; UCHAR ucExt_TV_ASIC_SlaveAddr; /*ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING];*/ @@ -3713,9 +3713,9 @@ typedef struct _ATOM_ANALOG_TV_INFO typedef struct _ATOM_ANALOG_TV_INFO_V1_2 { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; UCHAR ucTV_SupportedStandard; - UCHAR ucTV_BootUpDefaultStandard; + UCHAR ucTV_BootUpDefaultStandard; UCHAR ucExt_TV_ASIC_ID; UCHAR ucExt_TV_ASIC_SlaveAddr; ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING_V1_2]; @@ -3723,9 +3723,9 @@ typedef struct _ATOM_ANALOG_TV_INFO_V1_2 typedef struct _ATOM_DPCD_INFO { - UCHAR ucRevisionNumber; //10h : Revision 1.0; 11h : Revision 1.1 + UCHAR ucRevisionNumber; //10h : Revision 1.0; 11h : Revision 1.1 UCHAR ucMaxLinkRate; //06h : 1.62Gbps per lane; 0Ah = 2.7Gbps per lane - UCHAR ucMaxLane; //Bits 4:0 = MAX_LANE_COUNT (1/2/4). Bit 7 = ENHANCED_FRAME_CAP + UCHAR ucMaxLane; //Bits 4:0 = MAX_LANE_COUNT (1/2/4). Bit 7 = ENHANCED_FRAME_CAP UCHAR ucMaxDownSpread; //Bit0 = 0: No Down spread; Bit0 = 1: 0.5% (Subject to change according to DP spec) }ATOM_DPCD_INFO; @@ -3738,7 +3738,7 @@ typedef struct _ATOM_DPCD_INFO // Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down as below. // All the addresses below are the offsets from the frame buffer start.They all MUST be Dword aligned! // To driver: The physical address of this memory portion=mmFB_START(4K aligned)+ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR -// To Bios: ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX +// To Bios: ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX #ifndef VESA_MEMORY_IN_64K_BLOCK #define VESA_MEMORY_IN_64K_BLOCK 0x100 //256*64K=16Mb (Max. VESA memory is 16Mb!) @@ -3748,11 +3748,11 @@ typedef struct _ATOM_DPCD_INFO #define ATOM_HWICON_SURFACE_SIZE 4096 //In Bytes #define ATOM_HWICON_INFOTABLE_SIZE 32 #define MAX_DTD_MODE_IN_VRAM 6 -#define ATOM_DTD_MODE_SUPPORT_TBL_SIZE (MAX_DTD_MODE_IN_VRAM*28) //28= (SIZEOF ATOM_DTD_FORMAT) +#define ATOM_DTD_MODE_SUPPORT_TBL_SIZE (MAX_DTD_MODE_IN_VRAM*28) //28= (SIZEOF ATOM_DTD_FORMAT) #define ATOM_STD_MODE_SUPPORT_TBL_SIZE 32*8 //32 is a predefined number,8= (SIZEOF ATOM_STD_FORMAT) //20 bytes for Encoder Type and DPCD in STD EDID area -#define DFP_ENCODER_TYPE_OFFSET (ATOM_EDID_RAW_DATASIZE + ATOM_DTD_MODE_SUPPORT_TBL_SIZE + ATOM_STD_MODE_SUPPORT_TBL_SIZE - 20) -#define ATOM_DP_DPCD_OFFSET (DFP_ENCODER_TYPE_OFFSET + 4 ) +#define DFP_ENCODER_TYPE_OFFSET (ATOM_EDID_RAW_DATASIZE + ATOM_DTD_MODE_SUPPORT_TBL_SIZE + ATOM_STD_MODE_SUPPORT_TBL_SIZE - 20) +#define ATOM_DP_DPCD_OFFSET (DFP_ENCODER_TYPE_OFFSET + 4 ) #define ATOM_HWICON1_SURFACE_ADDR 0 #define ATOM_HWICON2_SURFACE_ADDR (ATOM_HWICON1_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE) @@ -3805,12 +3805,12 @@ typedef struct _ATOM_DPCD_INFO #define ATOM_DP_TRAINING_TBL_ADDR (ATOM_DFP5_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) -#define ATOM_STACK_STORAGE_START (ATOM_DP_TRAINING_TBL_ADDR + 1024) -#define ATOM_STACK_STORAGE_END ATOM_STACK_STORAGE_START + 512 +#define ATOM_STACK_STORAGE_START (ATOM_DP_TRAINING_TBL_ADDR + 1024) +#define ATOM_STACK_STORAGE_END ATOM_STACK_STORAGE_START + 512 //The size below is in Kb! #define ATOM_VRAM_RESERVE_SIZE ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)+4)&0xFFFC) - + #define ATOM_VRAM_RESERVE_V2_SIZE 32 #define ATOM_VRAM_OPERATION_FLAGS_MASK 0xC0000000L @@ -3818,18 +3818,18 @@ typedef struct _ATOM_DPCD_INFO #define ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION 0x1 #define ATOM_VRAM_BLOCK_NEEDS_RESERVATION 0x0 -/***********************************************************************************/ +/***********************************************************************************/ // Structure used in VRAM_UsageByFirmwareTable // Note1: This table is filled by SetBiosReservationStartInFB in CoreCommSubs.asm -// at running time. -// note2: From RV770, the memory is more than 32bit addressable, so we will change +// at running time. +// note2: From RV770, the memory is more than 32bit addressable, so we will change // ucTableFormatRevision=1,ucTableContentRevision=4, the structure remains -// exactly same as 1.1 and 1.2 (1.3 is never in use), but ulStartAddrUsedByFirmware -// (in offset to start of memory address) is KB aligned instead of byte aligend. -/***********************************************************************************/ +// exactly same as 1.1 and 1.2 (1.3 is never in use), but ulStartAddrUsedByFirmware +// (in offset to start of memory address) is KB aligned instead of byte aligned. +/***********************************************************************************/ // Note3: /* If we change usReserved to "usFBUsedbyDrvInKB", then to VBIOS this usFBUsedbyDrvInKB is a predefined, unchanged constant across VGA or non VGA adapter, -for CAIL, The size of FB access area is known, only thing missing is the Offset of FB Access area, so we can have: +for CAIL, The size of FB access area is known, only thing missing is the Offset of FB Access area, so we can have: If (ulStartAddrUsedByFirmware!=0) FBAccessAreaOffset= ulStartAddrUsedByFirmware - usFBUsedbyDrvInKB; @@ -3842,7 +3842,7 @@ else //Non VGA case CAIL needs to claim an reserved area defined by FBAccessAreaOffset and usFBUsedbyDrvInKB in non VGA case.*/ -/***********************************************************************************/ +/***********************************************************************************/ #define ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO 1 typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO @@ -3854,7 +3854,7 @@ typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; ATOM_FIRMWARE_VRAM_RESERVE_INFO asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO]; }ATOM_VRAM_USAGE_BY_FIRMWARE; @@ -3868,13 +3868,13 @@ typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5 { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO]; }ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5; -/****************************************************************************/ +/****************************************************************************/ // Structure used in GPIO_Pin_LUTTable -/****************************************************************************/ +/****************************************************************************/ typedef struct _ATOM_GPIO_PIN_ASSIGNMENT { USHORT usGpioPin_AIndex; @@ -3896,9 +3896,9 @@ typedef struct _ATOM_GPIO_PIN_LUT ATOM_GPIO_PIN_ASSIGNMENT asGPIO_Pin[1]; }ATOM_GPIO_PIN_LUT; -/****************************************************************************/ -// Structure used in ComponentVideoInfoTable -/****************************************************************************/ +/****************************************************************************/ +// Structure used in ComponentVideoInfoTable +/****************************************************************************/ #define GPIO_PIN_ACTIVE_HIGH 0x1 #define MAX_SUPPORTED_CV_STANDARDS 5 @@ -3926,25 +3926,25 @@ typedef struct _ATOM_GPIO_INFO //Line 3 out put 5V. #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_A 0x01 //represent gpio 3 state for 16:9 #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_B 0x02 //represent gpio 4 state for 16:9 -#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_SHIFT 0x0 +#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_SHIFT 0x0 -//Line 3 out put 2.2V +//Line 3 out put 2.2V #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_A 0x04 //represent gpio 3 state for 4:3 Letter box #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_B 0x08 //represent gpio 4 state for 4:3 Letter box -#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_SHIFT 0x2 +#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_SHIFT 0x2 //Line 3 out put 0V #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_A 0x10 //represent gpio 3 state for 4:3 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_B 0x20 //represent gpio 4 state for 4:3 -#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_SHIFT 0x4 +#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_SHIFT 0x4 #define ATOM_CV_LINE3_ASPECTRATIO_MASK 0x3F // bit [5:0] #define ATOM_CV_LINE3_ASPECTRATIO_EXIST 0x80 //bit 7 -//GPIO bit index in gpio setting per mode value, also represend the block no. in gpio blocks. -#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_A 3 //bit 3 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. -#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_B 4 //bit 4 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. +//GPIO bit index in gpio setting per mode value, also represent the block no. in gpio blocks. +#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_A 3 //bit 3 in uc480i/uc480p/uc720p/uc1080i, which represent the default gpio bit setting for the mode. +#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_B 4 //bit 4 in uc480i/uc480p/uc720p/uc1080i, which represent the default gpio bit setting for the mode. typedef struct _ATOM_COMPONENT_VIDEO_INFO @@ -3988,11 +3988,11 @@ typedef struct _ATOM_COMPONENT_VIDEO_INFO_V21 #define ATOM_COMPONENT_VIDEO_INFO_LAST ATOM_COMPONENT_VIDEO_INFO_V21 -/****************************************************************************/ +/****************************************************************************/ // Structure used in object_InfoTable -/****************************************************************************/ +/****************************************************************************/ typedef struct _ATOM_OBJECT_HEADER -{ +{ ATOM_COMMON_TABLE_HEADER sHeader; USHORT usDeviceSupport; USHORT usConnectorObjectTableOffset; @@ -4003,7 +4003,7 @@ typedef struct _ATOM_OBJECT_HEADER }ATOM_OBJECT_HEADER; typedef struct _ATOM_OBJECT_HEADER_V3 -{ +{ ATOM_COMMON_TABLE_HEADER sHeader; USHORT usDeviceSupport; USHORT usConnectorObjectTableOffset; @@ -4016,20 +4016,20 @@ typedef struct _ATOM_OBJECT_HEADER_V3 typedef struct _ATOM_DISPLAY_OBJECT_PATH { - USHORT usDeviceTag; //supported device + USHORT usDeviceTag; //supported device USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH - USHORT usConnObjectId; //Connector Object ID - USHORT usGPUObjectId; //GPU ID - USHORT usGraphicObjIds[1]; //1st Encoder Obj source from GPU to last Graphic Obj destinate to connector. + USHORT usConnObjectId; //Connector Object ID + USHORT usGPUObjectId; //GPU ID + USHORT usGraphicObjIds[1]; //1st Encoder Obj source from GPU to last Graphic Obj destinate to connector. }ATOM_DISPLAY_OBJECT_PATH; typedef struct _ATOM_DISPLAY_EXTERNAL_OBJECT_PATH { - USHORT usDeviceTag; //supported device + USHORT usDeviceTag; //supported device USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH - USHORT usConnObjectId; //Connector Object ID - USHORT usGPUObjectId; //GPU ID - USHORT usGraphicObjIds[2]; //usGraphicObjIds[0]= GPU internal encoder, usGraphicObjIds[1]= external encoder + USHORT usConnObjectId; //Connector Object ID + USHORT usGPUObjectId; //GPU ID + USHORT usGraphicObjIds[2]; //usGraphicObjIds[0]= GPU internal encoder, usGraphicObjIds[1]= external encoder }ATOM_DISPLAY_EXTERNAL_OBJECT_PATH; typedef struct _ATOM_DISPLAY_OBJECT_PATH_TABLE @@ -4041,7 +4041,7 @@ typedef struct _ATOM_DISPLAY_OBJECT_PATH_TABLE }ATOM_DISPLAY_OBJECT_PATH_TABLE; -typedef struct _ATOM_OBJECT //each object has this structure +typedef struct _ATOM_OBJECT //each object has this structure { USHORT usObjectID; USHORT usSrcDstTableOffset; @@ -4049,7 +4049,7 @@ typedef struct _ATOM_OBJECT //each object has thi USHORT usReserved; }ATOM_OBJECT; -typedef struct _ATOM_OBJECT_TABLE //Above 4 object table offset pointing to a bunch of objects all have this structure +typedef struct _ATOM_OBJECT_TABLE //Above 4 object table offset pointing to a bunch of objects all have this structure { UCHAR ucNumberOfObjects; UCHAR ucPadding[3]; @@ -4088,7 +4088,7 @@ typedef struct _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT //usSrcDstTableOffset #define MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES (EXT_AUXDDC_LUTINDEX_7+1) //ucChannelMapping are defined as following -//for DP connector, eDP, DP to VGA/LVDS +//for DP connector, eDP, DP to VGA/LVDS //Bit[1:0]: Define which pin connect to DP connector DP_Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 //Bit[3:2]: Define which pin connect to DP connector DP_Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 //Bit[5:4]: Define which pin connect to DP connector DP_Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 @@ -4108,7 +4108,7 @@ typedef struct _ATOM_DP_CONN_CHANNEL_MAPPING #endif }ATOM_DP_CONN_CHANNEL_MAPPING; -//for DVI/HDMI, in dual link case, both links have to have same mapping. +//for DVI/HDMI, in dual link case, both links have to have same mapping. //Bit[1:0]: Define which pin connect to DVI connector data Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 //Bit[3:2]: Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 //Bit[5:4]: Define which pin connect to DVI connector data Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 @@ -4130,8 +4130,8 @@ typedef struct _ATOM_DVI_CONN_CHANNEL_MAPPING typedef struct _EXT_DISPLAY_PATH { - USHORT usDeviceTag; //A bit vector to show what devices are supported - USHORT usDeviceACPIEnum; //16bit device ACPI id. + USHORT usDeviceTag; //A bit vector to show what devices are supported + USHORT usDeviceACPIEnum; //16bit device ACPI id. USHORT usDeviceConnector; //A physical connector for displays to plug in, using object connector definitions UCHAR ucExtAUXDDCLutIndex; //An index into external AUX/DDC channel LUT UCHAR ucExtHPDPINLutIndex; //An index into external HPD pin LUT @@ -4143,9 +4143,9 @@ typedef struct _EXT_DISPLAY_PATH }; UCHAR ucChPNInvert; // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted USHORT usCaps; - USHORT usReserved; + USHORT usReserved; }EXT_DISPLAY_PATH; - + #define NUMBER_OF_UCHAR_FOR_GUID 16 #define MAX_NUMBER_OF_EXT_DISPLAY_PATH 7 @@ -4158,7 +4158,7 @@ typedef struct _ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO ATOM_COMMON_TABLE_HEADER sHeader; UCHAR ucGuid [NUMBER_OF_UCHAR_FOR_GUID]; // a GUID is a 16 byte long string EXT_DISPLAY_PATH sPath[MAX_NUMBER_OF_EXT_DISPLAY_PATH]; // total of fixed 7 entries. - UCHAR ucChecksum; // a simple Checksum of the sum of whole structure equal to 0x0. + UCHAR ucChecksum; // a simple Checksum of the sum of whole structure equal to 0x0. UCHAR uc3DStereoPinId; // use for eDP panel UCHAR ucRemoteDisplayConfig; UCHAR uceDPToLVDSRxId; @@ -4174,7 +4174,7 @@ typedef struct _ATOM_COMMON_RECORD_HEADER }ATOM_COMMON_RECORD_HEADER; -#define ATOM_I2C_RECORD_TYPE 1 +#define ATOM_I2C_RECORD_TYPE 1 #define ATOM_HPD_INT_RECORD_TYPE 2 #define ATOM_OUTPUT_PROTECTION_RECORD_TYPE 3 #define ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE 4 @@ -4191,30 +4191,30 @@ typedef struct _ATOM_COMMON_RECORD_HEADER #define ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE 15 #define ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 16 //This is for the case when connectors are not known to object table #define ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 17 //This is for the case when connectors are not known to object table -#define ATOM_OBJECT_LINK_RECORD_TYPE 18 //Once this record is present under one object, it indicats the oobject is linked to another obj described by the record +#define ATOM_OBJECT_LINK_RECORD_TYPE 18 //Once this record is present under one object, it indicats the object is linked to another obj described by the record #define ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE 19 #define ATOM_ENCODER_CAP_RECORD_TYPE 20 #define ATOM_BRACKET_LAYOUT_RECORD_TYPE 21 -//Must be updated when new record type is added,equal to that record definition! +//Must be updated when new record type is added, equal to that record definition! #define ATOM_MAX_OBJECT_RECORD_NUMBER ATOM_BRACKET_LAYOUT_RECORD_TYPE typedef struct _ATOM_I2C_RECORD { ATOM_COMMON_RECORD_HEADER sheader; - ATOM_I2C_ID_CONFIG sucI2cId; + ATOM_I2C_ID_CONFIG sucI2cId; UCHAR ucI2CAddr; //The slave address, it's 0 when the record is attached to connector for DDC }ATOM_I2C_RECORD; typedef struct _ATOM_HPD_INT_RECORD { ATOM_COMMON_RECORD_HEADER sheader; - UCHAR ucHPDIntGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info + UCHAR ucHPDIntGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info UCHAR ucPlugged_PinState; }ATOM_HPD_INT_RECORD; -typedef struct _ATOM_OUTPUT_PROTECTION_RECORD +typedef struct _ATOM_OUTPUT_PROTECTION_RECORD { ATOM_COMMON_RECORD_HEADER sheader; UCHAR ucProtectionFlag; @@ -4262,7 +4262,7 @@ typedef struct _ATOM_ENCODER_FPGA_CONTROL_RECORD typedef struct _ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD { ATOM_COMMON_RECORD_HEADER sheader; - UCHAR ucGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info + UCHAR ucGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info UCHAR ucTVActiveState; //Indicating when the pin==0 or 1 when TV is connected }ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD; @@ -4296,18 +4296,18 @@ typedef struct _ATOM_OBJECT_GPIO_CNTL_RECORD ATOM_GPIO_PIN_CONTROL_PAIR asGpio[1]; // the real gpio pin pair determined by number of pins ucNumberOfPins }ATOM_OBJECT_GPIO_CNTL_RECORD; -//Definitions for GPIO pin state +//Definitions for GPIO pin state #define GPIO_PIN_TYPE_INPUT 0x00 #define GPIO_PIN_TYPE_OUTPUT 0x10 #define GPIO_PIN_TYPE_HW_CONTROL 0x20 -//For GPIO_PIN_TYPE_OUTPUT the following is defined +//For GPIO_PIN_TYPE_OUTPUT the following is defined #define GPIO_PIN_OUTPUT_STATE_MASK 0x01 #define GPIO_PIN_OUTPUT_STATE_SHIFT 0 #define GPIO_PIN_STATE_ACTIVE_LOW 0x0 #define GPIO_PIN_STATE_ACTIVE_HIGH 0x1 -// Indexes to GPIO array in GLSync record +// Indexes to GPIO array in GLSync record // GLSync record is for Frame Lock/Gen Lock feature. #define ATOM_GPIO_INDEX_GLSYNC_REFCLK 0 #define ATOM_GPIO_INDEX_GLSYNC_HSYNC 1 @@ -4329,26 +4329,26 @@ typedef struct _ATOM_ENCODER_DVO_CF_RECORD // Bit maps for ATOM_ENCODER_CAP_RECORD.ucEncoderCap #define ATOM_ENCODER_CAP_RECORD_HBR2 0x01 // DP1.2 HBR2 is supported by HW encoder -#define ATOM_ENCODER_CAP_RECORD_HBR2_EN 0x02 // DP1.2 HBR2 setting is qualified and HBR2 can be enabled +#define ATOM_ENCODER_CAP_RECORD_HBR2_EN 0x02 // DP1.2 HBR2 setting is qualified and HBR2 can be enabled typedef struct _ATOM_ENCODER_CAP_RECORD { ATOM_COMMON_RECORD_HEADER sheader; union { - USHORT usEncoderCap; + USHORT usEncoderCap; struct { #if ATOM_BIG_ENDIAN USHORT usReserved:14; // Bit1-15 may be defined for other capability in future USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable - USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability. + USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability. #else - USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability. + USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability. USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable USHORT usReserved:14; // Bit1-15 may be defined for other capability in future #endif }; - }; -}ATOM_ENCODER_CAP_RECORD; + }; +}ATOM_ENCODER_CAP_RECORD; // value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA 1 @@ -4380,7 +4380,7 @@ typedef struct _ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD typedef struct _ATOM_ROUTER_DDC_PATH_SELECT_RECORD { - ATOM_COMMON_RECORD_HEADER sheader; + ATOM_COMMON_RECORD_HEADER sheader; UCHAR ucMuxType; //decide the number of ucMuxState, =0, no pin state, =1: single state with complement, >1: multiple state UCHAR ucMuxControlPin; UCHAR ucMuxState[2]; //for alligment purpose @@ -4388,7 +4388,7 @@ typedef struct _ATOM_ROUTER_DDC_PATH_SELECT_RECORD typedef struct _ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD { - ATOM_COMMON_RECORD_HEADER sheader; + ATOM_COMMON_RECORD_HEADER sheader; UCHAR ucMuxType; UCHAR ucMuxControlPin; UCHAR ucMuxState[2]; //for alligment purpose @@ -4401,7 +4401,7 @@ typedef struct _ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD typedef struct _ATOM_CONNECTOR_HPDPIN_LUT_RECORD //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE { ATOM_COMMON_RECORD_HEADER sheader; - UCHAR ucHPDPINMap[MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES]; //An fixed size array which maps external pins to internal GPIO_PIN_INFO table + UCHAR ucHPDPINMap[MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES]; //An fixed size array which maps external pins to internal GPIO_PIN_INFO table }ATOM_CONNECTOR_HPDPIN_LUT_RECORD; typedef struct _ATOM_CONNECTOR_AUXDDC_LUT_RECORD //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE @@ -4447,9 +4447,9 @@ typedef struct _ATOM_BRACKET_LAYOUT_RECORD ATOM_CONNECTOR_LAYOUT_INFO asConnInfo[1]; }ATOM_BRACKET_LAYOUT_RECORD; -/****************************************************************************/ +/****************************************************************************/ // ASIC voltage data table -/****************************************************************************/ +/****************************************************************************/ typedef struct _ATOM_VOLTAGE_INFO_HEADER { USHORT usVDDCBaseLevel; //In number of 50mv unit @@ -4465,7 +4465,7 @@ typedef struct _ATOM_VOLTAGE_INFO_HEADER typedef struct _ATOM_VOLTAGE_INFO { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; ATOM_VOLTAGE_INFO_HEADER viHeader; UCHAR ucVoltageEntries[64]; //64 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries*ucBytesPerVoltageEntry }ATOM_VOLTAGE_INFO; @@ -4497,10 +4497,10 @@ typedef struct _ATOM_VOLTAGE_FORMULA_V2 typedef struct _ATOM_VOLTAGE_CONTROL { - UCHAR ucVoltageControlId; //Indicate it is controlled by I2C or GPIO or HW state machine + UCHAR ucVoltageControlId; //Indicate it is controlled by I2C or GPIO or HW state machine UCHAR ucVoltageControlI2cLine; UCHAR ucVoltageControlAddress; - UCHAR ucVoltageControlOffset; + UCHAR ucVoltageControlOffset; USHORT usGpioPin_AIndex; //GPIO_PAD register index UCHAR ucGpioPinBitShift[9]; //at most 8 pin support 255 VIDs, termintate with 0xff UCHAR ucReserved; @@ -4513,11 +4513,11 @@ typedef struct _ATOM_VOLTAGE_CONTROL #define VOLTAGE_CONTROL_ID_LM64 0x01 //I2C control, used for R5xx Core Voltage #define VOLTAGE_CONTROL_ID_DAC 0x02 //I2C control, used for R5xx/R6xx MVDDC,MVDDQ or VDDCI #define VOLTAGE_CONTROL_ID_VT116xM 0x03 //I2C control, used for R6xx Core Voltage -#define VOLTAGE_CONTROL_ID_DS4402 0x04 -#define VOLTAGE_CONTROL_ID_UP6266 0x05 +#define VOLTAGE_CONTROL_ID_DS4402 0x04 +#define VOLTAGE_CONTROL_ID_UP6266 0x05 #define VOLTAGE_CONTROL_ID_SCORPIO 0x06 -#define VOLTAGE_CONTROL_ID_VT1556M 0x07 -#define VOLTAGE_CONTROL_ID_CHL822x 0x08 +#define VOLTAGE_CONTROL_ID_VT1556M 0x07 +#define VOLTAGE_CONTROL_ID_CHL822x 0x08 #define VOLTAGE_CONTROL_ID_VT1586M 0x09 #define VOLTAGE_CONTROL_ID_UP1637 0x0A #define VOLTAGE_CONTROL_ID_CHL8214 0x0B @@ -4530,30 +4530,30 @@ typedef struct _ATOM_VOLTAGE_CONTROL typedef struct _ATOM_VOLTAGE_OBJECT { - UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI - UCHAR ucSize; //Size of Object - ATOM_VOLTAGE_CONTROL asControl; //describ how to control - ATOM_VOLTAGE_FORMULA asFormula; //Indicate How to convert real Voltage to VID + UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI + UCHAR ucSize; //Size of Object + ATOM_VOLTAGE_CONTROL asControl; //describ how to control + ATOM_VOLTAGE_FORMULA asFormula; //Indicate How to convert real Voltage to VID }ATOM_VOLTAGE_OBJECT; typedef struct _ATOM_VOLTAGE_OBJECT_V2 { - UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI - UCHAR ucSize; //Size of Object - ATOM_VOLTAGE_CONTROL asControl; //describ how to control - ATOM_VOLTAGE_FORMULA_V2 asFormula; //Indicate How to convert real Voltage to VID + UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI + UCHAR ucSize; //Size of Object + ATOM_VOLTAGE_CONTROL asControl; //describ how to control + ATOM_VOLTAGE_FORMULA_V2 asFormula; //Indicate How to convert real Voltage to VID }ATOM_VOLTAGE_OBJECT_V2; typedef struct _ATOM_VOLTAGE_OBJECT_INFO { - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_VOLTAGE_OBJECT asVoltageObj[3]; //Info for Voltage control + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_VOLTAGE_OBJECT asVoltageObj[3]; //Info for Voltage control }ATOM_VOLTAGE_OBJECT_INFO; typedef struct _ATOM_VOLTAGE_OBJECT_INFO_V2 { - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_VOLTAGE_OBJECT_V2 asVoltageObj[3]; //Info for Voltage control + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_VOLTAGE_OBJECT_V2 asVoltageObj[3]; //Info for Voltage control }ATOM_VOLTAGE_OBJECT_INFO_V2; typedef struct _ATOM_LEAKID_VOLTAGE @@ -4564,9 +4564,9 @@ typedef struct _ATOM_LEAKID_VOLTAGE }ATOM_LEAKID_VOLTAGE; typedef struct _ATOM_VOLTAGE_OBJECT_HEADER_V3{ - UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI - UCHAR ucVoltageMode; //Indicate voltage control mode: Init/Set/Leakage/Set phase - USHORT usSize; //Size of Object + UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI + UCHAR ucVoltageMode; //Indicate voltage control mode: Init/Set/Leakage/Set phase + USHORT usSize; //Size of Object }ATOM_VOLTAGE_OBJECT_HEADER_V3; // ATOM_VOLTAGE_OBJECT_HEADER_V3.ucVoltageMode @@ -4574,7 +4574,7 @@ typedef struct _ATOM_VOLTAGE_OBJECT_HEADER_V3{ #define VOLTAGE_OBJ_VR_I2C_INIT_SEQ 3 //VOLTAGE REGULATOR INIT sequece through I2C -> ATOM_I2C_VOLTAGE_OBJECT_V3 #define VOLTAGE_OBJ_PHASE_LUT 4 //Set Vregulator Phase lookup table ->ATOM_GPIO_VOLTAGE_OBJECT_V3 #define VOLTAGE_OBJ_SVID2 7 //Indicate voltage control by SVID2 ->ATOM_SVID2_VOLTAGE_OBJECT_V3 -#define VOLTAGE_OBJ_EVV 8 +#define VOLTAGE_OBJ_EVV 8 #define VOLTAGE_OBJ_PWRBOOST_LEAKAGE_LUT 0x10 //Powerboost Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 #define VOLTAGE_OBJ_HIGH_STATE_LEAKAGE_LUT 0x11 //High voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 #define VOLTAGE_OBJ_HIGH1_STATE_LEAKAGE_LUT 0x12 //High1 voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 @@ -4588,7 +4588,7 @@ typedef struct _VOLTAGE_LUT_ENTRY_V2 typedef struct _LEAKAGE_VOLTAGE_LUT_ENTRY_V2 { USHORT usVoltageLevel; // The Voltage ID which is used to program GPIO register - USHORT usVoltageId; + USHORT usVoltageId; USHORT usLeakageId; // The corresponding Voltage Value, in mV }LEAKAGE_VOLTAGE_LUT_ENTRY_V2; @@ -4598,7 +4598,7 @@ typedef struct _ATOM_I2C_VOLTAGE_OBJECT_V3 UCHAR ucVoltageRegulatorId; //Indicate Voltage Regulator Id UCHAR ucVoltageControlI2cLine; UCHAR ucVoltageControlAddress; - UCHAR ucVoltageControlOffset; + UCHAR ucVoltageControlOffset; ULONG ulReserved; VOLTAGE_LUT_ENTRY asVolI2cLut[1]; // end with 0xff }ATOM_I2C_VOLTAGE_OBJECT_V3; @@ -4610,12 +4610,12 @@ typedef struct _ATOM_I2C_VOLTAGE_OBJECT_V3 typedef struct _ATOM_GPIO_VOLTAGE_OBJECT_V3 { ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_GPIO_LUT or VOLTAGE_OBJ_PHASE_LUT - UCHAR ucVoltageGpioCntlId; // default is 0 which indicate control through CG VID mode - UCHAR ucGpioEntryNum; // indiate the entry numbers of Votlage/Gpio value Look up table + UCHAR ucVoltageGpioCntlId; // default is 0 which indicate control through CG VID mode + UCHAR ucGpioEntryNum; // indicate the entry numbers of Voltage/Gpio value Look up table UCHAR ucPhaseDelay; // phase delay in unit of micro second - UCHAR ucReserved; + UCHAR ucReserved; ULONG ulGpioMaskVal; // GPIO Mask value - VOLTAGE_LUT_ENTRY_V2 asVolGpioLut[1]; + VOLTAGE_LUT_ENTRY_V2 asVolGpioLut[1]; }ATOM_GPIO_VOLTAGE_OBJECT_V3; typedef struct _ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 @@ -4623,9 +4623,9 @@ typedef struct _ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = 0x10/0x11/0x12 UCHAR ucLeakageCntlId; // default is 0 UCHAR ucLeakageEntryNum; // indicate the entry number of LeakageId/Voltage Lut table - UCHAR ucReserved[2]; + UCHAR ucReserved[2]; ULONG ulMaxVoltageLevel; - LEAKAGE_VOLTAGE_LUT_ENTRY_V2 asLeakageIdLut[1]; + LEAKAGE_VOLTAGE_LUT_ENTRY_V2 asLeakageIdLut[1]; }ATOM_LEAKAGE_VOLTAGE_OBJECT_V3; @@ -4635,9 +4635,9 @@ typedef struct _ATOM_SVID2_VOLTAGE_OBJECT_V3 // 14:7 – PSI0_VID // 6 – PSI0_EN // 5 – PSI1 -// 4:2 – load line slope trim. -// 1:0 – offset trim, - USHORT usLoadLine_PSI; +// 4:2 – load line slope trim. +// 1:0 – offset trim, + USHORT usLoadLine_PSI; // GPU GPIO pin Id to SVID2 regulator VRHot pin. possible value 0~31. 0 means GPIO0, 31 means GPIO31 UCHAR ucSVDGpioId; //0~31 indicate GPIO0~31 UCHAR ucSVCGpioId; //0~31 indicate GPIO0~31 @@ -4653,8 +4653,8 @@ typedef union _ATOM_VOLTAGE_OBJECT_V3{ typedef struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 { - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_VOLTAGE_OBJECT_V3 asVoltageObj[3]; //Info for Voltage control + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_VOLTAGE_OBJECT_V3 asVoltageObj[3]; //Info for Voltage control }ATOM_VOLTAGE_OBJECT_INFO_V3_1; typedef struct _ATOM_ASIC_PROFILE_VOLTAGE @@ -4663,28 +4663,28 @@ typedef struct _ATOM_ASIC_PROFILE_VOLTAGE UCHAR ucReserved; USHORT usSize; USHORT usEfuseSpareStartAddr; - USHORT usFuseIndex[8]; //from LSB to MSB, Max 8bit,end of 0xffff if less than 8 efuse id, + USHORT usFuseIndex[8]; //from LSB to MSB, Max 8bit,end of 0xffff if less than 8 efuse id, ATOM_LEAKID_VOLTAGE asLeakVol[2]; //Leakid and relatd voltage }ATOM_ASIC_PROFILE_VOLTAGE; //ucProfileId -#define ATOM_ASIC_PROFILE_ID_EFUSE_VOLTAGE 1 +#define ATOM_ASIC_PROFILE_ID_EFUSE_VOLTAGE 1 #define ATOM_ASIC_PROFILE_ID_EFUSE_PERFORMANCE_VOLTAGE 1 #define ATOM_ASIC_PROFILE_ID_EFUSE_THERMAL_VOLTAGE 2 typedef struct _ATOM_ASIC_PROFILING_INFO { - ATOM_COMMON_TABLE_HEADER asHeader; + ATOM_COMMON_TABLE_HEADER asHeader; ATOM_ASIC_PROFILE_VOLTAGE asVoltage; }ATOM_ASIC_PROFILING_INFO; typedef struct _ATOM_ASIC_PROFILING_INFO_V2_1 { - ATOM_COMMON_TABLE_HEADER asHeader; + ATOM_COMMON_TABLE_HEADER asHeader; UCHAR ucLeakageBinNum; // indicate the entry number of LeakageId/Voltage Lut table - USHORT usLeakageBinArrayOffset; // offset of USHORT Leakage Bin list array ( from lower LeakageId to higher) + USHORT usLeakageBinArrayOffset; // offset of USHORT Leakage Bin list array ( from lower LeakageId to higher) - UCHAR ucElbVDDC_Num; + UCHAR ucElbVDDC_Num; USHORT usElbVDDC_IdArrayOffset; // offset of USHORT virtual VDDC voltage id ( 0xff01~0xff08 ) USHORT usElbVDDC_LevelArrayOffset; // offset of 2 dimension voltage level USHORT array @@ -4695,7 +4695,7 @@ typedef struct _ATOM_ASIC_PROFILING_INFO_V2_1 typedef struct _ATOM_ASIC_PROFILING_INFO_V3_1 { - ATOM_COMMON_TABLE_HEADER asHeader; + ATOM_COMMON_TABLE_HEADER asHeader; ULONG ulEvvDerateTdp; ULONG ulEvvDerateTdc; ULONG ulBoardCoreTemp; @@ -4745,7 +4745,7 @@ typedef struct _ATOM_POWER_SOURCE_OBJECT UCHAR ucPwrSensRegIndex; // I2C register Index if I2C detect UCHAR ucPwrSensRegBitMask; // detect which bit is used if I2C detect UCHAR ucPwrSensActiveState; // high active or low active - UCHAR ucReserve[3]; // reserve + UCHAR ucReserve[3]; // reserve USHORT usSensPwr; // in unit of watt }ATOM_POWER_SOURCE_OBJECT; @@ -4771,15 +4771,15 @@ typedef struct _ATOM_POWER_SOURCE_INFO typedef struct _ATOM_CLK_VOLT_CAPABILITY { - ULONG ulVoltageIndex; // The Voltage Index indicated by FUSE, same voltage index shared with SCLK DPM fuse table + ULONG ulVoltageIndex; // The Voltage Index indicated by FUSE, same voltage index shared with SCLK DPM fuse table ULONG ulMaximumSupportedCLK; // Maximum clock supported with specified voltage index, unit in 10kHz }ATOM_CLK_VOLT_CAPABILITY; typedef struct _ATOM_AVAILABLE_SCLK_LIST { ULONG ulSupportedSCLK; // Maximum clock supported with specified voltage index, unit in 10kHz - USHORT usVoltageIndex; // The Voltage Index indicated by FUSE for specified SCLK - USHORT usVoltageID; // The Voltage ID indicated by FUSE for specified SCLK + USHORT usVoltageIndex; // The Voltage Index indicated by FUSE for specified SCLK + USHORT usVoltageID; // The Voltage ID indicated by FUSE for specified SCLK }ATOM_AVAILABLE_SCLK_LIST; // ATOM_INTEGRATED_SYSTEM_INFO_V6 ulSystemConfig cap definition @@ -4790,28 +4790,28 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 { ATOM_COMMON_TABLE_HEADER sHeader; ULONG ulBootUpEngineClock; - ULONG ulDentistVCOFreq; - ULONG ulBootUpUMAClock; - ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; + ULONG ulDentistVCOFreq; + ULONG ulBootUpUMAClock; + ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; ULONG ulBootUpReqDisplayVector; ULONG ulOtherDisplayMisc; ULONG ulGPUCapInfo; ULONG ulSB_MMIO_Base_Addr; USHORT usRequestedPWMFreqInHz; - UCHAR ucHtcTmpLmt; + UCHAR ucHtcTmpLmt; UCHAR ucHtcHystLmt; - ULONG ulMinEngineClock; - ULONG ulSystemConfig; - ULONG ulCPUCapInfo; - USHORT usNBP0Voltage; + ULONG ulMinEngineClock; + ULONG ulSystemConfig; + ULONG ulCPUCapInfo; + USHORT usNBP0Voltage; USHORT usNBP1Voltage; - USHORT usBootUpNBVoltage; + USHORT usBootUpNBVoltage; USHORT usExtDispConnInfoOffset; - USHORT usPanelRefreshRateRange; - UCHAR ucMemoryType; + USHORT usPanelRefreshRateRange; + UCHAR ucMemoryType; UCHAR ucUMAChannelNumber; - ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10]; - ULONG ulCSR_M3_ARB_CNTL_UVD[10]; + ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10]; + ULONG ulCSR_M3_ARB_CNTL_UVD[10]; ULONG ulCSR_M3_ARB_CNTL_FS3D[10]; ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; ULONG ulGMCRestoreResetTime; @@ -4829,24 +4829,24 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 USHORT usDVISSpreadRateIn10Hz; ULONG SclkDpmBoostMargin; ULONG SclkDpmThrottleMargin; - USHORT SclkDpmTdpLimitPG; + USHORT SclkDpmTdpLimitPG; USHORT SclkDpmTdpLimitBoost; ULONG ulBoostEngineCLock; - UCHAR ulBoostVid_2bit; + UCHAR ulBoostVid_2bit; UCHAR EnableBoost; USHORT GnbTdpLimit; USHORT usMaxLVDSPclkFreqInSingleLink; UCHAR ucLvdsMisc; UCHAR ucLVDSReserved; - ULONG ulReserved3[15]; - ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; -}ATOM_INTEGRATED_SYSTEM_INFO_V6; + ULONG ulReserved3[15]; + ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; +}ATOM_INTEGRATED_SYSTEM_INFO_V6; // ulGPUCapInfo #define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__TMDSHDMI_COHERENT_SINGLEPLL_MODE 0x01 #define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__DISABLE_AUX_HW_MODE_DETECTION 0x08 -//ucLVDSMisc: +//ucLVDSMisc: #define SYS_INFO_LVDSMISC__888_FPDI_MODE 0x01 #define SYS_INFO_LVDSMISC__DL_CH_SWAP 0x02 #define SYS_INFO_LVDSMISC__888_BPC 0x04 @@ -4862,57 +4862,57 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 /********************************************************************************************************************** ATOM_INTEGRATED_SYSTEM_INFO_V6 Description ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock -ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. -ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. +ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. +ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. sDISPCLK_Voltage: Report Display clock voltage requirement. - + ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Liano/Ontaio projects: ATOM_DEVICE_CRT1_SUPPORT 0x0001 ATOM_DEVICE_CRT2_SUPPORT 0x0010 - ATOM_DEVICE_DFP1_SUPPORT 0x0008 - ATOM_DEVICE_DFP6_SUPPORT 0x0040 - ATOM_DEVICE_DFP2_SUPPORT 0x0080 - ATOM_DEVICE_DFP3_SUPPORT 0x0200 - ATOM_DEVICE_DFP4_SUPPORT 0x0400 + ATOM_DEVICE_DFP1_SUPPORT 0x0008 + ATOM_DEVICE_DFP6_SUPPORT 0x0040 + ATOM_DEVICE_DFP2_SUPPORT 0x0080 + ATOM_DEVICE_DFP3_SUPPORT 0x0200 + ATOM_DEVICE_DFP4_SUPPORT 0x0400 ATOM_DEVICE_DFP5_SUPPORT 0x0800 ATOM_DEVICE_LCD1_SUPPORT 0x0002 -ulOtherDisplayMisc: Other display related flags, not defined yet. +ulOtherDisplayMisc: Other display related flags, not defined yet. ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode. =1: TMDS/HDMI Coherent Mode use signel PLL mode. bit[3]=0: Enable HW AUX mode detection logic =1: Disable HW AUX mode dettion logic ulSB_MMIO_Base_Addr: Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage. -usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). +usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0; - + When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below: 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use; VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result, - Changing BL using VBIOS function is functional in both driver and non-driver present environment; + Changing BL using VBIOS function is functional in both driver and non-driver present environment; and enabling VariBri under the driver environment from PP table is optional. 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating that BL control from GPU is expected. VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1 Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but - it's per platform + it's per platform and enabling VariBri under the driver environment from PP table is optional. -ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. +ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. Threshold on value to enter HTC_active state. -ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. +ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt. ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings. -ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled +ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled =1: PCIE Power Gating Enabled Bit[1]=0: DDR-DLL shut-down feature disabled. 1: DDR-DLL shut-down feature enabled. Bit[2]=0: DDR-PLL Power down feature disabled. - 1: DDR-PLL Power down feature enabled. + 1: DDR-PLL Power down feature enabled. ulCPUCapInfo: TBD usNBP0Voltage: VID for voltage on NB P0 State -usNBP1Voltage: VID for voltage on NB P1 State +usNBP1Voltage: VID for voltage on NB P1 State usBootUpNBVoltage: Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement. usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set @@ -4922,24 +4922,24 @@ usPanelRefreshRateRange: Bit vector for LCD supported refresh rate rang SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved. -ucUMAChannelNumber: System memory channel numbers. +ucUMAChannelNumber: System memory channel numbers. ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback. ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications. -sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high -ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. -ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz. +sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high +ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. +ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz. ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz. ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns. usPCIEClkSSPercentage: PCIE Clock Spred Spectrum Percentage in unit 0.01%; 100 mean 1%. usPCIEClkSSType: PCIE Clock Spred Spectrum Type. 0 for Down spread(default); 1 for Center spread. -usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. -usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. -usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. -usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. -usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. -usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. +usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. +usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. +usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. +usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. +usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. +usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped @@ -4951,9 +4951,9 @@ ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 pan // this Table is used for Liano/Ontario APU typedef struct _ATOM_FUSION_SYSTEM_INFO_V1 { - ATOM_INTEGRATED_SYSTEM_INFO_V6 sIntegratedSysInfo; - ULONG ulPowerplayTable[128]; -}ATOM_FUSION_SYSTEM_INFO_V1; + ATOM_INTEGRATED_SYSTEM_INFO_V6 sIntegratedSysInfo; + ULONG ulPowerplayTable[128]; +}ATOM_FUSION_SYSTEM_INFO_V1; typedef struct _ATOM_TDP_CONFIG_BITS @@ -4980,8 +4980,8 @@ typedef union _ATOM_TDP_CONFIG /********************************************************************************************************************** ATOM_FUSION_SYSTEM_INFO_V1 Description sIntegratedSysInfo: refer to ATOM_INTEGRATED_SYSTEM_INFO_V6 definition. -ulPowerplayTable[128]: This 512 bytes memory is used to save ATOM_PPLIB_POWERPLAYTABLE3, starting form ulPowerplayTable[0] -**********************************************************************************************************************/ +ulPowerplayTable[128]: This 512 bytes memory is used to save ATOM_PPLIB_POWERPLAYTABLE3, starting form ulPowerplayTable[0] +**********************************************************************************************************************/ // this IntegrateSystemInfoTable is used for Trinity APU typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 @@ -4999,14 +4999,14 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 UCHAR ucHtcTmpLmt; UCHAR ucHtcHystLmt; ULONG ulMinEngineClock; - ULONG ulSystemConfig; + ULONG ulSystemConfig; ULONG ulCPUCapInfo; - USHORT usNBP0Voltage; + USHORT usNBP0Voltage; USHORT usNBP1Voltage; - USHORT usBootUpNBVoltage; + USHORT usBootUpNBVoltage; USHORT usExtDispConnInfoOffset; - USHORT usPanelRefreshRateRange; - UCHAR ucMemoryType; + USHORT usPanelRefreshRateRange; + UCHAR ucMemoryType; UCHAR ucUMAChannelNumber; UCHAR strVBIOSMsg[40]; ATOM_TDP_CONFIG asTdpConfig; @@ -5027,10 +5027,10 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 USHORT usDVISSpreadRateIn10Hz; ULONG SclkDpmBoostMargin; ULONG SclkDpmThrottleMargin; - USHORT SclkDpmTdpLimitPG; + USHORT SclkDpmTdpLimitPG; USHORT SclkDpmTdpLimitBoost; ULONG ulBoostEngineCLock; - UCHAR ulBoostVid_2bit; + UCHAR ulBoostVid_2bit; UCHAR EnableBoost; USHORT GnbTdpLimit; USHORT usMaxLVDSPclkFreqInSingleLink; @@ -5046,7 +5046,7 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 UCHAR ucMinAllowedBL_Level; ULONG ulLCDBitDepthControlVal; ULONG ulNbpStateMemclkFreq[4]; - USHORT usNBP2Voltage; + USHORT usNBP2Voltage; USHORT usNBP3Voltage; ULONG ulNbpStateNClkFreq[4]; UCHAR ucNBDPMEnable; @@ -5077,21 +5077,21 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 /********************************************************************************************************************** ATOM_INTEGRATED_SYSTEM_INFO_V1_7 Description ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock -ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. -ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. +ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. +ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. sDISPCLK_Voltage: Report Display clock voltage requirement. - + ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Trinity projects: ATOM_DEVICE_CRT1_SUPPORT 0x0001 - ATOM_DEVICE_DFP1_SUPPORT 0x0008 - ATOM_DEVICE_DFP6_SUPPORT 0x0040 - ATOM_DEVICE_DFP2_SUPPORT 0x0080 - ATOM_DEVICE_DFP3_SUPPORT 0x0200 - ATOM_DEVICE_DFP4_SUPPORT 0x0400 + ATOM_DEVICE_DFP1_SUPPORT 0x0008 + ATOM_DEVICE_DFP6_SUPPORT 0x0040 + ATOM_DEVICE_DFP2_SUPPORT 0x0080 + ATOM_DEVICE_DFP3_SUPPORT 0x0200 + ATOM_DEVICE_DFP4_SUPPORT 0x0400 ATOM_DEVICE_DFP5_SUPPORT 0x0800 ATOM_DEVICE_LCD1_SUPPORT 0x0002 -ulOtherDisplayMisc: bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS. - =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS. +ulOtherDisplayMisc: bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS. + =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS. bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS =1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS @@ -5104,42 +5104,42 @@ ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade =1: DP mode use single PLL mode bit[3]=0: Enable AUX HW mode detection logic =1: Disable AUX HW mode detection logic - + ulSB_MMIO_Base_Addr: Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage. -usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). +usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0; - + When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below: 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use; VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result, - Changing BL using VBIOS function is functional in both driver and non-driver present environment; + Changing BL using VBIOS function is functional in both driver and non-driver present environment; and enabling VariBri under the driver environment from PP table is optional. 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating that BL control from GPU is expected. VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1 Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but - it's per platform + it's per platform and enabling VariBri under the driver environment from PP table is optional. -ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. +ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. Threshold on value to enter HTC_active state. -ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. +ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt. ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings. -ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled +ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled =1: PCIE Power Gating Enabled Bit[1]=0: DDR-DLL shut-down feature disabled. 1: DDR-DLL shut-down feature enabled. Bit[2]=0: DDR-PLL Power down feature disabled. - 1: DDR-PLL Power down feature enabled. + 1: DDR-PLL Power down feature enabled. ulCPUCapInfo: TBD usNBP0Voltage: VID for voltage on NB P0 State -usNBP1Voltage: VID for voltage on NB P1 State +usNBP1Voltage: VID for voltage on NB P1 State usNBP2Voltage: VID for voltage on NB P2 State -usNBP3Voltage: VID for voltage on NB P3 State -usBootUpNBVoltage: Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement. +usNBP3Voltage: VID for voltage on NB P3 State +usBootUpNBVoltage: Voltage Index of GNB voltage configured by SBIOS, which is sufficient to support VBIOS DISPCLK requirement. usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set to indicate a range. @@ -5148,24 +5148,24 @@ usPanelRefreshRateRange: Bit vector for LCD supported refresh rate rang SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved. -ucUMAChannelNumber: System memory channel numbers. +ucUMAChannelNumber: System memory channel numbers. ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback. ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications. -sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high -ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. -ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz. +sAvail_SCLK[5]: Arrays to provide available list of SLCK and corresponding voltage, order from low to high +ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. +ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calculate data reconnection latency. Unit in 10kHz. ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz. ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns. usPCIEClkSSPercentage: PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%. usPCIEClkSSType: PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread. -usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. -usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. -usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. -usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. -usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. -usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. +usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. +usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. +usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. +usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. +usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. +usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped @@ -5173,40 +5173,40 @@ ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 pan [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low ) [bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to overwrite Traivs register LVDS_CTRL_4 -ucTravisLVDSVolAdjust When ucLVDSMisc[5]=1,it means platform SBIOS want to overwrite TravisLVDSVoltage. Then VBIOS will use ucTravisLVDSVolAdjust +ucTravisLVDSVolAdjust When ucLVDSMisc[5]=1,it means platform SBIOS want to overwrite TravisLVDSVoltage. Then VBIOS will use ucTravisLVDSVolAdjust value to program Travis register LVDS_CTRL_4 ucLVDSPwrOnSeqDIGONtoDE_in4Ms: LVDS power up sequence time in unit of 4ms, time delay from DIGON signal active to data enable signal active( DE ). - =0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. + =0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. -ucLVDSPwrOnDEtoVARY_BL_in4Ms: LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable signal active( VARY_BL ). - =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. +ucLVDSPwrOnDEtoVARY_BL_in4Ms: LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable signal active( VARY_BL ). + =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. -ucLVDSPwrOffVARY_BLtoDE_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCDVCC (DIGON) off. +ucLVDSPwrOffVARY_BLtoDE_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCDVCC (DIGON) off. =0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. -ucLVDSPwrOffDEtoDIGON_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable ( DE ) signal off. +ucLVDSPwrOffDEtoDIGON_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable ( DE ) signal off. =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. -ucLVDSOffToOnDelay_in4Ms: LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal active. +ucLVDSOffToOnDelay_in4Ms: LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal active. =0 means to use VBIOS default delay which is 125 ( 500ms ). This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms: - LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active. + LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active. =0 means to use VBIOS default delay which is 0 ( 0ms ). This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. -ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms: - LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off. +ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms: + LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off. =0 means to use VBIOS default delay which is 0 ( 0ms ). This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. -ucMinAllowedBL_Level: Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0. +ucMinAllowedBL_Level: Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0. -ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB pstate. +ulNbpStateMemclkFreq[4]: system memory clock frequency in unit of 10Khz in different NB pstate. **********************************************************************************************************************/ @@ -5226,13 +5226,13 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 UCHAR ucHtcTmpLmt; UCHAR ucHtcHystLmt; ULONG ulReserved2; - ULONG ulSystemConfig; + ULONG ulSystemConfig; ULONG ulCPUCapInfo; ULONG ulReserved3; USHORT usGPUReservedSysMemSize; USHORT usExtDispConnInfoOffset; - USHORT usPanelRefreshRateRange; - UCHAR ucMemoryType; + USHORT usPanelRefreshRateRange; + UCHAR ucMemoryType; UCHAR ucUMAChannelNumber; UCHAR strVBIOSMsg[40]; ATOM_TDP_CONFIG asTdpConfig; @@ -5267,21 +5267,21 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 UCHAR ucMinAllowedBL_Level; ULONG ulLCDBitDepthControlVal; ULONG ulNbpStateMemclkFreq[4]; - ULONG ulReserved6; + ULONG ulReserved6; ULONG ulNbpStateNClkFreq[4]; - USHORT usNBPStateVoltage[4]; - USHORT usBootUpNBVoltage; - USHORT usReserved2; + USHORT usNBPStateVoltage[4]; + USHORT usBootUpNBVoltage; + USHORT usReserved2; ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; }ATOM_INTEGRATED_SYSTEM_INFO_V1_8; /********************************************************************************************************************** ATOM_INTEGRATED_SYSTEM_INFO_V1_8 Description ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock -ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. -ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. +ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. +ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. sDISPCLK_Voltage: Report Display clock frequency requirement on GNB voltage(up to 4 voltage levels). - + ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Trinity projects: ATOM_DEVICE_CRT1_SUPPORT 0x0001 ATOM_DEVICE_DFP1_SUPPORT 0x0008 @@ -5292,8 +5292,8 @@ ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are suppo ATOM_DEVICE_DFP5_SUPPORT 0x0800 ATOM_DEVICE_LCD1_SUPPORT 0x0002 -ulVBIOSMisc: Miscellenous flags for VBIOS requirement and interface - bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS. +ulVBIOSMisc: Miscellenous flags for VBIOS requirement and interface + bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS. =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS. bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS =1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS @@ -5308,38 +5308,38 @@ ulGPUCapInfo: bit[0~2]= Reserved bit[4]=0: Disable DFS bypass feature =1: Enable DFS bypass feature -usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). +usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0; - + When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below: - 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use; + 1. SW uses the GPU BL PWM output to control the BL, in this case, this non-zero frequency determines what freq GPU should use; VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result, - Changing BL using VBIOS function is functional in both driver and non-driver present environment; + Changing BL using VBIOS function is functional in both driver and non-driver present environment; and enabling VariBri under the driver environment from PP table is optional. 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating that BL control from GPU is expected. VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1 Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but - it's per platform + it's per platform and enabling VariBri under the driver environment from PP table is optional. ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. Threshold on value to enter HTC_active state. -ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. - To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt. +ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. + To calculate threshold off value to exit HTC_active state, which is Threshold on value minus ucHtcHystLmt. -ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled +ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled =1: PCIE Power Gating Enabled Bit[1]=0: DDR-DLL shut-down feature disabled. 1: DDR-DLL shut-down feature enabled. Bit[2]=0: DDR-PLL Power down feature disabled. - 1: DDR-PLL Power down feature enabled. + 1: DDR-PLL Power down feature enabled. Bit[3]=0: GNB DPM is disabled - =1: GNB DPM is enabled + =1: GNB DPM is enabled ulCPUCapInfo: TBD usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure -usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set +usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requested by the platform, at least two bits need to be set to indicate a range. SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 @@ -5347,29 +5347,29 @@ usPanelRefreshRateRange: Bit vector for LCD supported refresh rate rang SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3;=5:GDDR5; [7:4] is reserved. -ucUMAChannelNumber: System memory channel numbers. +ucUMAChannelNumber: System memory channel numbers. -strVBIOSMsg[40]: VBIOS boot up customized message string +strVBIOSMsg[40]: VBIOS boot up customized message string -sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high +sAvail_SCLK[5]: Arrays to provide available list of SLCK and corresponding voltage, order from low to high -ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. +ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. ulIdleNClk: NCLK speed while memory runs in self-refresh state, used to calculate self-refresh latency. Unit in 10kHz. ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns. usPCIEClkSSPercentage: PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%. usPCIEClkSSType: PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread. -usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. -usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. -usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. -usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. -usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. -usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. +usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. +usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. +usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. +usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. +usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. +usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. usGPUReservedSysMemSize: Reserved system memory size for ACP engine in APU GNB, units in MB. 0/2/4MB based on CMOS options, current default could be 0MB. KV only, not on KB. -ulGPUReservedSysMemBaseAddrLo: Low 32 bits base address to the reserved system memory. -ulGPUReservedSysMemBaseAddrHi: High 32 bits base address to the reserved system memory. +ulGPUReservedSysMemBaseAddrLo: Low 32 bits base address to the reserved system memory. +ulGPUReservedSysMemBaseAddrHi: High 32 bits base address to the reserved system memory. usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode @@ -5378,45 +5378,45 @@ ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 pan [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low ) [bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to overwrite Traivs register LVDS_CTRL_4 -ucTravisLVDSVolAdjust When ucLVDSMisc[5]=1,it means platform SBIOS want to overwrite TravisLVDSVoltage. Then VBIOS will use ucTravisLVDSVolAdjust +ucTravisLVDSVolAdjust When ucLVDSMisc[5]=1,it means platform SBIOS want to overwrite TravisLVDSVoltage. Then VBIOS will use ucTravisLVDSVolAdjust value to program Travis register LVDS_CTRL_4 -ucLVDSPwrOnSeqDIGONtoDE_in4Ms: +ucLVDSPwrOnSeqDIGONtoDE_in4Ms: LVDS power up sequence time in unit of 4ms, time delay from DIGON signal active to data enable signal active( DE ). - =0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. + =0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. -ucLVDSPwrOnDEtoVARY_BL_in4Ms: - LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable signal active( VARY_BL ). - =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. +ucLVDSPwrOnDEtoVARY_BL_in4Ms: + LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable signal active( VARY_BL ). + =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. -ucLVDSPwrOffVARY_BLtoDE_in4Ms: - LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCDVCC (DIGON) off. +ucLVDSPwrOffVARY_BLtoDE_in4Ms: + LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCDVCC (DIGON) off. =0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. -ucLVDSPwrOffDEtoDIGON_in4Ms: - LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable ( DE ) signal off. +ucLVDSPwrOffDEtoDIGON_in4Ms: + LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable ( DE ) signal off. =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. -ucLVDSOffToOnDelay_in4Ms: - LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal active. +ucLVDSOffToOnDelay_in4Ms: + LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal active. =0 means to use VBIOS default delay which is 125 ( 500ms ). This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms: - LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active. + LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active. =0 means to use VBIOS default delay which is 0 ( 0ms ). This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. -ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms: - LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off. +ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms: + LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off. =0 means to use VBIOS default delay which is 0 ( 0ms ). This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. -ucMinAllowedBL_Level: Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0. +ucMinAllowedBL_Level: Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0. ulLCDBitDepthControlVal: GPU display control encoder bit dither control setting, used to program register mmFMT_BIT_DEPTH_CONTROL ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB P-State(P0, P1, P2 & P3). ulNbpStateNClkFreq[4]: NB P-State NClk frequency in different NB P-State usNBPStateVoltage[4]: NB P-State (P0/P1 & P2/P3) voltage; NBP3 refers to lowes voltage -usBootUpNBVoltage: NB P-State voltage during boot up before driver loaded +usBootUpNBVoltage: NB P-State voltage during boot up before driver loaded sExtDispConnInfo: Display connector information table provided to VBIOS **********************************************************************************************************************/ @@ -5426,7 +5426,7 @@ typedef struct _ATOM_FUSION_SYSTEM_INFO_V2 { ATOM_INTEGRATED_SYSTEM_INFO_V1_8 sIntegratedSysInfo; // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition ULONG ulPowerplayTable[128]; // Update comments here to link new powerplay table definition structure -}ATOM_FUSION_SYSTEM_INFO_V2; +}ATOM_FUSION_SYSTEM_INFO_V2; /**************************************************************************/ @@ -5451,13 +5451,13 @@ typedef struct _ATOM_I2C_DEVICE_SETUP_INFO UCHAR ucSSChipID; //SS chip being used UCHAR ucSSChipSlaveAddr; //Slave Address to set up this SS chip UCHAR ucNumOfI2CDataRecords; //number of data block - ATOM_I2C_DATA_RECORD asI2CData[1]; + ATOM_I2C_DATA_RECORD asI2CData[1]; }ATOM_I2C_DEVICE_SETUP_INFO; //========================================================================================== typedef struct _ATOM_ASIC_MVDD_INFO { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; ATOM_I2C_DEVICE_SETUP_INFO asI2CSetup[1]; }ATOM_ASIC_MVDD_INFO; @@ -5513,14 +5513,14 @@ typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V2 typedef struct _ATOM_ASIC_INTERNAL_SS_INFO { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; ATOM_ASIC_SS_ASSIGNMENT asSpreadSpectrum[4]; }ATOM_ASIC_INTERNAL_SS_INFO; typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 { - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_ASIC_SS_ASSIGNMENT_V2 asSpreadSpectrum[1]; //this is point only. + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_ASIC_SS_ASSIGNMENT_V2 asSpreadSpectrum[1]; //this is point only. }ATOM_ASIC_INTERNAL_SS_INFO_V2; typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V3 @@ -5541,8 +5541,8 @@ typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V3 typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 { - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_ASIC_SS_ASSIGNMENT_V3 asSpreadSpectrum[1]; //this is pointer only. + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_ASIC_SS_ASSIGNMENT_V3 asSpreadSpectrum[1]; //this is pointer only. }ATOM_ASIC_INTERNAL_SS_INFO_V3; @@ -5559,7 +5559,7 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 #define ATOM_I2C_CHANNEL_STATUS1_DEF 9 #define ATOM_INTERNAL_TIMER_DEF 10 -// BIOS_0_SCRATCH Definition +// BIOS_0_SCRATCH Definition #define ATOM_S0_CRT1_MONO 0x00000001L #define ATOM_S0_CRT1_COLOR 0x00000002L #define ATOM_S0_CRT1_MASK (ATOM_S0_CRT1_MONO+ATOM_S0_CRT1_COLOR) @@ -5597,14 +5597,14 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 #define ATOM_S0_DFP_MASK ATOM_S0_DFP1 | ATOM_S0_DFP2 | ATOM_S0_DFP3 | ATOM_S0_DFP4 | ATOM_S0_DFP5 | ATOM_S0_DFP6 -#define ATOM_S0_FAD_REGISTER_BUG 0x02000000L // If set, indicates we are running a PCIE asic with +#define ATOM_S0_FAD_REGISTER_BUG 0x02000000L // If set, indicates we are running a PCIE asic with // the FAD/HDP reg access bug. Bit is read by DAL, this is obsolete from RV5xx #define ATOM_S0_THERMAL_STATE_MASK 0x1C000000L #define ATOM_S0_THERMAL_STATE_SHIFT 26 #define ATOM_S0_SYSTEM_POWER_STATE_MASK 0xE0000000L -#define ATOM_S0_SYSTEM_POWER_STATE_SHIFT 29 +#define ATOM_S0_SYSTEM_POWER_STATE_SHIFT 29 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC 1 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC 2 @@ -5853,11 +5853,11 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 #define ATOM_S6_LID_STATEb0 0x40 #define ATOM_S6_DOCK_STATEb0 0x80 #define ATOM_S6_CRITICAL_STATEb1 0x01 -#define ATOM_S6_HW_I2C_BUSY_STATEb1 0x02 +#define ATOM_S6_HW_I2C_BUSY_STATEb1 0x02 #define ATOM_S6_THERMAL_STATE_CHANGEb1 0x04 #define ATOM_S6_INTERRUPT_SET_BY_BIOSb1 0x08 -#define ATOM_S6_REQ_LCD_EXPANSION_FULLb1 0x10 -#define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIOb1 0x20 +#define ATOM_S6_REQ_LCD_EXPANSION_FULLb1 0x10 +#define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIOb1 0x20 #define ATOM_S6_ACC_REQ_CRT1b2 0x01 #define ATOM_S6_ACC_REQ_LCD1b2 0x02 @@ -5915,26 +5915,26 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 // BIOS_8_SCRATCH Definition #define ATOM_S8_I2C_CHANNEL_BUSY_MASK 0x00000FFFF -#define ATOM_S8_I2C_HW_ENGINE_BUSY_MASK 0x0FFFF0000 +#define ATOM_S8_I2C_HW_ENGINE_BUSY_MASK 0x0FFFF0000 #define ATOM_S8_I2C_CHANNEL_BUSY_SHIFT 0 #define ATOM_S8_I2C_ENGINE_BUSY_SHIFT 16 // BIOS_9_SCRATCH Definition -#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_MASK +#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_MASK #define ATOM_S9_I2C_CHANNEL_COMPLETED_MASK 0x0000FFFF #endif -#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_MASK +#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_MASK #define ATOM_S9_I2C_CHANNEL_ABORTED_MASK 0xFFFF0000 #endif -#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT +#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT #define ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 0 #endif -#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT +#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT #define ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT 16 #endif - + #define ATOM_FLAG_SET 0x20 #define ATOM_FLAG_CLEAR 0 #define CLEAR_ATOM_S6_ACC_MODE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_ACC_MODE_SHIFT | ATOM_FLAG_CLEAR) @@ -5957,7 +5957,7 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 #define SET_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_SET) #define CLEAR_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_CLEAR) -#define SET_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_SET) +#define SET_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_SET) #define CLEAR_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_CLEAR ) #define SET_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_SET ) @@ -5972,7 +5972,7 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 #define SET_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_SET ) #define CLEAR_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_CLEAR ) -/****************************************************************************/ +/****************************************************************************/ //Portion II: Definitions only used in Driver /****************************************************************************/ @@ -5992,8 +5992,8 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 #define GET_DATA_TABLE_MAJOR_REVISION GET_COMMAND_TABLE_COMMANDSET_REVISION #define GET_DATA_TABLE_MINOR_REVISION GET_COMMAND_TABLE_PARAMETER_REVISION -/****************************************************************************/ -//Portion III: Definitinos only used in VBIOS +/****************************************************************************/ +//Portion III: Definitions only used in VBIOS /****************************************************************************/ #define ATOM_DAC_SRC 0x80 #define ATOM_SRC_DAC1 0 @@ -6011,13 +6011,13 @@ typedef struct _MEMORY_PLLINIT_PARAMETERS #define MEMORY_PLLINIT_PS_ALLOCATION MEMORY_PLLINIT_PARAMETERS -#define GPIO_PIN_WRITE 0x01 +#define GPIO_PIN_WRITE 0x01 #define GPIO_PIN_READ 0x00 typedef struct _GPIO_PIN_CONTROL_PARAMETERS { UCHAR ucGPIO_ID; //return value, read from GPIO pins - UCHAR ucGPIOBitShift; //define which bit in uGPIOBitVal need to be update + UCHAR ucGPIOBitShift; //define which bit in uGPIOBitVal need to be update UCHAR ucGPIOBitVal; //Set/Reset corresponding bit defined in ucGPIOBitMask UCHAR ucAction; //=GPIO_PIN_WRITE: Read; =GPIO_PIN_READ: Write }GPIO_PIN_CONTROL_PARAMETERS; @@ -6026,10 +6026,10 @@ typedef struct _ENABLE_SCALER_PARAMETERS { UCHAR ucScaler; // ATOM_SCALER1, ATOM_SCALER2 UCHAR ucEnable; // ATOM_SCALER_DISABLE or ATOM_SCALER_CENTER or ATOM_SCALER_EXPANSION - UCHAR ucTVStandard; // + UCHAR ucTVStandard; // UCHAR ucPadding[1]; -}ENABLE_SCALER_PARAMETERS; -#define ENABLE_SCALER_PS_ALLOCATION ENABLE_SCALER_PARAMETERS +}ENABLE_SCALER_PARAMETERS; +#define ENABLE_SCALER_PS_ALLOCATION ENABLE_SCALER_PARAMETERS //ucEnable: #define SCALER_BYPASS_AUTO_CENTER_NO_REPLICATION 0 @@ -6049,14 +6049,14 @@ typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION { ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS sEnableIcon; - ENABLE_CRTC_PARAMETERS sReserved; + ENABLE_CRTC_PARAMETERS sReserved; }ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION; typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS { USHORT usHight; // Image Hight USHORT usWidth; // Image Width - UCHAR ucSurface; // Surface 1 or 2 + UCHAR ucSurface; // Surface 1 or 2 UCHAR ucPadding[3]; }ENABLE_GRAPH_SURFACE_PARAMETERS; @@ -6075,7 +6075,7 @@ typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3 USHORT usWidth; // Image Width UCHAR ucSurface; // Surface 1 or 2 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE - USHORT usDeviceId; // Active Device Id for this surface. If no device, set to 0. + USHORT usDeviceId; // Active Device Id for this surface. If no device, set to 0. }ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3; typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_4 @@ -6097,7 +6097,7 @@ typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_4 typedef struct _ENABLE_GRAPH_SURFACE_PS_ALLOCATION { - ENABLE_GRAPH_SURFACE_PARAMETERS sSetSurface; + ENABLE_GRAPH_SURFACE_PARAMETERS sSetSurface; ENABLE_YUV_PS_ALLOCATION sReserved; // Don't set this one }ENABLE_GRAPH_SURFACE_PS_ALLOCATION; @@ -6110,23 +6110,23 @@ typedef struct _MEMORY_CLEAN_UP_PARAMETERS typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS { - USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC + USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC USHORT usY_Size; -}GET_DISPLAY_SURFACE_SIZE_PARAMETERS; +}GET_DISPLAY_SURFACE_SIZE_PARAMETERS; typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2 { union{ - USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC - USHORT usSurface; + USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC + USHORT usSurface; }; USHORT usY_Size; - USHORT usDispXStart; + USHORT usDispXStart; USHORT usDispYStart; -}GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2; +}GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2; -typedef struct _PALETTE_DATA_CONTROL_PARAMETERS_V3 +typedef struct _PALETTE_DATA_CONTROL_PARAMETERS_V3 { UCHAR ucLutId; UCHAR ucAction; @@ -6156,7 +6156,7 @@ typedef struct _INTERRUPT_SERVICE_PARAMETERS_V2 #define HDP4_INTERRUPT_ID 4 #define HDP5_INTERRUPT_ID 5 #define HDP6_INTERRUPT_ID 6 -#define SW_INTERRUPT_ID 11 +#define SW_INTERRUPT_ID 11 // ucAction #define INTERRUPT_SERVICE_GEN_SW_INT 1 @@ -6168,7 +6168,7 @@ typedef struct _INTERRUPT_SERVICE_PARAMETERS_V2 typedef struct _INDIRECT_IO_ACCESS { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; UCHAR IOAccessSequence[256]; } INDIRECT_IO_ACCESS; @@ -6197,7 +6197,7 @@ typedef struct _INDIRECT_IO_ACCESS #define INDIRECT_IO_SMU_WRITE INDIRECT_IO_SMU | INDIRECT_WRITE typedef struct _ATOM_OEM_INFO -{ +{ ATOM_COMMON_TABLE_HEADER sHeader; ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; }ATOM_OEM_INFO; @@ -6210,12 +6210,12 @@ typedef struct _ATOM_TV_MODE typedef struct _ATOM_BIOS_INT_TVSTD_MODE { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; USHORT usTV_Mode_LUT_Offset; // Pointer to standard to internal number conversion table USHORT usTV_FIFO_Offset; // Pointer to FIFO entry table USHORT usNTSC_Tbl_Offset; // Pointer to SDTV_Mode_NTSC table - USHORT usPAL_Tbl_Offset; // Pointer to SDTV_Mode_PAL table - USHORT usCV_Tbl_Offset; // Pointer to SDTV_Mode_PAL table + USHORT usPAL_Tbl_Offset; // Pointer to SDTV_Mode_PAL table + USHORT usCV_Tbl_Offset; // Pointer to SDTV_Mode_PAL table }ATOM_BIOS_INT_TVSTD_MODE; @@ -6228,13 +6228,13 @@ typedef struct _ATOM_TV_MODE_SCALER_PTR typedef struct _ATOM_STANDARD_VESA_TIMING { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; ATOM_DTD_FORMAT aModeTimings[16]; // 16 is not the real array number, just for initial allocation }ATOM_STANDARD_VESA_TIMING; typedef struct _ATOM_STD_FORMAT -{ +{ USHORT usSTD_HDisp; USHORT usSTD_VDisp; USHORT usSTD_RefreshRate; @@ -6248,8 +6248,8 @@ typedef struct _ATOM_VESA_TO_EXTENDED_MODE }ATOM_VESA_TO_EXTENDED_MODE; typedef struct _ATOM_VESA_TO_INTENAL_MODE_LUT -{ - ATOM_COMMON_TABLE_HEADER sHeader; +{ + ATOM_COMMON_TABLE_HEADER sHeader; ATOM_VESA_TO_EXTENDED_MODE asVESA_ToExtendedModeInfo[76]; }ATOM_VESA_TO_INTENAL_MODE_LUT; @@ -6315,7 +6315,7 @@ typedef struct _ATOM_INIT_REG_BLOCK{ #define ACCESS_PLACEHOLDER 0x80 typedef struct _ATOM_MC_INIT_PARAM_TABLE -{ +{ ATOM_COMMON_TABLE_HEADER sHeader; USHORT usAdjustARB_SEQDataOffset; USHORT usMCInitMemTypeTblOffset; @@ -6391,12 +6391,12 @@ typedef struct _MCuCodeHeader typedef struct _ATOM_VRAM_MODULE_V1 { ULONG ulReserved; - USHORT usEMRSValue; + USHORT usEMRSValue; USHORT usMRSValue; USHORT usReserved; UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] reserved; - UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender + UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vendor UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... UCHAR ucRow; // Number of Row,in power of 2; UCHAR ucColumn; // Number of Column,in power of 2; @@ -6418,12 +6418,12 @@ typedef struct _ATOM_VRAM_MODULE_V2 ULONG ulMemoryClock; // Override of default memory clock for particular memory type USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type - USHORT usEMRSValue; + USHORT usEMRSValue; USHORT usMRSValue; USHORT usReserved; UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; - UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed + UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vendor. If not predefined, vendor detection table gets executed UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... UCHAR ucRow; // Number of Row,in power of 2; UCHAR ucColumn; // Number of Column,in power of 2; @@ -6440,9 +6440,9 @@ typedef struct _ATOM_VRAM_MODULE_V2 typedef struct _ATOM_MEMORY_TIMING_FORMAT { - ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing + ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing union{ - USHORT usMRS; // mode register + USHORT usMRS; // mode register USHORT usDDR3_MR0; }; union{ @@ -6450,24 +6450,24 @@ typedef struct _ATOM_MEMORY_TIMING_FORMAT USHORT usDDR3_MR1; }; UCHAR ucCL; // CAS latency - UCHAR ucWL; // WRITE Latency + UCHAR ucWL; // WRITE Latency UCHAR uctRAS; // tRAS - UCHAR uctRC; // tRC + UCHAR uctRC; // tRC UCHAR uctRFC; // tRFC - UCHAR uctRCDR; // tRCDR + UCHAR uctRCDR; // tRCDR UCHAR uctRCDW; // tRCDW UCHAR uctRP; // tRP - UCHAR uctRRD; // tRRD + UCHAR uctRRD; // tRRD UCHAR uctWR; // tWR UCHAR uctWTR; // tWTR UCHAR uctPDIX; // tPDIX UCHAR uctFAW; // tFAW UCHAR uctAOND; // tAOND - union + union { struct { - UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon - UCHAR ucReserved; + UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon + UCHAR ucReserved; }; USHORT usDDR3_MR2; }; @@ -6476,71 +6476,71 @@ typedef struct _ATOM_MEMORY_TIMING_FORMAT typedef struct _ATOM_MEMORY_TIMING_FORMAT_V1 { - ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing - USHORT usMRS; // mode register + ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing + USHORT usMRS; // mode register USHORT usEMRS; // extended mode register UCHAR ucCL; // CAS latency - UCHAR ucWL; // WRITE Latency + UCHAR ucWL; // WRITE Latency UCHAR uctRAS; // tRAS - UCHAR uctRC; // tRC + UCHAR uctRC; // tRC UCHAR uctRFC; // tRFC - UCHAR uctRCDR; // tRCDR + UCHAR uctRCDR; // tRCDR UCHAR uctRCDW; // tRCDW UCHAR uctRP; // tRP - UCHAR uctRRD; // tRRD + UCHAR uctRRD; // tRRD UCHAR uctWR; // tWR UCHAR uctWTR; // tWTR UCHAR uctPDIX; // tPDIX UCHAR uctFAW; // tFAW UCHAR uctAOND; // tAOND - UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon + UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon ////////////////////////////////////GDDR parameters/////////////////////////////////// - UCHAR uctCCDL; // - UCHAR uctCRCRL; // - UCHAR uctCRCWL; // - UCHAR uctCKE; // - UCHAR uctCKRSE; // - UCHAR uctCKRSX; // - UCHAR uctFAW32; // - UCHAR ucMR5lo; // - UCHAR ucMR5hi; // + UCHAR uctCCDL; // + UCHAR uctCRCRL; // + UCHAR uctCRCWL; // + UCHAR uctCKE; // + UCHAR uctCKRSE; // + UCHAR uctCKRSX; // + UCHAR uctFAW32; // + UCHAR ucMR5lo; // + UCHAR ucMR5hi; // UCHAR ucTerminator; }ATOM_MEMORY_TIMING_FORMAT_V1; typedef struct _ATOM_MEMORY_TIMING_FORMAT_V2 { - ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing - USHORT usMRS; // mode register + ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing + USHORT usMRS; // mode register USHORT usEMRS; // extended mode register UCHAR ucCL; // CAS latency - UCHAR ucWL; // WRITE Latency + UCHAR ucWL; // WRITE Latency UCHAR uctRAS; // tRAS - UCHAR uctRC; // tRC + UCHAR uctRC; // tRC UCHAR uctRFC; // tRFC - UCHAR uctRCDR; // tRCDR + UCHAR uctRCDR; // tRCDR UCHAR uctRCDW; // tRCDW UCHAR uctRP; // tRP - UCHAR uctRRD; // tRRD + UCHAR uctRRD; // tRRD UCHAR uctWR; // tWR UCHAR uctWTR; // tWTR UCHAR uctPDIX; // tPDIX UCHAR uctFAW; // tFAW UCHAR uctAOND; // tAOND - UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon + UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon ////////////////////////////////////GDDR parameters/////////////////////////////////// - UCHAR uctCCDL; // - UCHAR uctCRCRL; // - UCHAR uctCRCWL; // - UCHAR uctCKE; // - UCHAR uctCKRSE; // - UCHAR uctCKRSX; // - UCHAR uctFAW32; // - UCHAR ucMR4lo; // - UCHAR ucMR4hi; // - UCHAR ucMR5lo; // - UCHAR ucMR5hi; // + UCHAR uctCCDL; // + UCHAR uctCRCRL; // + UCHAR uctCRCWL; // + UCHAR uctCKE; // + UCHAR uctCKRSE; // + UCHAR uctCKRSX; // + UCHAR uctFAW32; // + UCHAR ucMR4lo; // + UCHAR ucMR4hi; // + UCHAR ucMR5lo; // + UCHAR ucMR5hi; // UCHAR ucTerminator; - UCHAR ucReserved; + UCHAR ucReserved; }ATOM_MEMORY_TIMING_FORMAT_V2; typedef struct _ATOM_MEMORY_FORMAT @@ -6555,17 +6555,17 @@ typedef struct _ATOM_MEMORY_FORMAT USHORT usDDR3_MR3; // Used for DDR3 memory }; UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; - UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed + UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vendor. If not predefined, vendor detection table gets executed UCHAR ucRow; // Number of Row,in power of 2; UCHAR ucColumn; // Number of Column,in power of 2; UCHAR ucBank; // Nunber of Bank; UCHAR ucRank; // Number of Rank, in power of 2 UCHAR ucBurstSize; // burst size, 0= burst size=4 1= burst size=8 UCHAR ucDllDisBit; // position of DLL Enable/Disable bit in EMRS ( Extended Mode Register ) - UCHAR ucRefreshRateFactor; // memory refresh rate in unit of ms + UCHAR ucRefreshRateFactor; // memory refresh rate in unit of ms UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 UCHAR ucPreamble; //[7:4] Write Preamble, [3:0] Read Preamble - UCHAR ucMemAttrib; // Memory Device Addribute, like RDBI/WDBI etc + UCHAR ucMemAttrib; // Memory Device Attribute, like RDBI/WDBI etc ATOM_MEMORY_TIMING_FORMAT asMemTiming[5]; //Memory Timing block sort from lower clock to higher clock }ATOM_MEMORY_FORMAT; @@ -6578,8 +6578,8 @@ typedef struct _ATOM_VRAM_MODULE_V3 USHORT usDefaultMVDDC; // board dependent parameter:Default Memory IO Voltage UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module UCHAR ucChannelNum; // board dependent parameter:Number of channel; - UCHAR ucChannelSize; // board dependent parameter:32bit or 64bit - UCHAR ucVREFI; // board dependnt parameter: EXT or INT +160mv to -140mv + UCHAR ucChannelSize; // board dependent parameter:32bit or 64bit + UCHAR ucVREFI; // board dependent parameter: EXT or INT +160mv to -140mv UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters UCHAR ucFlag; // To enable/disable functionalities based on memory type ATOM_MEMORY_FORMAT asMemory; // describ all of video memory parameters from memory spec @@ -6621,7 +6621,7 @@ typedef struct _ATOM_VRAM_MODULE_V4 union{ USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type USHORT usDDR3_MR3; // Used for DDR3 memory - }; + }; UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) UCHAR ucReserved2[2]; @@ -6717,13 +6717,13 @@ typedef struct _ATOM_VRAM_MODULE_V7 USHORT usSEQSettingOffset; UCHAR ucReserved; // Memory Module specific values - USHORT usEMRS2Value; // EMRS2/MR2 Value. + USHORT usEMRS2Value; // EMRS2/MR2 Value. USHORT usEMRS3Value; // EMRS3/MR3 Value. UCHAR ucMemoryVenderID; // [7:4] Revision, [3:0] Vendor code UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) UCHAR ucFIFODepth; // FIFO depth can be detected during vendor detection, here is hardcoded per memory UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth - char strMemPNString[20]; // part number end with '0'. + char strMemPNString[20]; // part number end with '0'. }ATOM_VRAM_MODULE_V7; typedef struct _ATOM_VRAM_INFO_V2 @@ -6756,7 +6756,7 @@ typedef struct _ATOM_VRAM_INFO_V4 USHORT usRerseved; UCHAR ucMemDQ7_0ByteRemap; // DQ line byte remap, =0: Memory Data line BYTE0, =1: BYTE1, =2: BYTE2, =3: BYTE3 ULONG ulMemDQ7_0BitRemap; // each DQ line ( 7~0) use 3bits, like: DQ0=Bit[2:0], DQ1:[5:3], ... DQ7:[23:21] - UCHAR ucReservde[4]; + UCHAR ucReservde[4]; UCHAR ucNumOfVRAMModule; ATOM_VRAM_MODULE_V4 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; ATOM_INIT_REG_BLOCK asMemPatch; // for allocation @@ -6773,7 +6773,7 @@ typedef struct _ATOM_VRAM_INFO_HEADER_V2_1 UCHAR ucNumOfVRAMModule; // indicate number of VRAM module UCHAR ucMemoryClkPatchTblVer; // version of memory AC timing register list UCHAR ucVramModuleVer; // indicate ATOM_VRAM_MODUE version - UCHAR ucReserved; + UCHAR ucReserved; ATOM_VRAM_MODULE_V7 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; }ATOM_VRAM_INFO_HEADER_V2_1; @@ -6797,18 +6797,18 @@ typedef struct _ATOM_MEMORY_TRAINING_INFO typedef struct SW_I2C_CNTL_DATA_PARAMETERS { UCHAR ucControl; - UCHAR ucData; - UCHAR ucSatus; - UCHAR ucTemp; + UCHAR ucData; + UCHAR ucSatus; + UCHAR ucTemp; } SW_I2C_CNTL_DATA_PARAMETERS; #define SW_I2C_CNTL_DATA_PS_ALLOCATION SW_I2C_CNTL_DATA_PARAMETERS typedef struct _SW_I2C_IO_DATA_PARAMETERS -{ +{ USHORT GPIO_Info; - UCHAR ucAct; - UCHAR ucData; + UCHAR ucAct; + UCHAR ucData; } SW_I2C_IO_DATA_PARAMETERS; #define SW_I2C_IO_DATA_PS_ALLOCATION SW_I2C_IO_DATA_PARAMETERS @@ -6842,8 +6842,8 @@ typedef struct _SW_I2C_IO_DATA_PARAMETERS typedef struct _PTR_32_BIT_STRUCTURE { - USHORT Offset16; - USHORT Segment16; + USHORT Offset16; + USHORT Segment16; } PTR_32_BIT_STRUCTURE; typedef union _PTR_32_BIT_UNION @@ -6963,7 +6963,7 @@ typedef struct _VESA_MODE_INFO_BLOCK #define ATOM_BIOS_FUNCTION_SHORT_QUERY1 0x04 #define ATOM_BIOS_FUNCTION_SHORT_QUERY2 0x05 #define ATOM_BIOS_FUNCTION_SHORT_QUERY3 0x06 -#define ATOM_BIOS_FUNCTION_GET_DDC 0x0B +#define ATOM_BIOS_FUNCTION_GET_DDC 0x0B #define ATOM_BIOS_FUNCTION_ASIC_DSTATE 0x0E #define ATOM_BIOS_FUNCTION_DEBUG_PLAY 0x0F #define ATOM_BIOS_FUNCTION_STV_STD 0x16 @@ -6973,28 +6973,28 @@ typedef struct _VESA_MODE_INFO_BLOCK #define ATOM_BIOS_FUNCTION_PANEL_CONTROL 0x82 #define ATOM_BIOS_FUNCTION_OLD_DEVICE_DET 0x83 #define ATOM_BIOS_FUNCTION_OLD_DEVICE_SWITCH 0x84 -#define ATOM_BIOS_FUNCTION_HW_ICON 0x8A +#define ATOM_BIOS_FUNCTION_HW_ICON 0x8A #define ATOM_BIOS_FUNCTION_SET_CMOS 0x8B #define SUB_FUNCTION_UPDATE_DISPLAY_INFO 0x8000 // Sub function 80 #define SUB_FUNCTION_UPDATE_EXPANSION_INFO 0x8100 // Sub function 80 #define ATOM_BIOS_FUNCTION_DISPLAY_INFO 0x8D #define ATOM_BIOS_FUNCTION_DEVICE_ON_OFF 0x8E -#define ATOM_BIOS_FUNCTION_VIDEO_STATE 0x8F -#define ATOM_SUB_FUNCTION_GET_CRITICAL_STATE 0x0300 // Sub function 03 +#define ATOM_BIOS_FUNCTION_VIDEO_STATE 0x8F +#define ATOM_SUB_FUNCTION_GET_CRITICAL_STATE 0x0300 // Sub function 03 #define ATOM_SUB_FUNCTION_GET_LIDSTATE 0x0700 // Sub function 7 #define ATOM_SUB_FUNCTION_THERMAL_STATE_NOTICE 0x1400 // Notify caller the current thermal state #define ATOM_SUB_FUNCTION_CRITICAL_STATE_NOTICE 0x8300 // Notify caller the current critical state #define ATOM_SUB_FUNCTION_SET_LIDSTATE 0x8500 // Sub function 85 #define ATOM_SUB_FUNCTION_GET_REQ_DISPLAY_FROM_SBIOS_MODE 0x8900// Sub function 89 #define ATOM_SUB_FUNCTION_INFORM_ADC_SUPPORT 0x9400 // Notify caller that ADC is supported - -#define ATOM_BIOS_FUNCTION_VESA_DPMS 0x4F10 // Set DPMS -#define ATOM_SUB_FUNCTION_SET_DPMS 0x0001 // BL: Sub function 01 -#define ATOM_SUB_FUNCTION_GET_DPMS 0x0002 // BL: Sub function 02 -#define ATOM_PARAMETER_VESA_DPMS_ON 0x0000 // BH Parameter for DPMS ON. -#define ATOM_PARAMETER_VESA_DPMS_STANDBY 0x0100 // BH Parameter for DPMS STANDBY + +#define ATOM_BIOS_FUNCTION_VESA_DPMS 0x4F10 // Set DPMS +#define ATOM_SUB_FUNCTION_SET_DPMS 0x0001 // BL: Sub function 01 +#define ATOM_SUB_FUNCTION_GET_DPMS 0x0002 // BL: Sub function 02 +#define ATOM_PARAMETER_VESA_DPMS_ON 0x0000 // BH Parameter for DPMS ON. +#define ATOM_PARAMETER_VESA_DPMS_STANDBY 0x0100 // BH Parameter for DPMS STANDBY #define ATOM_PARAMETER_VESA_DPMS_SUSPEND 0x0200 // BH Parameter for DPMS SUSPEND #define ATOM_PARAMETER_VESA_DPMS_OFF 0x0400 // BH Parameter for DPMS OFF #define ATOM_PARAMETER_VESA_DPMS_REDUCE_ON 0x0800 // BH Parameter for DPMS REDUCE ON (NOT SUPPORTED) @@ -7037,7 +7037,7 @@ typedef struct _ASIC_ENCODER_INFO typedef struct _ATOM_DISP_OUT_INFO { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; USHORT ptrTransmitterInfo; USHORT ptrEncoderInfo; ASIC_TRANSMITTER_INFO asTransmitterInfo[1]; @@ -7046,17 +7046,17 @@ typedef struct _ATOM_DISP_OUT_INFO typedef struct _ATOM_DISP_OUT_INFO_V2 { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; USHORT ptrTransmitterInfo; USHORT ptrEncoderInfo; - USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary. + USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary. ASIC_TRANSMITTER_INFO asTransmitterInfo[1]; ASIC_ENCODER_INFO asEncoderInfo[1]; }ATOM_DISP_OUT_INFO_V2; typedef struct _ATOM_DISP_CLOCK_ID { - UCHAR ucPpllId; + UCHAR ucPpllId; UCHAR ucPpllAttribute; }ATOM_DISP_CLOCK_ID; @@ -7080,19 +7080,19 @@ typedef struct _ASIC_TRANSMITTER_INFO_V2 typedef struct _ATOM_DISP_OUT_INFO_V3 { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; USHORT ptrTransmitterInfo; USHORT ptrEncoderInfo; - USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary. + USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary. USHORT usReserved; - UCHAR ucDCERevision; + UCHAR ucDCERevision; UCHAR ucMaxDispEngineNum; UCHAR ucMaxActiveDispEngineNum; UCHAR ucMaxPPLLNum; UCHAR ucCoreRefClkSource; // value of CORE_REF_CLK_SOURCE UCHAR ucDispCaps; UCHAR ucReserved[2]; - ASIC_TRANSMITTER_INFO_V2 asTransmitterInfo[1]; // for alligment only + ASIC_TRANSMITTER_INFO_V2 asTransmitterInfo[1]; // for alignment only }ATOM_DISP_OUT_INFO_V3; //ucDispCaps @@ -7108,7 +7108,7 @@ typedef enum CORE_REF_CLK_SOURCE{ // DispDevicePriorityInfo typedef struct _ATOM_DISPLAY_DEVICE_PRIORITY_INFO { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; USHORT asDevicePriority[16]; }ATOM_DISPLAY_DEVICE_PRIORITY_INFO; @@ -7149,7 +7149,7 @@ typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 typedef struct _DP_ENCODER_SERVICE_PARAMETERS { USHORT ucLinkClock; - union + union { UCHAR ucConfig; // for DP training command UCHAR ucI2cId; // use for GET_SINK_TYPE command @@ -7187,7 +7187,7 @@ typedef struct _DP_ENCODER_SERVICE_PARAMETERS_V2 USHORT usExtEncoderObjId; // External Encoder Object Id, output parameter only, use when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION UCHAR ucAuxId; UCHAR ucAction; - UCHAR ucSinkType; // Iput and Output parameters. + UCHAR ucSinkType; // Iput and Output parameters. UCHAR ucHPDId; // Input parameter, used when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION UCHAR ucReserved[2]; }DP_ENCODER_SERVICE_PARAMETERS_V2; @@ -7204,7 +7204,7 @@ typedef struct _DP_ENCODER_SERVICE_PS_ALLOCATION_V2 // DP_TRAINING_TABLE -#define DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR ATOM_DP_TRAINING_TBL_ADDR +#define DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR ATOM_DP_TRAINING_TBL_ADDR #define DPCD_SET_SS_CNTL_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 8 ) #define DPCD_SET_LANE_VSWING_PREEMP_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 16 ) #define DPCD_SET_TRAINING_PATTERN0_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 24 ) @@ -7215,7 +7215,7 @@ typedef struct _DP_ENCODER_SERVICE_PS_ALLOCATION_V2 #define DP_I2C_AUX_DDC_WRITE_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 64) #define DP_I2C_AUX_DDC_READ_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 72) #define DP_I2C_AUX_DDC_READ_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 76) -#define DP_I2C_AUX_DDC_WRITE_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 80) +#define DP_I2C_AUX_DDC_WRITE_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 80) #define DP_I2C_AUX_DDC_READ_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 84) typedef struct _PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS @@ -7227,7 +7227,7 @@ typedef struct _PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS UCHAR ucStatus; }; USHORT lpI2CDataOut; - UCHAR ucFlag; + UCHAR ucFlag; UCHAR ucTransBytes; UCHAR ucSlaveAddr; UCHAR ucLineNumber; @@ -7240,17 +7240,17 @@ typedef struct _PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS #define HW_I2C_READ 0 #define I2C_2BYTE_ADDR 0x02 -/****************************************************************************/ +/****************************************************************************/ // Structures used by HW_Misc_OperationTable -/****************************************************************************/ -typedef struct _ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1 +/****************************************************************************/ +typedef struct _ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1 { UCHAR ucCmd; // Input: To tell which action to take UCHAR ucReserved[3]; ULONG ulReserved; -}ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1; +}ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1; -typedef struct _ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1 +typedef struct _ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1 { UCHAR ucReturnCode; // Output: Return value base on action was taken UCHAR ucReserved[3]; @@ -7260,7 +7260,7 @@ typedef struct _ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1 // Actions code #define ATOM_GET_SDI_SUPPORT 0xF0 -// Return code +// Return code #define ATOM_UNKNOWN_CMD 0 #define ATOM_FEATURE_NOT_SUPPORTED 1 #define ATOM_FEATURE_SUPPORTED 2 @@ -7268,15 +7268,15 @@ typedef struct _ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1 typedef struct _ATOM_HW_MISC_OPERATION_PS_ALLOCATION { ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1 sInput_Output; - PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS sReserved; + PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS sReserved; }ATOM_HW_MISC_OPERATION_PS_ALLOCATION; -/****************************************************************************/ +/****************************************************************************/ typedef struct _SET_HWBLOCK_INSTANCE_PARAMETER_V2 { UCHAR ucHWBlkInst; // HW block instance, 0, 1, 2, ... - UCHAR ucReserved[3]; + UCHAR ucReserved[3]; }SET_HWBLOCK_INSTANCE_PARAMETER_V2; #define HWBLKINST_INSTANCE_MASK 0x07 @@ -7293,24 +7293,24 @@ typedef struct _SET_HWBLOCK_INSTANCE_PARAMETER_V2 #define SELECT_CRTC_PIXEL_RATE 7 #define SELECT_VGA_BLK 8 -// DIGTransmitterInfoTable structure used to program UNIPHY settings -typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_1{ - ATOM_COMMON_TABLE_HEADER sHeader; - USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock - USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info +// DIGTransmitterInfoTable structure used to program UNIPHY settings +typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_1{ + ATOM_COMMON_TABLE_HEADER sHeader; + USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock + USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range - USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info + USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info USHORT usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings }DIG_TRANSMITTER_INFO_HEADER_V3_1; -typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_2{ - ATOM_COMMON_TABLE_HEADER sHeader; - USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock - USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info +typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_2{ + ATOM_COMMON_TABLE_HEADER sHeader; + USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock + USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range - USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info + USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info USHORT usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings - USHORT usDPSSRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy SS Pll register Info + USHORT usDPSSRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy SS Pll register Info USHORT usDPSSSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy SS Pll Settings }DIG_TRANSMITTER_INFO_HEADER_V3_2; @@ -7371,9 +7371,9 @@ typedef struct _PHY_ANALOG_SETTING_INFO_V2{ typedef struct _GFX_HAVESTING_PARAMETERS { UCHAR ucGfxBlkId; //GFX blk id to be harvested, like CU, RB or PRIM - UCHAR ucReserved; //reserved + UCHAR ucReserved; //reserved UCHAR ucActiveUnitNumPerSH; //requested active CU/RB/PRIM number per shader array - UCHAR ucMaxUnitNumPerSH; //max CU/RB/PRIM number per shader array + UCHAR ucMaxUnitNumPerSH; //max CU/RB/PRIM number per shader array } GFX_HAVESTING_PARAMETERS; //ucGfxBlkId @@ -7381,8 +7381,8 @@ typedef struct _GFX_HAVESTING_PARAMETERS { #define GFX_HARVESTING_RB_ID 1 #define GFX_HARVESTING_PRIM_ID 2 -/****************************************************************************/ -//Portion VI: Definitinos for vbios MC scratch registers that driver used +/****************************************************************************/ +//Portion VI: Definitions for vbios MC scratch registers that driver used /****************************************************************************/ #define MC_MISC0__MEMORY_TYPE_MASK 0xF0000000 @@ -7402,23 +7402,23 @@ typedef struct _GFX_HAVESTING_PARAMETERS { #define ATOM_MEM_TYPE_HBM_STRING "HBM" #define ATOM_MEM_TYPE_DDR3_STRING "DDR3" -/****************************************************************************/ -//Portion VI: Definitinos being oboselete +/****************************************************************************/ +//Portion VI: Definitions being obsolete /****************************************************************************/ //========================================================================================== //Remove the definitions below when driver is ready! typedef struct _ATOM_DAC_INFO { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; USHORT usMaxFrequency; // in 10kHz unit USHORT usReserved; }ATOM_DAC_INFO; -typedef struct _COMPASSIONATE_DATA +typedef struct _COMPASSIONATE_DATA { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; //============================== DAC1 portion UCHAR ucDAC1_BG_Adjustment; @@ -7448,7 +7448,7 @@ typedef struct _COMPASSIONATE_DATA /****************************Supported Device Info Table Definitions**********************/ // ucConnectInfo: // [7:4] - connector type -// = 1 - VGA connector +// = 1 - VGA connector // = 2 - DVI-I // = 3 - DVI-D // = 4 - DVI-A @@ -7467,7 +7467,7 @@ typedef struct _COMPASSIONATE_DATA // = 2 - DACB // = 3 - External DAC // Others=TBD -// +// typedef struct _ATOM_CONNECTOR_INFO { @@ -7494,7 +7494,7 @@ typedef struct _ATOM_CONNECTOR_INFO_I2C typedef struct _ATOM_SUPPORTED_DEVICES_INFO -{ +{ ATOM_COMMON_TABLE_HEADER sHeader; USHORT usDeviceSupport; ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO]; @@ -7508,7 +7508,7 @@ typedef struct _ATOM_CONNECTOR_INC_SRC_BITMAP }ATOM_CONNECTOR_INC_SRC_BITMAP; typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2 -{ +{ ATOM_COMMON_TABLE_HEADER sHeader; USHORT usDeviceSupport; ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2]; @@ -7516,7 +7516,7 @@ typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2 }ATOM_SUPPORTED_DEVICES_INFO_2; typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 -{ +{ ATOM_COMMON_TABLE_HEADER sHeader; USHORT usDeviceSupport; ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE]; @@ -7534,14 +7534,14 @@ typedef struct _ATOM_MISC_CONTROL_INFO UCHAR ucPLL_DutyCycle; // PLL duty cycle control UCHAR ucPLL_VCO_Gain; // PLL VCO gain control UCHAR ucPLL_VoltageSwing; // PLL driver voltage swing control -}ATOM_MISC_CONTROL_INFO; +}ATOM_MISC_CONTROL_INFO; #define ATOM_MAX_MISC_INFO 4 typedef struct _ATOM_TMDS_INFO { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; USHORT usMaxFrequency; // in 10Khz ATOM_MISC_CONTROL_INFO asMiscInfo[ATOM_MAX_MISC_INFO]; }ATOM_TMDS_INFO; @@ -7549,14 +7549,14 @@ typedef struct _ATOM_TMDS_INFO typedef struct _ATOM_ENCODER_ANALOG_ATTRIBUTE { - UCHAR ucTVStandard; //Same as TV standards defined above, + UCHAR ucTVStandard; //Same as TV standards defined above, UCHAR ucPadding[1]; }ATOM_ENCODER_ANALOG_ATTRIBUTE; typedef struct _ATOM_ENCODER_DIGITAL_ATTRIBUTE { UCHAR ucAttribute; //Same as other digital encoder attributes defined above - UCHAR ucPadding[1]; + UCHAR ucPadding[1]; }ATOM_ENCODER_DIGITAL_ATTRIBUTE; typedef union _ATOM_ENCODER_ATTRIBUTE @@ -7568,15 +7568,15 @@ typedef union _ATOM_ENCODER_ATTRIBUTE typedef struct _DVO_ENCODER_CONTROL_PARAMETERS { - USHORT usPixelClock; - USHORT usEncoderID; - UCHAR ucDeviceType; //Use ATOM_DEVICE_xxx1_Index to indicate device type only. + USHORT usPixelClock; + USHORT usEncoderID; + UCHAR ucDeviceType; //Use ATOM_DEVICE_xxx1_Index to indicate device type only. UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT - ATOM_ENCODER_ATTRIBUTE usDevAttr; + ATOM_ENCODER_ATTRIBUTE usDevAttr; }DVO_ENCODER_CONTROL_PARAMETERS; typedef struct _DVO_ENCODER_CONTROL_PS_ALLOCATION -{ +{ DVO_ENCODER_CONTROL_PARAMETERS sDVOEncoder; WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion }DVO_ENCODER_CONTROL_PS_ALLOCATION; @@ -7589,25 +7589,25 @@ typedef struct _DVO_ENCODER_CONTROL_PS_ALLOCATION #define ATOM_XTMDS_SUPPORTED_DUALLINK 0x00000002 #define ATOM_XTMDS_MVPU_FPGA 0x00000004 - + typedef struct _ATOM_XTMDS_INFO { - ATOM_COMMON_TABLE_HEADER sHeader; - USHORT usSingleLinkMaxFrequency; + ATOM_COMMON_TABLE_HEADER sHeader; + USHORT usSingleLinkMaxFrequency; ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //Point the ID on which I2C is used to control external chip - UCHAR ucXtransimitterID; + UCHAR ucXtransimitterID; UCHAR ucSupportedLink; // Bit field, bit0=1, single link supported;bit1=1,dual link supported - UCHAR ucSequnceAlterID; // Even with the same external TMDS asic, it's possible that the program seqence alters - // due to design. This ID is used to alert driver that the sequence is not "standard"! + UCHAR ucSequnceAlterID; // Even with the same external TMDS asic, it's possible that the program sequence alters + // due to design. This ID is used to alert driver that the sequence is not "standard"! UCHAR ucMasterAddress; // Address to control Master xTMDS Chip UCHAR ucSlaveAddress; // Address to control Slave xTMDS Chip }ATOM_XTMDS_INFO; typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS -{ +{ UCHAR ucEnable; // ATOM_ENABLE=On or ATOM_DISABLE=Off UCHAR ucDevice; // ATOM_DEVICE_DFP1_INDEX.... - UCHAR ucPadding[2]; + UCHAR ucPadding[2]; }DFP_DPMS_STATUS_CHANGE_PARAMETERS; /****************************Legacy Power Play Table Definitions **********************/ @@ -7624,8 +7624,8 @@ typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS #define ATOM_PM_MISCINFO_ENGINE_CLOCK_CONTRL_EN 0x00000020L #define ATOM_PM_MISCINFO_MEMORY_CLOCK_CONTRL_EN 0x00000040L -#define ATOM_PM_MISCINFO_PROGRAM_VOLTAGE 0x00000080L //When this bit set, ucVoltageDropIndex is not an index for GPIO pin, but a voltage ID that SW needs program - +#define ATOM_PM_MISCINFO_PROGRAM_VOLTAGE 0x00000080L //When this bit set, ucVoltageDropIndex is not an index for GPIO pin, but a voltage ID that SW needs program + #define ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN 0x00000100L #define ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN 0x00000200L #define ATOM_PM_MISCINFO_ASIC_SLEEP_MODE_EN 0x00000400L @@ -7635,22 +7635,22 @@ typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS #define ATOM_PM_MISCINFO_LOW_LCD_REFRESH_RATE 0x00004000L #define ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE 0x00008000L -#define ATOM_PM_MISCINFO_OVER_CLOCK_MODE 0x00010000L +#define ATOM_PM_MISCINFO_OVER_CLOCK_MODE 0x00010000L #define ATOM_PM_MISCINFO_OVER_DRIVE_MODE 0x00020000L #define ATOM_PM_MISCINFO_POWER_SAVING_MODE 0x00040000L #define ATOM_PM_MISCINFO_THERMAL_DIODE_MODE 0x00080000L #define ATOM_PM_MISCINFO_FRAME_MODULATION_MASK 0x00300000L //0-FM Disable, 1-2 level FM, 2-4 level FM, 3-Reserved -#define ATOM_PM_MISCINFO_FRAME_MODULATION_SHIFT 20 +#define ATOM_PM_MISCINFO_FRAME_MODULATION_SHIFT 20 #define ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE 0x00400000L #define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2 0x00800000L #define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4 0x01000000L -#define ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN 0x02000000L //When set, Dynamic +#define ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN 0x02000000L //When set, Dynamic #define ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN 0x04000000L //When set, Dynamic #define ATOM_PM_MISCINFO_3D_ACCELERATION_EN 0x08000000L //When set, This mode is for acceleated 3D mode -#define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_MASK 0x70000000L //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-High Performance, 5- Optimal Performance (Default state with Default clocks) +#define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_MASK 0x70000000L //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-High Performance, 5- Optimal Performance (Default state with Default clocks) #define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_SHIFT 28 #define ATOM_PM_MISCINFO_ENABLE_BACK_BIAS 0x80000000L @@ -7660,11 +7660,11 @@ typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS #define ATOM_PM_MISCINFO2_FS3D_OVERDRIVE_INFO 0x00000008L #define ATOM_PM_MISCINFO2_FORCEDLOWPWR_MODE 0x00000010L #define ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN 0x00000020L -#define ATOM_PM_MISCINFO2_VIDEO_PLAYBACK_CAPABLE 0x00000040L //If this bit is set in multi-pp mode, then driver will pack up one with the minior power consumption. +#define ATOM_PM_MISCINFO2_VIDEO_PLAYBACK_CAPABLE 0x00000040L //If this bit is set in multi-pp mode, then driver will pack up one with the minior power consumption. //If it's not set in any pp mode, driver will use its default logic to pick a pp mode in video playback #define ATOM_PM_MISCINFO2_NOT_VALID_ON_DC 0x00000080L #define ATOM_PM_MISCINFO2_STUTTER_MODE_EN 0x00000100L -#define ATOM_PM_MISCINFO2_UVD_SUPPORT_MODE 0x00000200L +#define ATOM_PM_MISCINFO2_UVD_SUPPORT_MODE 0x00000200L //ucTableFormatRevision=1 //ucTableContentRevision=1 @@ -7687,8 +7687,8 @@ typedef struct _ATOM_POWERMODE_INFO typedef struct _ATOM_POWERMODE_INFO_V2 { ULONG ulMiscInfo; //The power level should be arranged in ascending order - ULONG ulMiscInfo2; - ULONG ulEngineClock; + ULONG ulMiscInfo2; + ULONG ulEngineClock; ULONG ulMemoryClock; UCHAR ucVoltageDropIndex; // index to GPIO table UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate @@ -7702,15 +7702,15 @@ typedef struct _ATOM_POWERMODE_INFO_V2 typedef struct _ATOM_POWERMODE_INFO_V3 { ULONG ulMiscInfo; //The power level should be arranged in ascending order - ULONG ulMiscInfo2; - ULONG ulEngineClock; + ULONG ulMiscInfo2; + ULONG ulEngineClock; ULONG ulMemoryClock; - UCHAR ucVoltageDropIndex; // index to Core (VDDC) votage table + UCHAR ucVoltageDropIndex; // index to Core (VDDC) voltage table UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate UCHAR ucMinTemperature; UCHAR ucMaxTemperature; UCHAR ucNumPciELanes; // number of PCIE lanes - UCHAR ucVDDCI_VoltageDropIndex; // index to VDDCI votage table + UCHAR ucVDDCI_VoltageDropIndex; // index to VDDCI voltage table }ATOM_POWERMODE_INFO_V3; @@ -7730,7 +7730,7 @@ typedef struct _ATOM_POWERMODE_INFO_V3 typedef struct _ATOM_POWERPLAY_INFO { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; UCHAR ucOverdriveThermalController; UCHAR ucOverdriveI2cLine; UCHAR ucOverdriveIntBitmap; @@ -7742,7 +7742,7 @@ typedef struct _ATOM_POWERPLAY_INFO typedef struct _ATOM_POWERPLAY_INFO_V2 { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; UCHAR ucOverdriveThermalController; UCHAR ucOverdriveI2cLine; UCHAR ucOverdriveIntBitmap; @@ -7751,10 +7751,10 @@ typedef struct _ATOM_POWERPLAY_INFO_V2 UCHAR ucNumOfPowerModeEntries; ATOM_POWERMODE_INFO_V2 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; }ATOM_POWERPLAY_INFO_V2; - + typedef struct _ATOM_POWERPLAY_INFO_V3 { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; UCHAR ucOverdriveThermalController; UCHAR ucOverdriveI2cLine; UCHAR ucOverdriveIntBitmap; @@ -7765,14 +7765,14 @@ typedef struct _ATOM_POWERPLAY_INFO_V3 }ATOM_POWERPLAY_INFO_V3; -// Following definitions are for compatibility issue in different SW components. +// Following definitions are for compatibility issue in different SW components. #define ATOM_MASTER_DATA_TABLE_REVISION 0x01 -#define Object_Info Object_Header +#define Object_Info Object_Header #define AdjustARB_SEQ MC_InitParameter #define VRAM_GPIO_DetectionInfo VoltageObjectInfo -#define ASIC_VDDCI_Info ASIC_ProfilingInfo +#define ASIC_VDDCI_Info ASIC_ProfilingInfo #define ASIC_MVDDQ_Info MemoryTrainingInfo -#define SS_Info PPLL_SS_Info +#define SS_Info PPLL_SS_Info #define ASIC_MVDDC_Info ASIC_InternalSS_Info #define DispDevicePriorityInfo SaveRestoreInfo #define DispOutInfo TV_VideoMode @@ -7796,7 +7796,7 @@ typedef struct _ATOM_POWERPLAY_INFO_V3 #define ATOM_DEVICE_DFP1I_INDEX ATOM_DEVICE_DFP1_INDEX #define ATOM_DEVICE_DFP1X_INDEX ATOM_DEVICE_DFP2_INDEX - + #define ATOM_DEVICE_DFP2I_INDEX 0x00000009 #define ATOM_DEVICE_DFP2I_SUPPORT (0x1L << ATOM_DEVICE_DFP2I_INDEX) @@ -7814,7 +7814,7 @@ typedef struct _ATOM_POWERPLAY_INFO_V3 #define ATOM_S3_DFP2I_ACTIVEb1 0x02 -#define ATOM_S3_DFP1I_ACTIVE ATOM_S3_DFP1_ACTIVE +#define ATOM_S3_DFP1I_ACTIVE ATOM_S3_DFP1_ACTIVE #define ATOM_S3_DFP1X_ACTIVE ATOM_S3_DFP2_ACTIVE #define ATOM_S3_DFP2I_ACTIVE 0x00000200L @@ -7833,14 +7833,14 @@ typedef struct _ATOM_POWERPLAY_INFO_V3 #define ATOM_S6_ACC_REQ_DFP2Ib3 0x02 #define ATOM_S6_ACC_REQ_DFP2I 0x02000000L -#define TMDS1XEncoderControl DVOEncoderControl +#define TMDS1XEncoderControl DVOEncoderControl #define DFP1XOutputControl DVOOutputControl #define ExternalDFPOutputControl DFP1XOutputControl #define EnableExternalTMDS_Encoder TMDS1XEncoderControl #define DFP1IOutputControl TMDSAOutputControl -#define DFP2IOutputControl LVTMAOutputControl +#define DFP2IOutputControl LVTMAOutputControl #define DAC1_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS #define DAC1_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION @@ -7849,7 +7849,7 @@ typedef struct _ATOM_POWERPLAY_INFO_V3 #define DAC2_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION #define ucDac1Standard ucDacStandard -#define ucDac2Standard ucDacStandard +#define ucDac2Standard ucDacStandard #define TMDS1EncoderControl TMDSAEncoderControl #define TMDS2EncoderControl LVTMAEncoderControl @@ -7861,7 +7861,7 @@ typedef struct _ATOM_POWERPLAY_INFO_V3 //These two lines will be removed for sure in a few days, will follow up with Michael V. #define EnableLVDS_SS EnableSpreadSpectrumOnPPLL -#define ENABLE_LVDS_SS_PARAMETERS_V3 ENABLE_SPREAD_SPECTRUM_ON_PPLL +#define ENABLE_LVDS_SS_PARAMETERS_V3 ENABLE_SPREAD_SPECTRUM_ON_PPLL //#define ATOM_S2_CRT1_DPMS_STATE 0x00010000L //#define ATOM_S2_LCD1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE diff --git a/sys/dev/pci/if_aq_pci.c b/sys/dev/pci/if_aq_pci.c index 206e4b3a4..14391968b 100644 --- a/sys/dev/pci/if_aq_pci.c +++ b/sys/dev/pci/if_aq_pci.c @@ -1,4 +1,4 @@ -/* $OpenBSD: if_aq_pci.c,v 1.21 2023/05/01 08:25:55 kettenis Exp $ */ +/* $OpenBSD: if_aq_pci.c,v 1.22 2023/05/02 12:32:22 kettenis Exp $ */ /* $NetBSD: if_aq.c,v 1.27 2021/06/16 00:21:18 riastradh Exp $ */ /* @@ -1970,7 +1970,7 @@ aq2_fw_reboot(struct aq_softc *sc) snprintf(buf, sizeof(buf), "(unknown 0x%08x)", v); break; } - printf(", Atlantic2 %s, F/W version %d.%d.%d\n", buf, + printf(", Atlantic2 %s, F/W version %d.%d.%d", buf, FW_VERSION_MAJOR(sc), FW_VERSION_MINOR(sc), FW_VERSION_BUILD(sc)); aq2_interface_buffer_read(sc, AQ2_FW_INTERFACE_OUT_FILTER_CAPS_REG, diff --git a/sys/dev/softraid_raid1c.c b/sys/dev/softraid_raid1c.c index 47ab5e227..bbd32c577 100644 --- a/sys/dev/softraid_raid1c.c +++ b/sys/dev/softraid_raid1c.c @@ -329,7 +329,7 @@ sr_raid1c_rw(struct sr_workunit *wu) if (sr_validate_io(wu, &blkno, "sr_raid1c_rw")) return (1); - + if (ISSET(wu->swu_xs->flags, SCSI_DATA_OUT) && !ISSET(wu->swu_flags, SR_WUF_REBUILD)) { mdd_raid1c = &wu->swu_dis->mds.mdd_raid1c; diff --git a/sys/dev/spdmem.c b/sys/dev/spdmem.c index 56691be5f..b10e6b358 100644 --- a/sys/dev/spdmem.c +++ b/sys/dev/spdmem.c @@ -673,7 +673,7 @@ spdmem_ddr3_decode(struct spdmem_softc *sc, struct spdmem *s) SPDMEM_DDR3_DATAWIDTH_PRIMASK; chipwidth = s->sm_data[SPDMEM_DDR3_MOD_ORG] & SPDMEM_DDR3_MOD_ORG_CHIPWIDTH_MASK; - physbanks = (s->sm_data[SPDMEM_DDR3_MOD_ORG] >> + physbanks = (s->sm_data[SPDMEM_DDR3_MOD_ORG] >> SPDMEM_DDR3_MOD_ORG_BANKS_SHIFT) & SPDMEM_DDR3_MOD_ORG_BANKS_MASK; dimm_size = (chipsize + 28 - 20) - 3 + (datawidth + 3) - @@ -691,7 +691,7 @@ spdmem_ddr3_decode(struct spdmem_softc *sc, struct spdmem *s) if (mtype == SPDMEM_DDR3_RDIMM || mtype == SPDMEM_DDR3_MINI_RDIMM) printf(" registered"); - if (s->sm_data[SPDMEM_DDR3_DATAWIDTH] & SPDMEM_DDR3_DATAWIDTH_ECCMASK) + if (s->sm_data[SPDMEM_DDR3_DATAWIDTH] & SPDMEM_DDR3_DATAWIDTH_ECCMASK) printf(" ECC"); dividend = s->sm_data[SPDMEM_DDR3_MTB_DIVIDEND]; @@ -759,7 +759,7 @@ spdmem_ddr4_decode(struct spdmem_softc *sc, struct spdmem *s) SPDMEM_DDR4_DATAWIDTH_PRIMASK; chipwidth = s->sm_data[SPDMEM_DDR4_MOD_ORG] & SPDMEM_DDR4_MOD_ORG_CHIPWIDTH_MASK; - physbanks = (s->sm_data[SPDMEM_DDR4_MOD_ORG] >> + physbanks = (s->sm_data[SPDMEM_DDR4_MOD_ORG] >> SPDMEM_DDR4_MOD_ORG_BANKS_SHIFT) & SPDMEM_DDR4_MOD_ORG_BANKS_MASK; if ((s->sm_data[SPDMEM_DDR4_PACK_TYPE] & @@ -796,7 +796,7 @@ spdmem_ddr4_decode(struct spdmem_softc *sc, struct spdmem *s) if (mtype == SPDMEM_DDR4_16B_SO_DIMM) printf(" 16-bit"); - if (s->sm_data[SPDMEM_DDR4_DATAWIDTH] & SPDMEM_DDR4_DATAWIDTH_ECCMASK) + if (s->sm_data[SPDMEM_DDR4_DATAWIDTH] & SPDMEM_DDR4_DATAWIDTH_ECCMASK) printf(" ECC"); mtb = s->sm_data[SPDMEM_DDR4_TCKMIN_MTB]; diff --git a/sys/lib/libz/zconf.h b/sys/lib/libz/zconf.h index 6e5605f0d..7bc5562f1 100644 --- a/sys/lib/libz/zconf.h +++ b/sys/lib/libz/zconf.h @@ -526,7 +526,7 @@ typedef uLong FAR uLongf; #if !defined(_WIN32) && defined(Z_LARGE64) # define z_off64_t off64_t #else -# if defined(_WIN32) && !defined(__GNUC__) && !defined(Z_SOLO) +# if defined(_WIN32) && !defined(__GNUC__) # define z_off64_t __int64 # else # define z_off64_t z_off_t diff --git a/sys/lib/libz/zlib.h b/sys/lib/libz/zlib.h index 062cfe6b6..547185ec7 100644 --- a/sys/lib/libz/zlib.h +++ b/sys/lib/libz/zlib.h @@ -729,7 +729,7 @@ ZEXTERN int ZEXPORT deflateParams(z_streamp strm, Then no more input data should be provided before the deflateParams() call. If this is done, the old level and strategy will be applied to the data compressed before deflateParams(), and the new level and strategy will be - applied to the the data compressed after deflateParams(). + applied to the data compressed after deflateParams(). deflateParams returns Z_OK on success, Z_STREAM_ERROR if the source stream state was inconsistent or if a parameter was invalid, or Z_BUF_ERROR if diff --git a/sys/netinet6/nd6.c b/sys/netinet6/nd6.c index 5e4d00e8b..a67096332 100644 --- a/sys/netinet6/nd6.c +++ b/sys/netinet6/nd6.c @@ -1,4 +1,4 @@ -/* $OpenBSD: nd6.c,v 1.272 2023/04/05 23:01:03 kn Exp $ */ +/* $OpenBSD: nd6.c,v 1.273 2023/05/02 06:06:13 bluhm Exp $ */ /* $KAME: nd6.c,v 1.280 2002/06/08 19:52:07 itojun Exp $ */ /* @@ -303,7 +303,8 @@ nd6_llinfo_timer(struct rtentry *rt) if (ln->ln_asked < nd6_mmaxtries) { ln->ln_asked++; nd6_llinfo_settimer(ln, RETRANS_TIMER / 1000); - nd6_ns_output(ifp, NULL, &dst->sin6_addr, ln, 0); + nd6_ns_output(ifp, NULL, &dst->sin6_addr, + &ln->ln_saddr6, 0); } else { struct mbuf_list ml; struct mbuf *m; @@ -336,6 +337,7 @@ nd6_llinfo_timer(struct rtentry *rt) ln = NULL; } break; + case ND6_LLINFO_REACHABLE: if (!ND6_LLINFO_PERMANENT(ln)) { ln->ln_state = ND6_LLINFO_STALE; @@ -357,14 +359,16 @@ nd6_llinfo_timer(struct rtentry *rt) ln->ln_asked = 1; ln->ln_state = ND6_LLINFO_PROBE; nd6_llinfo_settimer(ln, RETRANS_TIMER / 1000); - nd6_ns_output(ifp, &dst->sin6_addr, &dst->sin6_addr, ln, 0); + nd6_ns_output(ifp, &dst->sin6_addr, &dst->sin6_addr, + &ln->ln_saddr6, 0); break; + case ND6_LLINFO_PROBE: if (ln->ln_asked < nd6_umaxtries) { ln->ln_asked++; nd6_llinfo_settimer(ln, RETRANS_TIMER / 1000); - nd6_ns_output(ifp, &dst->sin6_addr, - &dst->sin6_addr, ln, 0); + nd6_ns_output(ifp, &dst->sin6_addr, &dst->sin6_addr, + &ln->ln_saddr6, 0); } else { nd6_free(rt); ln = NULL; @@ -1247,7 +1251,9 @@ nd6_resolve(struct ifnet *ifp, struct rtentry *rt0, struct mbuf *m, struct sockaddr_dl *sdl; struct rtentry *rt; struct llinfo_nd6 *ln = NULL; + struct in6_addr saddr6; time_t uptime; + int solicit = 0; if (m->m_flags & M_MCAST) { ETHER_MAP_IPV6_MULTICAST(&satosin6(dst)->sin6_addr, desten); @@ -1357,9 +1363,13 @@ nd6_resolve(struct ifnet *ifp, struct rtentry *rt0, struct mbuf *m, if (!ND6_LLINFO_PERMANENT(ln) && ln->ln_asked == 0) { ln->ln_asked++; nd6_llinfo_settimer(ln, RETRANS_TIMER / 1000); - nd6_ns_output(ifp, NULL, &satosin6(dst)->sin6_addr, ln, 0); + saddr6 = ln->ln_saddr6; + solicit = 1; } KERNEL_UNLOCK(); + + if (solicit) + nd6_ns_output(ifp, NULL, &satosin6(dst)->sin6_addr, &saddr6, 0); return (EAGAIN); bad: diff --git a/sys/netinet6/nd6.h b/sys/netinet6/nd6.h index 8e6a72263..e9dc93e99 100644 --- a/sys/netinet6/nd6.h +++ b/sys/netinet6/nd6.h @@ -1,4 +1,4 @@ -/* $OpenBSD: nd6.h,v 1.97 2023/04/05 21:51:47 bluhm Exp $ */ +/* $OpenBSD: nd6.h,v 1.98 2023/05/02 06:06:13 bluhm Exp $ */ /* $KAME: nd6.h,v 1.95 2002/06/08 11:31:06 itojun Exp $ */ /* @@ -141,7 +141,7 @@ void nd6_na_output(struct ifnet *, const struct in6_addr *, const struct in6_addr *, u_long, int, struct sockaddr *); void nd6_ns_input(struct mbuf *, int, int); void nd6_ns_output(struct ifnet *, const struct in6_addr *, - const struct in6_addr *, const struct llinfo_nd6 *, int); + const struct in6_addr *, const struct in6_addr *, int); caddr_t nd6_ifptomac(struct ifnet *); void nd6_dad_start(struct ifaddr *); void nd6_dad_stop(struct ifaddr *); diff --git a/sys/netinet6/nd6_nbr.c b/sys/netinet6/nd6_nbr.c index ab3c122d0..263671847 100644 --- a/sys/netinet6/nd6_nbr.c +++ b/sys/netinet6/nd6_nbr.c @@ -1,4 +1,4 @@ -/* $OpenBSD: nd6_nbr.c,v 1.146 2023/04/28 14:09:06 phessler Exp $ */ +/* $OpenBSD: nd6_nbr.c,v 1.147 2023/05/02 06:06:13 bluhm Exp $ */ /* $KAME: nd6_nbr.c,v 1.61 2001/02/10 16:06:14 jinmei Exp $ */ /* @@ -360,7 +360,7 @@ nd6_ns_input(struct mbuf *m, int off, int icmp6len) */ void nd6_ns_output(struct ifnet *ifp, const struct in6_addr *daddr6, - const struct in6_addr *taddr6, const struct llinfo_nd6 *ln, int dad) + const struct in6_addr *taddr6, const struct in6_addr *saddr6, int dad) { struct mbuf *m; struct ip6_hdr *ip6; @@ -423,7 +423,7 @@ nd6_ns_output(struct ifnet *ifp, const struct in6_addr *daddr6, bzero(&dst_sa, sizeof(dst_sa)); src_sa.sin6_family = dst_sa.sin6_family = AF_INET6; src_sa.sin6_len = dst_sa.sin6_len = sizeof(struct sockaddr_in6); - if (daddr6) + if (daddr6 != NULL) dst_sa.sin6_addr = *daddr6; else { dst_sa.sin6_addr.s6_addr16[0] = __IPV6_ADDR_INT16_MLL; @@ -451,14 +451,13 @@ nd6_ns_output(struct ifnet *ifp, const struct in6_addr *daddr6, * - if taddr is link local saddr6 must be link local as well * Otherwise, we perform the source address selection as usual. */ - if (ln != NULL) - src_sa.sin6_addr = ln->ln_saddr6; + if (saddr6 != NULL) + src_sa.sin6_addr = *saddr6; if (!IN6_IS_ADDR_LINKLOCAL(taddr6) || IN6_IS_ADDR_UNSPECIFIED(&src_sa.sin6_addr) || IN6_IS_ADDR_LINKLOCAL(&src_sa.sin6_addr) || !in6ifa_ifpwithaddr(ifp, &src_sa.sin6_addr)) { - struct rtentry *rt; rt = rtalloc(sin6tosa(&dst_sa), RT_RESOLVE, diff --git a/usr.bin/wall/ttymsg.c b/usr.bin/wall/ttymsg.c index af279ddfb..c1570e20d 100644 --- a/usr.bin/wall/ttymsg.c +++ b/usr.bin/wall/ttymsg.c @@ -1,4 +1,4 @@ -/* $OpenBSD: ttymsg.c,v 1.20 2021/10/24 21:24:17 deraadt Exp $ */ +/* $OpenBSD: ttymsg.c,v 1.21 2023/05/02 09:51:22 tb Exp $ */ /* $NetBSD: ttymsg.c,v 1.3 1994/11/17 07:17:55 jtc Exp $ */ /* @@ -54,11 +54,7 @@ char *ttymsg(struct iovec *, int, char *, int); * ignored (exclusive-use, lack of permission, etc.). */ char * -ttymsg(iov, iovcnt, line, tmout) - struct iovec *iov; - int iovcnt; - char *line; - int tmout; +ttymsg(struct iovec *iov, int iovcnt, char *line, int tmout) { static char device[MAXNAMLEN] = _PATH_DEV; static char errbuf[1024]; diff --git a/usr.sbin/vmctl/vmctl.c b/usr.sbin/vmctl/vmctl.c index 66b7d2718..9f323b677 100644 --- a/usr.sbin/vmctl/vmctl.c +++ b/usr.sbin/vmctl/vmctl.c @@ -1,4 +1,4 @@ -/* $OpenBSD: vmctl.c,v 1.87 2023/04/28 19:46:41 dv Exp $ */ +/* $OpenBSD: vmctl.c,v 1.88 2023/05/02 13:02:51 jsg Exp $ */ /* * Copyright (c) 2014 Mike Larkin @@ -202,7 +202,7 @@ vm_start(uint32_t start_id, const char *name, size_t memsize, int nnics, imsg_compose(ibuf, IMSG_VMDOP_START_VM_REQUEST, 0, 0, vmc->vmc_kernel, vmc, sizeof(struct vmop_create_params)); - free(vcp); + free(vmc); return (0); }