sync with OpenBSD -current
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GPG Key ID:
F42C07F07E2E35B7
@ -1,4 +1,4 @@
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/* $OpenBSD: identcpu.c,v 1.144 2024/06/16 14:01:26 kn Exp $ */
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/* $OpenBSD: identcpu.c,v 1.145 2024/06/24 21:22:14 bluhm Exp $ */
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/* $NetBSD: identcpu.c,v 1.1 2003/04/26 18:39:28 fvdl Exp $ */
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/*
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@ -66,6 +66,7 @@ char cpu_model[48];
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int cpuspeed;
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int amd64_has_xcrypt;
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int amd64_pos_cbit;
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int has_rdrand;
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int has_rdseed;
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@ -695,6 +696,22 @@ identifycpu(struct cpu_info *ci)
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printf("\n%s: MELTDOWN", ci->ci_dev->dv_xname);
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}
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/* AMD secure memory encryption and encrypted virtualization features */
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if (ci->ci_vendor == CPUV_AMD &&
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ci->ci_pnfeatset >= CPUID_AMD_SEV_CAP) {
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CPUID(CPUID_AMD_SEV_CAP, ci->ci_feature_amdsev_eax,
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ci->ci_feature_amdsev_ebx, ci->ci_feature_amdsev_ecx,
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ci->ci_feature_amdsev_edx);
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pcpuid3(ci, "8000001F",
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'a', CPUID_MEMBER(ci_feature_amdsev_eax),
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CPUID_AMDSEV_EAX_BITS,
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'c', CPUID_MEMBER(ci_feature_amdsev_ecx),
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CPUID_AMDSEV_ECX_BITS,
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'd', CPUID_MEMBER(ci_feature_amdsev_edx),
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CPUID_AMDSEV_EDX_BITS);
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amd64_pos_cbit = (ci->ci_feature_amdsev_ebx & 0x3f);
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}
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printf("\n");
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replacemeltdown();
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@ -1,4 +1,4 @@
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/* $OpenBSD: cpu.h,v 1.173 2024/06/09 21:15:29 jca Exp $ */
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/* $OpenBSD: cpu.h,v 1.174 2024/06/24 21:22:14 bluhm Exp $ */
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/* $NetBSD: cpu.h,v 1.1 2003/04/26 18:39:39 fvdl Exp $ */
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/*-
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@ -170,6 +170,10 @@ struct cpu_info {
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u_int32_t ci_feature_sefflags_ecx;/* [I] */
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u_int32_t ci_feature_sefflags_edx;/* [I] */
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u_int32_t ci_feature_amdspec_ebx; /* [I] */
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u_int32_t ci_feature_amdsev_eax; /* [I] */
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u_int32_t ci_feature_amdsev_ebx; /* [I] */
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u_int32_t ci_feature_amdsev_ecx; /* [I] */
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u_int32_t ci_feature_amdsev_edx; /* [I] */
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u_int32_t ci_feature_tpmflags; /* [I] */
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u_int32_t ci_pnfeatset; /* [I] */
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u_int32_t ci_efeature_eax; /* [I] */
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@ -1,4 +1,4 @@
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/* $OpenBSD: specialreg.h,v 1.112 2024/05/11 19:21:47 guenther Exp $ */
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/* $OpenBSD: specialreg.h,v 1.113 2024/06/24 21:22:14 bluhm Exp $ */
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/* $NetBSD: specialreg.h,v 1.1 2003/04/26 18:39:48 fvdl Exp $ */
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/* $NetBSD: x86/specialreg.h,v 1.2 2003/04/25 21:54:30 fvdl Exp $ */
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@ -395,6 +395,47 @@
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"\022STIBP_ALL" "\023IBRS_PREF" "\024IBRS_SM" "\031SSBD" "\032VIRTSSBD" \
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"\033SSBDNR" )
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/*
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* AMD CPUID function 0x8000001F EAX bits
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*/
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#define CPUIDEAX_SME (1ULL << 0) /* SME */
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#define CPUIDEAX_SEV (1ULL << 1) /* SEV */
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#define CPUIDEAX_PFLUSH_MSR (1ULL << 2) /* Page Flush MSR */
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#define CPUIDEAX_SEVES (1ULL << 3) /* SEV-ES */
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#define CPUIDEAX_SEVSNP (1ULL << 4) /* SEV-SNP */
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#define CPUIDEAX_VMPL (1ULL << 5) /* VM Permission Levels */
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#define CPUIDEAX_RMPQUERY (1ULL << 6) /* RMPQUERY */
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#define CPUIDEAX_VMPLSSS (1ULL << 7) /* VMPL Supservisor Shadow Stack */
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#define CPUIDEAX_SECTSC (1ULL << 8) /* Secure TSC */
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#define CPUIDEAX_TSCAUXVIRT (1ULL << 9) /* TSC Aux Virtualization */
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#define CPUIDEAX_HWECACHECOH (1ULL << 10) /* Coherency Across Enc. Domains */
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#define CPUIDEAX_64BITHOST (1ULL << 11) /* SEV guest requires 64bit host */
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#define CPUIDEAX_RESTINJ (1ULL << 12) /* Restricted Injection */
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#define CPUIDEAX_ALTINJ (1ULL << 13) /* Alternate Injection */
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#define CPUIDEAX_DBGSTSW (1ULL << 14) /* Full debug state swap */
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#define CPUIDEAX_IBSDISALLOW (1ULL << 15) /* Disallowing IBS use by host */
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#define CPUIDEAX_VTE (1ULL << 16) /* Virt. Transparent Encryption */
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#define CPUIDEAX_VMGEXITPARAM (1ULL << 17) /* VMGEXIT Parameter */
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#define CPUIDEAX_VTOMMSR (1ULL << 18) /* Virtual TOM MSR */
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#define CPUIDEAX_IBSVIRT (1ULL << 19) /* IBS Virtualization for SEV-ES */
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#define CPUIDEAX_VMSARPROT (1ULL << 24) /* VMSA Register Protection */
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#define CPUIDEAX_SMTPROT (1ULL << 25) /* SMT Protection */
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#define CPUIDEAX_SVSMPAGEMSR (1ULL << 28) /* SVSM Communication Page MSR */
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#define CPUIDEAX_NVSMSR (1ULL << 29) /* NestedVirtSnpMsr */
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#define CPUID_AMDSEV_EAX_BITS \
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("\20" "\01SME" "\02SEV" "\03PFLUSH_MSR" "\04SEVES" "\05SEVSNP" "\06VMPL" \
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"\07RMPQUERY" "\010VMPLSSS" "\011SECTSC" "\012TSCAUXVIRT" \
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"\013HWECACHECOH" "\014REQ64BITHOST" "\015RESTINJ" "\016ALTINJ" \
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"\017DBGSTSW" "\020IBSDISALLOW" "\021VTE" "\022VMGEXITPARAM" \
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"\023VTOMMSR" "\024IBSVIRT" "\031VMSARPROT" "\032SMTPROT" \
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"\035SVSMPAGEMSR" "\036NVSMSR" )
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/* Number of encrypted guests */
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#define CPUID_AMDSEV_ECX_BITS ("\20")
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/* Minimum ASID for SEV enabled, SEV-ES disabled guest. */
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#define CPUID_AMDSEV_EDX_BITS ("\20")
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#define CPUID2FAMILY(cpuid) (((cpuid) >> 8) & 15)
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#define CPUID2MODEL(cpuid) (((cpuid) >> 4) & 15)
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#define CPUID2STEPPING(cpuid) ((cpuid) & 15)
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@ -1547,6 +1588,13 @@
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#define SVM_INTERCEPT_CR14_WRITE_POST (1UL << 30)
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#define SVM_INTERCEPT_CR15_WRITE_POST (1UL << 31)
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/*
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* SME and SEV
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*/
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#define CPUID_AMD_SEV_CAP 0x8000001F
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#define AMD_SME_CAP (1UL << 0)
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#define AMD_SEV_CAP (1UL << 1)
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/*
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* PAT
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*/
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