102 lines
2.6 KiB
ArmAsm
102 lines
2.6 KiB
ArmAsm
#if defined(__SUNPRO_C) && defined(__sparcv9)
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# define ABI64 /* They've said -xarch=v9 at command line */
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#elif defined(__GNUC__) && defined(__arch64__)
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# define ABI64 /* They've said -m64 at command line */
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#endif
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#ifdef ABI64
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.register %g2,#scratch
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.register %g3,#scratch
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# define FRAME -192
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# define BIAS 2047
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#else
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# define FRAME -96
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# define BIAS 0
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#endif
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.global _sparcv9_vis1_probe
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.align 8
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_sparcv9_vis1_probe:
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add %sp,BIAS+2,%o1
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.word 0xc19a5a40 !ldda [%o1]ASI_FP16_P,%f0
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retl
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.word 0x81b00d80 !fxor %f0,%f0,%f0
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.type _sparcv9_vis1_probe,#function
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.size _sparcv9_vis1_probe,.-_sparcv9_vis1_probe
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! Probe and instrument VIS1 instruction. Output is number of cycles it
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! takes to execute rdtick and pair of VIS1 instructions. US-Tx VIS unit
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! is slow (documented to be 6 cycles on T2) and the core is in-order
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! single-issue, it should be possible to distinguish Tx reliably...
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! Observed return values are:
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!
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! UltraSPARC IIe 7
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! UltraSPARC III 7
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! UltraSPARC T1 24
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!
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! Numbers for T2 and SPARC64 V-VII are more than welcomed.
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!
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! It would be possible to detect specifically US-T1 by instrumenting
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! fmul8ulx16, which is emulated on T1 and as such accounts for quite
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! a lot of %tick-s, couple of thousand on Linux...
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.global _sparcv9_vis1_instrument
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.align 8
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_sparcv9_vis1_instrument:
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.word 0x91410000 !rd %tick,%o0
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.word 0x81b00d80 !fxor %f0,%f0,%f0
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.word 0x85b08d82 !fxor %f2,%f2,%f2
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.word 0x93410000 !rd %tick,%o1
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.word 0x81b00d80 !fxor %f0,%f0,%f0
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.word 0x85b08d82 !fxor %f2,%f2,%f2
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.word 0x95410000 !rd %tick,%o2
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.word 0x81b00d80 !fxor %f0,%f0,%f0
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.word 0x85b08d82 !fxor %f2,%f2,%f2
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.word 0x97410000 !rd %tick,%o3
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.word 0x81b00d80 !fxor %f0,%f0,%f0
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.word 0x85b08d82 !fxor %f2,%f2,%f2
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.word 0x99410000 !rd %tick,%o4
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! calculate intervals
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sub %o1,%o0,%o0
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sub %o2,%o1,%o1
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sub %o3,%o2,%o2
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sub %o4,%o3,%o3
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! find minimum value
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cmp %o0,%o1
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.word 0x38680002 !bgu,a %xcc,.+8
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mov %o1,%o0
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cmp %o0,%o2
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.word 0x38680002 !bgu,a %xcc,.+8
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mov %o2,%o0
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cmp %o0,%o3
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.word 0x38680002 !bgu,a %xcc,.+8
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mov %o3,%o0
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retl
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nop
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.type _sparcv9_vis1_instrument,#function
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.size _sparcv9_vis1_instrument,.-_sparcv9_vis1_instrument
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.global _sparcv9_vis2_probe
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.align 8
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_sparcv9_vis2_probe:
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retl
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.word 0x81b00980 !bshuffle %f0,%f0,%f0
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.type _sparcv9_vis2_probe,#function
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.size _sparcv9_vis2_probe,.-_sparcv9_vis2_probe
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.global _sparcv9_fmadd_probe
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.align 8
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_sparcv9_fmadd_probe:
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.word 0x81b00d80 !fxor %f0,%f0,%f0
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.word 0x85b08d82 !fxor %f2,%f2,%f2
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retl
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.word 0x81b80440 !fmaddd %f0,%f0,%f2,%f0
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.type _sparcv9_fmadd_probe,#function
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.size _sparcv9_fmadd_probe,.-_sparcv9_fmadd_probe
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.section ".init",#alloc,#execinstr
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call OPENSSL_cpuid_setup
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nop
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