148 lines
3.2 KiB
Raku
148 lines
3.2 KiB
Raku
#!/usr/bin/env perl
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$flavour = shift;
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$output = shift;
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if ($flavour =~ /\./) { $output = $flavour; undef $flavour; }
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$0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
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( $xlate="${dir}x86_64-xlate.pl" and -f $xlate ) or
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( $xlate="${dir}perlasm/x86_64-xlate.pl" and -f $xlate) or
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die "can't locate x86_64-xlate.pl";
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open OUT,"| \"$^X\" $xlate $flavour $output";
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*STDOUT=*OUT;
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($arg1,$arg2,$arg3,$arg4)=("%rdi","%rsi","%rdx","%rcx"); # Unix order
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print<<___;
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.text
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.globl OPENSSL_ia32_cpuid
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.type OPENSSL_ia32_cpuid,\@abi-omnipotent
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.align 16
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OPENSSL_ia32_cpuid:
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_CET_ENDBR
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mov %rbx,%r8 # save %rbx
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xor %eax,%eax
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cpuid
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mov %eax,%r11d # max value for standard query level
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xor %eax,%eax
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cmp \$0x756e6547,%ebx # "Genu"
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setne %al
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mov %eax,%r9d
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cmp \$0x49656e69,%edx # "ineI"
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setne %al
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or %eax,%r9d
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cmp \$0x6c65746e,%ecx # "ntel"
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setne %al
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or %eax,%r9d # 0 indicates Intel CPU
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jz .Lintel
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cmp \$0x68747541,%ebx # "Auth"
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setne %al
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mov %eax,%r10d
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cmp \$0x69746E65,%edx # "enti"
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setne %al
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or %eax,%r10d
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cmp \$0x444D4163,%ecx # "cAMD"
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setne %al
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or %eax,%r10d # 0 indicates AMD CPU
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jnz .Lintel
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# AMD specific
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mov \$0x80000000,%eax
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cpuid
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cmp \$0x80000001,%eax
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jb .Lintel
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mov %eax,%r10d
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mov \$0x80000001,%eax
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cpuid
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or %ecx,%r9d
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and \$IA32CAP_MASK1_AMD_XOP,%r9d # isolate AMD XOP bit
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or \$1,%r9d # make sure %r9d is not zero
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cmp \$0x80000008,%r10d
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jb .Lintel
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mov \$0x80000008,%eax
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cpuid
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movzb %cl,%r10 # number of cores - 1
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inc %r10 # number of cores
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mov \$1,%eax
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cpuid
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bt \$IA32CAP_BIT0_HT,%edx # test hyper-threading bit
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jnc .Lgeneric
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shr \$16,%ebx # number of logical processors
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cmp %r10b,%bl
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ja .Lgeneric
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xor \$IA32CAP_MASK0_HT,%edx
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jmp .Lgeneric
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.Lintel:
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cmp \$4,%r11d
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mov \$-1,%r10d
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jb .Lnocacheinfo
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mov \$4,%eax
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mov \$0,%ecx # query L1D
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cpuid
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mov %eax,%r10d
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shr \$14,%r10d
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and \$0xfff,%r10d # number of cores -1 per L1D
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.Lnocacheinfo:
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mov \$1,%eax
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cpuid
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# force reserved bits to 0
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and \$(~(IA32CAP_MASK0_INTELP4 | IA32CAP_MASK0_INTEL)),%edx
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cmp \$0,%r9d
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jne .Lnotintel
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# set reserved bit#30 on Intel CPUs
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or \$IA32CAP_MASK0_INTEL,%edx
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and \$15,%ah
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cmp \$15,%ah # examine Family ID
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jne .Lnotintel
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# set reserved bit#20 to engage RC4_CHAR
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or \$IA32CAP_MASK0_INTELP4,%edx
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.Lnotintel:
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bt \$IA32CAP_BIT0_HT,%edx # test hyper-threading bit
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jnc .Lgeneric
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xor \$IA32CAP_MASK0_HT,%edx
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cmp \$0,%r10d
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je .Lgeneric
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or \$IA32CAP_MASK0_HT,%edx
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shr \$16,%ebx
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cmp \$1,%bl # see if cache is shared
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ja .Lgeneric
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xor \$IA32CAP_MASK0_HT,%edx # clear hyper-threading bit if not
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.Lgeneric:
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and \$IA32CAP_MASK1_AMD_XOP,%r9d # isolate AMD XOP flag
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and \$(~IA32CAP_MASK1_AMD_XOP),%ecx
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or %ecx,%r9d # merge AMD XOP flag
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mov %edx,%r10d # %r9d:%r10d is copy of %ecx:%edx
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bt \$IA32CAP_BIT1_OSXSAVE,%r9d # check OSXSAVE bit
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jnc .Lclear_avx
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xor %ecx,%ecx # XCR0
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.byte 0x0f,0x01,0xd0 # xgetbv
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and \$6,%eax # isolate XMM and YMM state support
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cmp \$6,%eax
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je .Ldone
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.Lclear_avx:
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mov \$(~(IA32CAP_MASK1_AVX | IA32CAP_MASK1_FMA3 | IA32CAP_MASK1_AMD_XOP)),%eax
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and %eax,%r9d # clear AVX, FMA and AMD XOP bits
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.Ldone:
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shl \$32,%r9
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mov %r10d,%eax
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mov %r8,%rbx # restore %rbx
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or %r9,%rax
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ret
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.size OPENSSL_ia32_cpuid,.-OPENSSL_ia32_cpuid
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___
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close STDOUT; # flush
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