154 lines
3.8 KiB
Raku
154 lines
3.8 KiB
Raku
#!/usr/bin/env perl
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$0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
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push(@INC, "${dir}perlasm", "perlasm");
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require "x86asm.pl";
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&asm_init($ARGV[0],"x86cpuid");
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for (@ARGV) { $sse2=1 if (/-DOPENSSL_IA32_SSE2/); }
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&function_begin("OPENSSL_ia32_cpuid");
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&xor ("edx","edx");
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&pushf ();
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&pop ("eax");
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&mov ("ecx","eax");
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&xor ("eax",1<<21);
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&push ("eax");
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&popf ();
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&pushf ();
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&pop ("eax");
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&xor ("ecx","eax");
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&xor ("eax","eax");
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&bt ("ecx",21);
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&jnc (&label("nocpuid"));
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&cpuid ();
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&mov ("edi","eax"); # max value for standard query level
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&xor ("eax","eax");
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&cmp ("ebx",0x756e6547); # "Genu"
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&setne (&LB("eax"));
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&mov ("ebp","eax");
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&cmp ("edx",0x49656e69); # "ineI"
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&setne (&LB("eax"));
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&or ("ebp","eax");
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&cmp ("ecx",0x6c65746e); # "ntel"
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&setne (&LB("eax"));
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&or ("ebp","eax"); # 0 indicates Intel CPU
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&jz (&label("intel"));
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&cmp ("ebx",0x68747541); # "Auth"
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&setne (&LB("eax"));
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&mov ("esi","eax");
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&cmp ("edx",0x69746E65); # "enti"
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&setne (&LB("eax"));
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&or ("esi","eax");
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&cmp ("ecx",0x444D4163); # "cAMD"
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&setne (&LB("eax"));
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&or ("esi","eax"); # 0 indicates AMD CPU
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&jnz (&label("intel"));
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# AMD specific
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&mov ("eax",0x80000000);
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&cpuid ();
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&cmp ("eax",0x80000001);
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&jb (&label("intel"));
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&mov ("esi","eax");
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&mov ("eax",0x80000001);
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&cpuid ();
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&and ("ecx","\$IA32CAP_MASK1_AMD_XOP"); # isolate AMD XOP bit
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&or ("ecx",1); # make sure ecx is not zero
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&mov ("ebp","ecx");
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&cmp ("esi",0x80000008);
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&jb (&label("intel"));
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&mov ("eax",0x80000008);
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&cpuid ();
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&movz ("esi",&LB("ecx")); # number of cores - 1
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&inc ("esi"); # number of cores
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&mov ("eax",1);
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&xor ("ecx","ecx");
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&cpuid ();
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&bt ("edx","\$IA32CAP_BIT0_HT");
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&jnc (&label("generic"));
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&shr ("ebx",16);
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&and ("ebx",0xff);
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&cmp ("ebx","esi");
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&ja (&label("generic"));
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&xor ("edx","\$IA32CAP_MASK0_HT"); # clear hyper-threading bit
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&jmp (&label("generic"));
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&set_label("intel");
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&cmp ("edi",4);
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&mov ("edi",-1);
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&jb (&label("nocacheinfo"));
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&mov ("eax",4);
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&mov ("ecx",0); # query L1D
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&cpuid ();
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&mov ("edi","eax");
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&shr ("edi",14);
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&and ("edi",0xfff); # number of cores -1 per L1D
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&set_label("nocacheinfo");
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&mov ("eax",1);
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&xor ("ecx","ecx");
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&cpuid ();
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# force reserved bits to 0.
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&and ("edx","\$~(IA32CAP_MASK0_INTELP4 | IA32CAP_MASK0_INTEL)");
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&cmp ("ebp",0);
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&jne (&label("notintel"));
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# set reserved bit#30 on Intel CPUs
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&or ("edx","\$IA32CAP_MASK0_INTEL");
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&and (&HB("eax"),15); # family ID
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&cmp (&HB("eax"),15); # P4?
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&jne (&label("notintel"));
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# set reserved bit#20 to engage RC4_CHAR
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&or ("edx","\$IA32CAP_MASK0_INTELP4");
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&set_label("notintel");
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&bt ("edx","\$IA32CAP_BIT0_HT"); # test hyper-threading bit
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&jnc (&label("generic"));
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&xor ("edx","\$IA32CAP_MASK0_HT");
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&cmp ("edi",0);
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&je (&label("generic"));
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&or ("edx","\$IA32CAP_MASK0_HT");
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&shr ("ebx",16);
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&cmp (&LB("ebx"),1); # see if cache is shared
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&ja (&label("generic"));
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&xor ("edx","\$IA32CAP_MASK0_HT"); # clear hyper-threading bit if not
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&set_label("generic");
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&and ("ebp","\$IA32CAP_MASK1_AMD_XOP"); # isolate AMD XOP flag
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# force reserved bits to 0.
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&and ("ecx","\$~IA32CAP_MASK1_AMD_XOP");
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&mov ("esi","edx");
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&or ("ebp","ecx"); # merge AMD XOP flag
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&bt ("ecx","\$IA32CAP_BIT1_OSXSAVE"); # check OSXSAVE bit
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&jnc (&label("clear_avx"));
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&xor ("ecx","ecx");
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&data_byte(0x0f,0x01,0xd0); # xgetbv
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&and ("eax",6);
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&cmp ("eax",6);
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&je (&label("done"));
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&cmp ("eax",2);
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&je (&label("clear_avx"));
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&set_label("clear_xmm");
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# clear AESNI and PCLMULQDQ bits.
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&and ("ebp","\$~(IA32CAP_MASK1_AESNI | IA32CAP_MASK1_PCLMUL)");
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# clear FXSR.
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&and ("esi","\$~IA32CAP_MASK0_FXSR");
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&set_label("clear_avx");
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# clear AVX, FMA3 and AMD XOP bits.
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&and ("ebp","\$~(IA32CAP_MASK1_AVX | IA32CAP_MASK1_FMA3 | IA32CAP_MASK1_AMD_XOP)");
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&set_label("done");
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&mov ("eax","esi");
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&mov ("edx","ebp");
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&set_label("nocpuid");
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&function_end("OPENSSL_ia32_cpuid");
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&asm_finish();
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