354 lines
8.7 KiB
C
354 lines
8.7 KiB
C
/* $OpenBSD: ccpmic.c,v 1.3 2022/04/06 18:59:27 naddy Exp $ */
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/*
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* Copyright (c) 2018 Mark Kettenis <kettenis@openbsd.org>
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <dev/acpi/acpireg.h>
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#include <dev/acpi/acpivar.h>
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#include <dev/acpi/acpidev.h>
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#include <dev/acpi/amltypes.h>
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#include <dev/acpi/dsdt.h>
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#include <dev/i2c/i2cvar.h>
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#define CCPMIC_GPIO0P0CTLO 0x2b
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#define CCPMIC_GPIO0P0CTLI 0x33
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#define CCPMIC_GPIO1P0CTLO 0x3b
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#define CCPMIC_GPIO1P0CTLI 0x43
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#define CCPMIC_GPIOPANELCTL 0x52
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#define CCPMIC_GPIOCTLO_RVAL_2KUP (1 << 1)
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#define CCPMIC_GPIOCTLO_DRV_REN (1 << 3)
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#define CCPMIC_GPIOCTLO_DIR_OUT (1 << 5)
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#define CCPMIC_GPIOCTLI_VALUE (1 << 0)
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#define CCPMIC_GPIOCTLO_INPUT \
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(CCPMIC_GPIOCTLO_DRV_REN | CCPMIC_GPIOCTLO_RVAL_2KUP)
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#define CCPMIC_GPIOCTLO_OUTPUT \
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(CCPMIC_GPIOCTLO_INPUT | CCPMIC_GPIOCTLO_DIR_OUT)
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#define CCPMIC_V1P8SX 0x5d
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#define CCPMIC_V1P2SX 0x61
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#define CCPMIC_V2P85SX 0x66
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#define CCPMIC_PWR_ON (1 << 0)
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#define CCPMIC_PWR_SEL (1 << 1)
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#define CCPMIC_SYS2_THRM_RSLT_H 0x78
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#define CCPMIC_SYS2_THRM_RSLT_L 0x79
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#define CCPMIC_REGIONSPACE_THERMAL 0x8c
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#define CCPMIC_REGIONSPACE_POWER 0x8d
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#define CCPMIC_NPINS 16
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struct acpi_lpat {
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int32_t temp;
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int32_t raw;
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};
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struct ccpmic_softc {
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struct device sc_dev;
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struct acpi_softc *sc_acpi;
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struct aml_node *sc_node;
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i2c_tag_t sc_tag;
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i2c_addr_t sc_addr;
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struct acpi_lpat *sc_lpat;
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size_t sc_lpat_len;
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struct acpi_gpio sc_gpio;
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};
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int ccpmic_match(struct device *, void *, void *);
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void ccpmic_attach(struct device *, struct device *, void *);
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const struct cfattach ccpmic_ca = {
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sizeof(struct ccpmic_softc), ccpmic_match, ccpmic_attach
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};
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struct cfdriver ccpmic_cd = {
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NULL, "ccpmic", DV_DULL
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};
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uint8_t ccpmic_read_1(struct ccpmic_softc *, uint8_t, int);
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void ccpmic_write_1(struct ccpmic_softc *, uint8_t, uint8_t, int);
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void ccpmic_get_lpat(struct ccpmic_softc *);
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int32_t ccpmic_raw_to_temp(struct ccpmic_softc *, int32_t);
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int ccpmic_thermal_opreg_handler(void *, int, uint64_t, int, uint64_t *);
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int ccpmic_power_opreg_handler(void *, int, uint64_t, int, uint64_t *);
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int ccpmic_read_pin(void *, int);
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void ccpmic_write_pin(void *, int, int);
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int
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ccpmic_match(struct device *parent, void *match, void *aux)
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{
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struct i2c_attach_args *ia = aux;
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return (strcmp(ia->ia_name, "INT33FD") == 0);
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}
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void
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ccpmic_attach(struct device *parent, struct device *self, void *aux)
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{
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struct ccpmic_softc *sc = (struct ccpmic_softc *)self;
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struct i2c_attach_args *ia = aux;
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sc->sc_tag = ia->ia_tag;
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sc->sc_addr = ia->ia_addr;
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sc->sc_acpi = acpi_softc;
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sc->sc_node = ia->ia_cookie;
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printf("\n");
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ccpmic_get_lpat(sc);
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if (sc->sc_lpat == NULL)
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return;
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sc->sc_gpio.cookie = sc;
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sc->sc_gpio.read_pin = ccpmic_read_pin;
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sc->sc_gpio.write_pin = ccpmic_write_pin;
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sc->sc_node->gpio = &sc->sc_gpio;
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acpi_register_gpio(sc->sc_acpi, sc->sc_node);
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/* Register OEM defined address space. */
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aml_register_regionspace(sc->sc_node, CCPMIC_REGIONSPACE_THERMAL,
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sc, ccpmic_thermal_opreg_handler);
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aml_register_regionspace(sc->sc_node, CCPMIC_REGIONSPACE_POWER,
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sc, ccpmic_power_opreg_handler);
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}
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uint8_t
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ccpmic_read_1(struct ccpmic_softc *sc, uint8_t reg, int flags)
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{
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uint8_t val;
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int error;
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iic_acquire_bus(sc->sc_tag, flags);
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error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_addr,
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®, sizeof(reg), &val, sizeof(val), flags);
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iic_release_bus(sc->sc_tag, flags);
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if (error) {
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printf("%s: can't read register 0x%02x\n",
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sc->sc_dev.dv_xname, reg);
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val = 0xff;
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}
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return val;
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}
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void
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ccpmic_write_1(struct ccpmic_softc *sc, uint8_t reg, uint8_t val, int flags)
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{
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int error;
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iic_acquire_bus(sc->sc_tag, flags);
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error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, sc->sc_addr,
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®, sizeof(reg), &val, sizeof(val), flags);
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iic_release_bus(sc->sc_tag, flags);
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if (error) {
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printf("%s: can't write register 0x%02x\n",
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sc->sc_dev.dv_xname, reg);
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}
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}
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void
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ccpmic_get_lpat(struct ccpmic_softc *sc)
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{
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struct aml_value res;
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int i;
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if (aml_evalname(sc->sc_acpi, sc->sc_node, "LPAT", 0, NULL, &res))
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return;
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if (res.type != AML_OBJTYPE_PACKAGE)
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goto out;
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if (res.length < 4 || (res.length % 2) != 0)
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goto out;
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sc->sc_lpat_len = res.length / 2;
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sc->sc_lpat = mallocarray(sc->sc_lpat_len, sizeof(struct acpi_lpat),
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M_DEVBUF, M_WAITOK);
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for (i = 0; i < sc->sc_lpat_len; i++) {
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sc->sc_lpat[i].temp = aml_val2int(res.v_package[2 * i]);
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sc->sc_lpat[i].raw = aml_val2int(res.v_package[2 * i + 1]);
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}
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out:
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aml_freevalue(&res);
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}
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int32_t
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ccpmic_raw_to_temp(struct ccpmic_softc *sc, int32_t raw)
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{
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struct acpi_lpat *lpat = sc->sc_lpat;
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int32_t raw0, delta_raw;
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int32_t temp0, delta_temp;
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int i;
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for (i = 1; i < sc->sc_lpat_len; i++) {
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/* Coefficient can be positive or negative. */
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if (raw >= lpat[i - 1].raw && raw <= lpat[i].raw)
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break;
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if (raw <= lpat[i - 1].raw && raw >= lpat[i].raw)
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break;
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}
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if (i == sc->sc_lpat_len)
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return -1;
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raw0 = lpat[i - 1].raw;
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temp0 = lpat[i - 1].temp;
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delta_raw = lpat[i].raw - raw0;
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delta_temp = lpat[i].temp - temp0;
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return temp0 + (raw - raw0) * delta_temp / delta_raw;
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}
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struct ccpmic_regmap {
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uint8_t address;
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uint8_t hi, lo;
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};
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struct ccpmic_regmap ccpmic_thermal_regmap[] = {
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{ 0x18, CCPMIC_SYS2_THRM_RSLT_H, CCPMIC_SYS2_THRM_RSLT_L }, /* TMP2 */
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};
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int
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ccpmic_thermal_opreg_handler(void *cookie, int iodir, uint64_t address,
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int size, uint64_t *value)
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{
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struct ccpmic_softc *sc = cookie;
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int32_t temp;
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uint16_t raw;
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uint8_t lo, hi;
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int i;
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/* Only allow 32-bit read access. */
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if (size != 4 || iodir != ACPI_IOREAD)
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return -1;
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for (i = 0; i < nitems(ccpmic_thermal_regmap); i++) {
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if (address == ccpmic_thermal_regmap[i].address)
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break;
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}
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if (i == nitems(ccpmic_thermal_regmap)) {
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printf("%s: addr 0x%02llx\n", __func__, address);
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return -1;
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}
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lo = ccpmic_thermal_regmap[i].lo;
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hi = ccpmic_thermal_regmap[i].hi;
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raw = ccpmic_read_1(sc, lo, 0);
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raw |= (ccpmic_read_1(sc, hi, 0) & 0x03) << 8;
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temp = ccpmic_raw_to_temp(sc, raw);
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if (temp < 0)
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return -1;
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*value = temp;
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return 0;
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}
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struct ccpmic_regmap ccpmic_power_regmap[] = {
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{ 0x24, CCPMIC_V2P85SX }, /* X285 */
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{ 0x48, CCPMIC_V1P8SX }, /* V18X */
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{ 0x50, CCPMIC_V1P2SX }, /* V12X */
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};
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int
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ccpmic_power_opreg_handler(void *cookie, int iodir, uint64_t address,
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int size, uint64_t *value)
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{
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struct ccpmic_softc *sc = cookie;
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uint8_t reg, val;
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int i;
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/* Only allow 32-bit access. */
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if (size != 4)
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return -1;
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for (i = 0; i < nitems(ccpmic_power_regmap); i++) {
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if (address == ccpmic_power_regmap[i].address)
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break;
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}
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if (i == nitems(ccpmic_power_regmap)) {
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printf("%s: addr 0x%02llx\n", __func__, address);
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return -1;
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}
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reg = ccpmic_power_regmap[i].hi;
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val = ccpmic_read_1(sc, reg, 0);
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if (iodir == ACPI_IOREAD) {
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if ((val & CCPMIC_PWR_SEL) && (val & CCPMIC_PWR_ON))
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*value = 1;
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else
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*value = 0;
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} else {
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if (*value)
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val |= CCPMIC_PWR_ON;
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else
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val &= ~CCPMIC_PWR_ON;
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ccpmic_write_1(sc, reg, val | CCPMIC_PWR_SEL, 0);
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}
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return 0;
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}
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/*
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* We have 16 real GPIOs and a bunch of virtual ones. The virtual
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* ones are mostly there to deal with a limitation of Microsoft
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* Windows. We only implement the "panel" control GPIO, which
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* actually maps onto a real GPIO.
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*/
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int
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ccpmic_read_pin(void *cookie, int pin)
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{
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struct ccpmic_softc *sc = cookie;
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uint8_t reg;
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if (pin >= CCPMIC_NPINS)
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return 0;
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reg = ((pin < 8) ? CCPMIC_GPIO0P0CTLO : CCPMIC_GPIO1P0CTLO) + pin % 8;
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ccpmic_write_1(sc, reg, CCPMIC_GPIOCTLO_INPUT, 0);
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reg = ((pin < 8) ? CCPMIC_GPIO0P0CTLI : CCPMIC_GPIO1P0CTLI) + pin % 8;
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return ccpmic_read_1(sc, reg, 0) & CCPMIC_GPIOCTLI_VALUE;
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}
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void
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ccpmic_write_pin(void *cookie, int pin, int value)
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{
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struct ccpmic_softc *sc = cookie;
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uint8_t reg;
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if (pin == 0x5e) {
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reg = CCPMIC_GPIOPANELCTL;
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ccpmic_write_1(sc, reg, CCPMIC_GPIOCTLO_OUTPUT | !!value, 0);
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return;
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}
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if (pin >= CCPMIC_NPINS)
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return;
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reg = ((pin < 8) ? CCPMIC_GPIO0P0CTLO : CCPMIC_GPIO1P0CTLO) + pin % 8;
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ccpmic_write_1(sc, reg, CCPMIC_GPIOCTLO_OUTPUT | !!value, 0);
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}
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