346 lines
8.3 KiB
C
346 lines
8.3 KiB
C
/* $OpenBSD: qciic_fdt.c,v 1.1 2022/11/06 15:36:13 patrick Exp $ */
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/*
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* Copyright (c) 2022 Mark Kettenis <kettenis@openbsd.org>
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <machine/fdt.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_gpio.h>
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#include <dev/ofw/fdt.h>
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#define _I2C_PRIVATE
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#include <dev/i2c/i2cvar.h>
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/* Registers */
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#define GENI_I2C_TX_TRANS_LEN 0x26c
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#define GENI_I2C_RX_TRANS_LEN 0x270
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#define GENI_M_CMD0 0x600
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#define GENI_M_CMD0_OPCODE_I2C_WRITE (0x1 << 27)
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#define GENI_M_CMD0_OPCODE_I2C_READ (0x2 << 27)
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#define GENI_M_CMD0_SLV_ADDR_SHIFT 9
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#define GENI_M_CMD0_STOP_STRETCH (1 << 2)
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#define GENI_M_IRQ_STATUS 0x610
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#define GENI_M_IRQ_CLEAR 0x618
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#define GENI_M_IRQ_CMD_DONE (1 << 0)
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#define GENI_TX_FIFO 0x700
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#define GENI_RX_FIFO 0x780
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#define GENI_TX_FIFO_STATUS 0x800
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#define GENI_RX_FIFO_STATUS 0x804
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#define GENI_RX_FIFO_STATUS_WC(val) ((val) & 0xffffff)
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#define HREAD4(sc, reg) \
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(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
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#define HWRITE4(sc, reg, val) \
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bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
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struct qciic_fdt_softc {
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struct device sc_dev;
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bus_space_tag_t sc_iot;
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bus_space_handle_t sc_ioh;
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int sc_node;
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struct device *sc_iic;
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struct i2c_controller sc_ic;
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};
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int qciic_fdt_match(struct device *, void *, void *);
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void qciic_fdt_attach(struct device *, struct device *, void *);
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const struct cfattach qciic_fdt_ca = {
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sizeof (struct qciic_fdt_softc), qciic_fdt_match, qciic_fdt_attach
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};
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int qciic_fdt_acquire_bus(void *, int);
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void qciic_fdt_release_bus(void *, int);
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int qciic_fdt_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t,
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void *, size_t, int);
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void *qciic_fdt_i2c_intr_establish(void *, void *, int, int (*)(void *),
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void *, const char *);
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void qciic_fdt_i2c_intr_disestablish(void *, void *);
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const char *qciic_fdt_i2c_intr_string(void *, void *);
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void qciic_fdt_bus_scan(struct device *, struct i2cbus_attach_args *,
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void *);
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int
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qciic_fdt_match(struct device *parent, void *match, void *aux)
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{
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struct fdt_attach_args *faa = aux;
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return OF_is_compatible(faa->fa_node, "qcom,geni-i2c");
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}
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void
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qciic_fdt_attach(struct device *parent, struct device *self, void *aux)
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{
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struct qciic_fdt_softc *sc = (struct qciic_fdt_softc *)self;
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struct fdt_attach_args *faa = aux;
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struct i2cbus_attach_args iba;
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sc->sc_node = faa->fa_node;
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sc->sc_iot = faa->fa_iot;
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if (bus_space_map(sc->sc_iot, faa->fa_reg[0].addr, faa->fa_reg[0].size,
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0, &sc->sc_ioh)) {
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printf(": can't map registers\n");
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return;
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}
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printf("\n");
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sc->sc_ic.ic_cookie = sc;
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sc->sc_ic.ic_acquire_bus = qciic_fdt_acquire_bus;
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sc->sc_ic.ic_release_bus = qciic_fdt_release_bus;
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sc->sc_ic.ic_exec = qciic_fdt_exec;
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sc->sc_ic.ic_intr_establish = qciic_fdt_i2c_intr_establish;
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sc->sc_ic.ic_intr_disestablish = qciic_fdt_i2c_intr_disestablish;
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sc->sc_ic.ic_intr_string = qciic_fdt_i2c_intr_string;
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memset(&iba, 0, sizeof(iba));
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iba.iba_name = "iic";
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iba.iba_tag = &sc->sc_ic;
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iba.iba_bus_scan = qciic_fdt_bus_scan;
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iba.iba_bus_scan_arg = &sc->sc_node;
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config_found(&sc->sc_dev, &iba, iicbus_print);
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}
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int
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qciic_fdt_acquire_bus(void *cookie, int flags)
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{
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return 0;
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}
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void
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qciic_fdt_release_bus(void *cookie, int flags)
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{
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}
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int
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qciic_fdt_wait(struct qciic_fdt_softc *sc, uint32_t bits)
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{
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uint32_t stat;
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int timo;
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for (timo = 50000; timo > 0; timo--) {
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stat = HREAD4(sc, GENI_M_IRQ_STATUS);
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if (stat & bits)
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break;
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delay(10);
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}
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if (timo == 0)
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return ETIMEDOUT;
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return 0;
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}
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int
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qciic_fdt_read(struct qciic_fdt_softc *sc, uint8_t *buf, size_t len)
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{
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uint32_t stat, word;
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int timo, i;
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word = 0;
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for (i = 0; i < len; i++) {
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if ((i % 4) == 0) {
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for (timo = 50000; timo > 0; timo--) {
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stat = HREAD4(sc, GENI_RX_FIFO_STATUS);
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if (GENI_RX_FIFO_STATUS_WC(stat) > 0)
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break;
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delay(10);
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}
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if (timo == 0)
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return ETIMEDOUT;
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word = HREAD4(sc, GENI_RX_FIFO);
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}
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buf[i] = word >> ((i % 4) * 8);
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}
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return 0;
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}
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int
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qciic_fdt_write(struct qciic_fdt_softc *sc, const uint8_t *buf, size_t len)
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{
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uint32_t stat, word;
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int timo, i;
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word = 0;
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for (i = 0; i < len; i++) {
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word |= buf[i] << ((i % 4) * 8);
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if ((i % 4) == 3 || i == (len - 1)) {
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for (timo = 50000; timo > 0; timo--) {
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stat = HREAD4(sc, GENI_TX_FIFO_STATUS);
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if (stat < 16)
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break;
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delay(10);
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}
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if (timo == 0)
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return ETIMEDOUT;
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HWRITE4(sc, GENI_TX_FIFO, word);
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word = 0;
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}
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}
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return 0;
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}
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int
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qciic_fdt_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, const void *cmd,
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size_t cmdlen, void *buf, size_t buflen, int flags)
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{
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struct qciic_fdt_softc *sc = cookie;
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uint32_t m_cmd, m_param, stat;
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int error;
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m_param = addr << GENI_M_CMD0_SLV_ADDR_SHIFT;
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m_param |= GENI_M_CMD0_STOP_STRETCH;
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if (buflen == 0 && I2C_OP_STOP_P(op))
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m_param &= ~GENI_M_CMD0_STOP_STRETCH;
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if (cmdlen > 0) {
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stat = HREAD4(sc, GENI_M_IRQ_STATUS);
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HWRITE4(sc, GENI_M_IRQ_CLEAR, stat);
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HWRITE4(sc, GENI_I2C_TX_TRANS_LEN, cmdlen);
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m_cmd = GENI_M_CMD0_OPCODE_I2C_WRITE | m_param;
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HWRITE4(sc, GENI_M_CMD0, m_cmd);
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error = qciic_fdt_write(sc, cmd, cmdlen);
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if (error)
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return error;
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error = qciic_fdt_wait(sc, GENI_M_IRQ_CMD_DONE);
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if (error)
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return error;
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}
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if (buflen == 0)
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return 0;
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if (I2C_OP_STOP_P(op))
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m_param &= ~GENI_M_CMD0_STOP_STRETCH;
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if (I2C_OP_READ_P(op)) {
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stat = HREAD4(sc, GENI_M_IRQ_STATUS);
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HWRITE4(sc, GENI_M_IRQ_CLEAR, stat);
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HWRITE4(sc, GENI_I2C_RX_TRANS_LEN, buflen);
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m_cmd = GENI_M_CMD0_OPCODE_I2C_READ | m_param;
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HWRITE4(sc, GENI_M_CMD0, m_cmd);
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error = qciic_fdt_read(sc, buf, buflen);
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if (error)
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return error;
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error = qciic_fdt_wait(sc, GENI_M_IRQ_CMD_DONE);
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if (error)
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return error;
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} else {
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stat = HREAD4(sc, GENI_M_IRQ_STATUS);
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HWRITE4(sc, GENI_M_IRQ_CLEAR, stat);
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HWRITE4(sc, GENI_I2C_TX_TRANS_LEN, buflen);
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m_cmd = GENI_M_CMD0_OPCODE_I2C_WRITE | m_param;
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HWRITE4(sc, GENI_M_CMD0, m_cmd);
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error = qciic_fdt_write(sc, buf, buflen);
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if (error)
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return error;
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error = qciic_fdt_wait(sc, GENI_M_IRQ_CMD_DONE);
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if (error)
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return error;
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}
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return 0;
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}
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void *
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qciic_fdt_i2c_intr_establish(void *cookie, void *ih, int level,
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int (*func)(void *), void *arg, const char *name)
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{
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int node = *(int *)ih;
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return fdt_intr_establish(node, level, func, arg, (char *)name);
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}
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void
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qciic_fdt_i2c_intr_disestablish(void *cookie, void *ih)
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{
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fdt_intr_disestablish(ih);
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}
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const char *
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qciic_fdt_i2c_intr_string(void *cookie, void *ih)
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{
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static char irqstr[64];
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snprintf(irqstr, sizeof(irqstr), "irq");
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return irqstr;
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}
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void
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qciic_fdt_bus_scan(struct device *self, struct i2cbus_attach_args *iba, void *aux)
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{
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int iba_node = *(int *)aux;
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extern int iic_print(void *, const char *);
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struct i2c_attach_args ia;
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char name[32], status[32];
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uint32_t reg[1];
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int node;
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for (node = OF_child(iba_node); node; node = OF_peer(node)) {
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memset(name, 0, sizeof(name));
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memset(status, 0, sizeof(status));
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memset(reg, 0, sizeof(reg));
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if (OF_getprop(node, "compatible", name, sizeof(name)) == -1)
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continue;
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if (name[0] == '\0')
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continue;
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if (OF_getprop(node, "status", status, sizeof(status)) > 0 &&
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strcmp(status, "disabled") == 0)
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continue;
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if (OF_getprop(node, "reg", ®, sizeof(reg)) != sizeof(reg))
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continue;
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memset(&ia, 0, sizeof(ia));
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ia.ia_tag = iba->iba_tag;
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ia.ia_addr = bemtoh32(®[0]);
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ia.ia_name = name;
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ia.ia_cookie = &node;
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ia.ia_intr = &node;
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/* Quirk for ihidev(4) */
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if (strcmp(name, "hid-over-i2c") == 0) {
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ia.ia_name = "ihidev";
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ia.ia_size = OF_getpropint(node, "hid-descr-addr", 0);
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ia.ia_cookie = name;
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}
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config_found(self, &ia, iic_print);
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}
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}
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