594 lines
16 KiB
C
594 lines
16 KiB
C
/* $OpenBSD: athnvar.h,v 1.42 2021/04/15 18:25:43 stsp Exp $ */
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/*-
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* Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifdef notyet
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#define ATHN_BT_COEXISTENCE 1
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#endif
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#ifdef ATHN_DEBUG
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#define DPRINTF(x) do { if (athn_debug > 0) printf x; } while (0)
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#define DPRINTFN(n, x) do { if (athn_debug >= (n)) printf x; } while (0)
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extern int athn_debug;
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#else
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#define DPRINTF(x)
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#define DPRINTFN(n, x)
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#endif
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#define LE_READ_4(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24)
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#define LE_READ_2(p) ((p)[0] | (p)[1] << 8)
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#define ATHN_RXBUFSZ 3872
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#define ATHN_TXBUFSZ 4096
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#define ATHN_NRXBUFS 64
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#define ATHN_NTXBUFS 64 /* Shared between all Tx queues. */
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struct athn_rx_radiotap_header {
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struct ieee80211_radiotap_header wr_ihdr;
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uint64_t wr_tsft;
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uint8_t wr_flags;
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uint8_t wr_rate;
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uint16_t wr_chan_freq;
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uint16_t wr_chan_flags;
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int8_t wr_dbm_antsignal;
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uint8_t wr_antenna;
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} __packed;
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#define ATHN_RX_RADIOTAP_PRESENT \
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(1 << IEEE80211_RADIOTAP_TSFT | \
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1 << IEEE80211_RADIOTAP_FLAGS | \
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1 << IEEE80211_RADIOTAP_RATE | \
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1 << IEEE80211_RADIOTAP_CHANNEL | \
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1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL | \
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1 << IEEE80211_RADIOTAP_ANTENNA)
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struct athn_tx_radiotap_header {
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struct ieee80211_radiotap_header wt_ihdr;
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uint8_t wt_flags;
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uint8_t wt_rate;
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uint16_t wt_chan_freq;
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uint16_t wt_chan_flags;
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} __packed;
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#define ATHN_TX_RADIOTAP_PRESENT \
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(1 << IEEE80211_RADIOTAP_FLAGS | \
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1 << IEEE80211_RADIOTAP_RATE | \
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1 << IEEE80211_RADIOTAP_CHANNEL)
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struct athn_tx_buf {
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SIMPLEQ_ENTRY(athn_tx_buf) bf_list;
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void *bf_descs;
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bus_dmamap_t bf_map;
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bus_addr_t bf_daddr;
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struct mbuf *bf_m;
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struct ieee80211_node *bf_ni;
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int bf_txmcs;
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int bf_txflags;
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#define ATHN_TXFLAG_PAPRD (1 << 0)
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#define ATHN_TXFLAG_CAB (1 << 1)
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};
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struct athn_txq {
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SIMPLEQ_HEAD(, athn_tx_buf) head;
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void *lastds;
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struct athn_tx_buf *wait;
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int queued;
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};
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struct athn_rx_buf {
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SIMPLEQ_ENTRY(athn_rx_buf) bf_list;
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void *bf_desc;
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bus_dmamap_t bf_map;
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struct mbuf *bf_m;
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bus_addr_t bf_daddr;
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};
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struct athn_rxq {
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struct athn_rx_buf *bf;
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void *descs;
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void *lastds;
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bus_dmamap_t map;
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bus_dma_segment_t seg;
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int count;
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SIMPLEQ_HEAD(, athn_rx_buf) head;
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};
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/* Software rate indexes. */
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#define ATHN_RIDX_CCK1 0
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#define ATHN_RIDX_CCK2 1
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#define ATHN_RIDX_OFDM6 4
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#define ATHN_RIDX_MCS0 12
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#define ATHN_RIDX_MCS8 (ATHN_RIDX_MCS0 + 8)
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#define ATHN_RIDX_MCS15 27
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#define ATHN_RIDX_MAX 27
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#define ATHN_MCS_MAX 15
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#define ATHN_NUM_MCS (ATHN_MCS_MAX + 1)
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#define ATHN_IS_HT_RIDX(ridx) ((ridx) >= ATHN_RIDX_MCS0)
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#define ATHN_IS_MIMO_RIDX(ridx) ((ridx) >= ATHN_RIDX_MCS8)
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static const struct athn_rate {
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uint16_t rate; /* Rate in 500Kbps unit. */
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uint8_t hwrate; /* HW representation. */
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uint8_t rspridx; /* Control Response Frame rate index. */
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enum ieee80211_phytype phy;
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} athn_rates[] = {
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{ 2, 0x1b, 0, IEEE80211_T_DS },
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{ 4, 0x1a, 1, IEEE80211_T_DS },
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{ 11, 0x19, 1, IEEE80211_T_DS },
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{ 22, 0x18, 1, IEEE80211_T_DS },
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{ 12, 0x0b, 4, IEEE80211_T_OFDM },
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{ 18, 0x0f, 4, IEEE80211_T_OFDM },
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{ 24, 0x0a, 6, IEEE80211_T_OFDM },
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{ 36, 0x0e, 6, IEEE80211_T_OFDM },
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{ 48, 0x09, 8, IEEE80211_T_OFDM },
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{ 72, 0x0d, 8, IEEE80211_T_OFDM },
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{ 96, 0x08, 8, IEEE80211_T_OFDM },
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{ 108, 0x0c, 8, IEEE80211_T_OFDM },
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{ 13, 0x80, 4, IEEE80211_T_OFDM },
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{ 26, 0x81, 6, IEEE80211_T_OFDM },
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{ 39, 0x82, 6, IEEE80211_T_OFDM },
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{ 52, 0x83, 8, IEEE80211_T_OFDM },
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{ 78, 0x84, 8, IEEE80211_T_OFDM },
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{ 104, 0x85, 8, IEEE80211_T_OFDM },
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{ 117, 0x86, 8, IEEE80211_T_OFDM },
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{ 130, 0x87, 8, IEEE80211_T_OFDM },
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{ 26, 0x88, 4, IEEE80211_T_OFDM },
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{ 52, 0x89, 6, IEEE80211_T_OFDM },
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{ 78, 0x8a, 8, IEEE80211_T_OFDM },
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{ 104, 0x8b, 8, IEEE80211_T_OFDM },
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{ 156, 0x8c, 8, IEEE80211_T_OFDM },
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{ 208, 0x8d, 8, IEEE80211_T_OFDM },
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{ 234, 0x8e, 8, IEEE80211_T_OFDM },
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{ 260, 0x8f, 8, IEEE80211_T_OFDM }
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};
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struct athn_series {
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uint16_t dur;
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uint8_t hwrate;
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};
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struct athn_pier {
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uint8_t fbin;
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const uint8_t *pwr[AR_PD_GAINS_IN_MASK];
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const uint8_t *vpd[AR_PD_GAINS_IN_MASK];
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};
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/*
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* Structures used to store initialization values.
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*/
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struct athn_ini {
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int nregs;
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const uint16_t *regs;
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const uint32_t *vals_5g20;
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const uint32_t *vals_5g40;
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const uint32_t *vals_2g40;
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const uint32_t *vals_2g20;
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int ncmregs;
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const uint16_t *cmregs;
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const uint32_t *cmvals;
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int nfastregs;
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const uint16_t *fastregs;
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const uint32_t *fastvals_5g20;
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const uint32_t *fastvals_5g40;
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};
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struct athn_gain {
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int nregs;
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const uint16_t *regs;
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const uint32_t *vals_5g;
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const uint32_t *vals_2g;
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};
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struct athn_addac {
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int nvals;
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const uint32_t *vals;
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};
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struct athn_serdes {
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int nvals;
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const uint32_t *regs;
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const uint32_t *vals;
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};
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/* Rx queue software indexes. */
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#define ATHN_QID_LP 0
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#define ATHN_QID_HP 1
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/* Tx queue software indexes. */
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#define ATHN_QID_AC_BE 0
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#define ATHN_QID_PSPOLL 1
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#define ATHN_QID_AC_BK 2
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#define ATHN_QID_AC_VI 3
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#define ATHN_QID_AC_VO 4
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#define ATHN_QID_UAPSD 5
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#define ATHN_QID_CAB 6
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#define ATHN_QID_BEACON 7
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#define ATHN_QID_COUNT 8
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/* Map Access Category to Tx queue Id. */
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static const uint8_t athn_ac2qid[EDCA_NUM_AC] = {
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ATHN_QID_AC_BE, /* EDCA_AC_BE */
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ATHN_QID_AC_BK, /* EDCA_AC_BK */
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ATHN_QID_AC_VI, /* EDCA_AC_VI */
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ATHN_QID_AC_VO /* EDCA_AC_VO */
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};
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static const uint8_t athn_5ghz_chans[] = {
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/* UNII 1. */
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36, 40, 44, 48,
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/* UNII 2. */
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52, 56, 60, 64,
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/* Middle band. */
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100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140,
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/* UNII 3. */
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149, 153, 157, 161, 165
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};
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/* Number of data bits per OFDM symbol for MCS[0-15]. */
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/* See tables 20-29, 20-30, 20-33, 20-34. */
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static const uint16_t ar_mcs_ndbps[][2] = {
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/* 20MHz 40MHz */
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{ 26, 54 }, /* MCS0 */
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{ 52, 108 }, /* MCS1 */
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{ 78, 162 }, /* MCS2 */
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{ 104, 216 }, /* MCS3 */
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{ 156, 324 }, /* MCS4 */
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{ 208, 432 }, /* MCS5 */
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{ 234, 486 }, /* MCS6 */
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{ 260, 540 }, /* MCS7 */
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{ 26, 108 }, /* MCS8 */
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{ 52, 216 }, /* MCS9 */
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{ 78, 324 }, /* MCS10 */
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{ 104, 432 }, /* MCS11 */
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{ 156, 648 }, /* MCS12 */
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{ 208, 864 }, /* MCS13 */
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{ 234, 972 }, /* MCS14 */
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{ 260, 1080 } /* MCS15 */
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};
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#define ATHN_POWER_OFDM6 0
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#define ATHN_POWER_OFDM9 1
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#define ATHN_POWER_OFDM12 2
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#define ATHN_POWER_OFDM18 3
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#define ATHN_POWER_OFDM24 4
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#define ATHN_POWER_OFDM36 5
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#define ATHN_POWER_OFDM48 6
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#define ATHN_POWER_OFDM54 7
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#define ATHN_POWER_CCK1_LP 8
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#define ATHN_POWER_CCK2_LP 9
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#define ATHN_POWER_CCK2_SP 10
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#define ATHN_POWER_CCK55_LP 11
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#define ATHN_POWER_CCK55_SP 12
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#define ATHN_POWER_CCK11_LP 13
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#define ATHN_POWER_CCK11_SP 14
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#define ATHN_POWER_XR 15
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#define ATHN_POWER_HT20(mcs) (16 + (mcs))
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#define ATHN_POWER_HT40(mcs) (40 + (mcs))
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#define ATHN_POWER_CCK_DUP 64
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#define ATHN_POWER_OFDM_DUP 65
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#define ATHN_POWER_CCK_EXT 66
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#define ATHN_POWER_OFDM_EXT 67
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#define ATHN_POWER_COUNT 68
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#define ATHN_NUM_LEGACY_RATES IEEE80211_RATE_MAXSIZE
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#define ATHN_NUM_RATES (ATHN_NUM_LEGACY_RATES + ATHN_NUM_MCS)
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struct athn_node {
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struct ieee80211_node ni;
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struct ieee80211_amrr_node amn;
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struct ieee80211_ra_node rn;
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uint8_t ridx[ATHN_NUM_RATES];
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uint8_t fallback[ATHN_NUM_RATES];
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uint8_t sta_index;
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};
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/*
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* Adaptive noise immunity state.
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*/
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#define ATHN_ANI_PERIOD 100
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#define ATHN_ANI_RSSI_THR_HIGH 40
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#define ATHN_ANI_RSSI_THR_LOW 7
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struct athn_ani {
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uint8_t noise_immunity_level;
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uint8_t spur_immunity_level;
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uint8_t firstep_level;
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uint8_t ofdm_weak_signal;
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uint8_t cck_weak_signal;
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uint32_t listen_time;
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uint32_t ofdm_trig_high;
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uint32_t ofdm_trig_low;
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int32_t cck_trig_high;
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int32_t cck_trig_low;
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uint32_t ofdm_phy_err_base;
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uint32_t cck_phy_err_base;
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uint32_t ofdm_phy_err_count;
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uint32_t cck_phy_err_count;
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uint32_t cyccnt;
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uint32_t txfcnt;
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uint32_t rxfcnt;
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};
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struct athn_iq_cal {
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uint32_t pwr_meas_i;
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uint32_t pwr_meas_q;
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int32_t iq_corr_meas;
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};
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struct athn_adc_cal {
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uint32_t pwr_meas_odd_i;
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uint32_t pwr_meas_even_i;
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uint32_t pwr_meas_odd_q;
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uint32_t pwr_meas_even_q;
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};
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struct athn_calib {
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int nsamples;
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struct athn_iq_cal iq[AR_MAX_CHAINS];
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struct athn_adc_cal adc_gain[AR_MAX_CHAINS];
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struct athn_adc_cal adc_dc_offset[AR_MAX_CHAINS];
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};
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#define ATHN_NF_CAL_HIST_MAX 5
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struct athn_softc;
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struct athn_ops {
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/* Bus callbacks. */
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uint32_t (*read)(struct athn_softc *, uint32_t);
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void (*write)(struct athn_softc *, uint32_t, uint32_t);
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void (*write_barrier)(struct athn_softc *);
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void (*setup)(struct athn_softc *);
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void (*set_txpower)(struct athn_softc *, struct ieee80211_channel *,
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struct ieee80211_channel *);
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void (*spur_mitigate)(struct athn_softc *,
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struct ieee80211_channel *, struct ieee80211_channel *);
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const struct ar_spur_chan *
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(*get_spur_chans)(struct athn_softc *, int);
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void (*init_from_rom)(struct athn_softc *,
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struct ieee80211_channel *, struct ieee80211_channel *);
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int (*set_synth)(struct athn_softc *, struct ieee80211_channel *,
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struct ieee80211_channel *);
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int (*read_rom_data)(struct athn_softc *, uint32_t, void *, int);
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const uint8_t *
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(*get_rom_template)(struct athn_softc *, uint8_t);
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void (*swap_rom)(struct athn_softc *);
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void (*olpc_init)(struct athn_softc *);
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void (*olpc_temp_compensation)(struct athn_softc *);
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/* GPIO callbacks. */
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int (*gpio_read)(struct athn_softc *, int);
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void (*gpio_write)(struct athn_softc *, int, int);
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void (*gpio_config_input)(struct athn_softc *, int);
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void (*gpio_config_output)(struct athn_softc *, int, int);
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void (*rfsilent_init)(struct athn_softc *);
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/* DMA callbacks. */
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int (*dma_alloc)(struct athn_softc *);
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void (*dma_free)(struct athn_softc *);
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void (*rx_enable)(struct athn_softc *);
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int (*intr)(struct athn_softc *);
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int (*tx)(struct athn_softc *, struct mbuf *,
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struct ieee80211_node *, int);
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/* PHY callbacks. */
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void (*set_rf_mode)(struct athn_softc *,
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struct ieee80211_channel *);
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int (*rf_bus_request)(struct athn_softc *);
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void (*rf_bus_release)(struct athn_softc *);
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void (*set_phy)(struct athn_softc *, struct ieee80211_channel *,
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struct ieee80211_channel *);
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void (*set_delta_slope)(struct athn_softc *,
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struct ieee80211_channel *, struct ieee80211_channel *);
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void (*enable_antenna_diversity)(struct athn_softc *);
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void (*init_baseband)(struct athn_softc *);
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void (*disable_phy)(struct athn_softc *);
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void (*set_rxchains)(struct athn_softc *);
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void (*noisefloor_calib)(struct athn_softc *);
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void (*init_noisefloor_calib)(struct athn_softc *);
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int (*get_noisefloor)(struct athn_softc *);
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void (*apply_noisefloor)(struct athn_softc *);
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void (*do_calib)(struct athn_softc *);
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void (*next_calib)(struct athn_softc *);
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void (*hw_init)(struct athn_softc *, struct ieee80211_channel *,
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struct ieee80211_channel *);
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void (*get_paprd_masks)(struct athn_softc *sc,
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struct ieee80211_channel *, uint32_t *, uint32_t *);
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/* ANI callbacks. */
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void (*set_noise_immunity_level)(struct athn_softc *, int);
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void (*enable_ofdm_weak_signal)(struct athn_softc *);
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void (*disable_ofdm_weak_signal)(struct athn_softc *);
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void (*set_cck_weak_signal)(struct athn_softc *, int);
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void (*set_firstep_level)(struct athn_softc *, int);
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void (*set_spur_immunity_level)(struct athn_softc *, int);
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};
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struct athn_softc {
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struct device sc_dev;
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struct ieee80211com sc_ic;
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int (*sc_enable)(struct athn_softc *);
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void (*sc_disable)(struct athn_softc *);
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void (*sc_power)(struct athn_softc *, int);
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void (*sc_disable_aspm)(struct athn_softc *);
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void (*sc_enable_extsynch)(
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struct athn_softc *);
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int (*sc_newstate)(struct ieee80211com *,
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enum ieee80211_state, int);
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bus_dma_tag_t sc_dmat;
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struct timeout scan_to;
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struct timeout calib_to;
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struct ieee80211_amrr amrr;
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u_int flags;
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#define ATHN_FLAG_PCIE (1 << 0)
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#define ATHN_FLAG_USB (1 << 1)
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#define ATHN_FLAG_OLPC (1 << 2)
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#define ATHN_FLAG_PAPRD (1 << 3)
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#define ATHN_FLAG_FAST_PLL_CLOCK (1 << 4)
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#define ATHN_FLAG_RFSILENT (1 << 5)
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#define ATHN_FLAG_RFSILENT_REVERSED (1 << 6)
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#define ATHN_FLAG_BTCOEX2WIRE (1 << 7)
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#define ATHN_FLAG_BTCOEX3WIRE (1 << 8)
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/* Shortcut. */
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#define ATHN_FLAG_BTCOEX (ATHN_FLAG_BTCOEX2WIRE | ATHN_FLAG_BTCOEX3WIRE)
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#define ATHN_FLAG_11A (1 << 9)
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#define ATHN_FLAG_11G (1 << 10)
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#define ATHN_FLAG_11N (1 << 11)
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#define ATHN_FLAG_AN_TOP2_FIXUP (1 << 12)
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#define ATHN_FLAG_NON_ENTERPRISE (1 << 13)
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#define ATHN_FLAG_3TREDUCE_CHAIN (1 << 14)
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uint8_t ngpiopins;
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int led_pin;
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int rfsilent_pin;
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int led_state;
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uint32_t isync;
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uint32_t imask;
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uint16_t mac_ver;
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uint8_t mac_rev;
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uint8_t rf_rev;
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uint16_t eep_rev;
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uint8_t txchainmask;
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uint8_t rxchainmask;
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uint8_t ntxchains;
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uint8_t nrxchains;
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uint8_t sup_calib_mask;
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uint8_t cur_calib_mask;
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#define ATHN_CAL_IQ (1 << 0)
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#define ATHN_CAL_ADC_GAIN (1 << 1)
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#define ATHN_CAL_ADC_DC (1 << 2)
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#define ATHN_CAL_TEMP (1 << 3)
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struct ieee80211_channel *curchan;
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struct ieee80211_channel *curchanext;
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/* Open Loop Power Control. */
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int8_t tx_gain_tbl[AR9280_TX_GAIN_TABLE_SIZE];
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int8_t pdadc;
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int8_t tcomp;
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int olpc_ticks;
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int iqcal_ticks;
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|
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/* PA predistortion. */
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uint16_t gain1[AR_MAX_CHAINS];
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uint32_t txgain[AR9003_TX_GAIN_TABLE_SIZE];
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int16_t pa_in[AR_MAX_CHAINS]
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[AR9003_PAPRD_MEM_TAB_SIZE];
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int16_t angle[AR_MAX_CHAINS]
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[AR9003_PAPRD_MEM_TAB_SIZE];
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int32_t trainpow;
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uint8_t paprd_curchain;
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uint32_t rwbuf[64];
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int kc_entries;
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void *eep;
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const void *eep_def;
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uint32_t eep_base;
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uint32_t eep_size;
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struct athn_rxq rxq[2];
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struct athn_txq txq[31];
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void *descs;
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bus_dmamap_t map;
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bus_dma_segment_t seg;
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SIMPLEQ_HEAD(, athn_tx_buf) txbufs;
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struct athn_tx_buf *bcnbuf;
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struct athn_tx_buf txpool[ATHN_NTXBUFS];
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|
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bus_dmamap_t txsmap;
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bus_dma_segment_t txsseg;
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void *txsring;
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int txscur;
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|
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int sc_if_flags;
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int sc_tx_timer;
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|
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const struct athn_ini *ini;
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const struct athn_gain *rx_gain;
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const struct athn_gain *tx_gain;
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const struct athn_addac *addac;
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const struct athn_serdes *serdes;
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uint32_t workaround;
|
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uint32_t obs_off;
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|
uint32_t gpio_input_en_off;
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|
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struct athn_ops ops;
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|
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int fixed_ridx;
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|
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int16_t cca_min_2g;
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int16_t cca_max_2g;
|
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int16_t cca_min_5g;
|
|
int16_t cca_max_5g;
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struct {
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int16_t nf[AR_MAX_CHAINS];
|
|
int16_t nf_ext[AR_MAX_CHAINS];
|
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} nf_hist[ATHN_NF_CAL_HIST_MAX];
|
|
int nf_hist_cur;
|
|
int nf_hist_nvalid;
|
|
int16_t nf_priv[AR_MAX_CHAINS];
|
|
int16_t nf_ext_priv[AR_MAX_CHAINS];
|
|
int nf_calib_pending;
|
|
int nf_calib_ticks;
|
|
int pa_calib_ticks;
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|
|
|
struct athn_calib calib;
|
|
struct athn_ani ani;
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|
|
|
#if NBPFILTER > 0
|
|
caddr_t sc_drvbpf;
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|
|
|
union {
|
|
struct athn_rx_radiotap_header th;
|
|
uint8_t pad[IEEE80211_RADIOTAP_HDRLEN];
|
|
} sc_rxtapu;
|
|
#define sc_rxtap sc_rxtapu.th
|
|
int sc_rxtap_len;
|
|
|
|
union {
|
|
struct athn_tx_radiotap_header th;
|
|
uint8_t pad[IEEE80211_RADIOTAP_HDRLEN];
|
|
} sc_txtapu;
|
|
#define sc_txtap sc_txtapu.th
|
|
int sc_txtap_len;
|
|
#endif
|
|
};
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|
|
|
extern int athn_attach(struct athn_softc *);
|
|
extern void athn_detach(struct athn_softc *);
|
|
extern void athn_suspend(struct athn_softc *);
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|
extern void athn_wakeup(struct athn_softc *);
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|
extern int athn_intr(void *);
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