112 lines
4.6 KiB
C
112 lines
4.6 KiB
C
/* $OpenBSD: nsphyreg.h,v 1.4 2008/06/26 05:42:16 ray Exp $ */
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/* $NetBSD: nsphyreg.h,v 1.1 1998/08/10 23:58:39 thorpej Exp $ */
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/*-
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DEV_MII_NSPHYREG_H_
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#define _DEV_MII_NSPHYREG_H_
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/*
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* National Semiconductor DP83840 Ethernet PHY register definitions
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* Further documentation can be found at:
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* http://www.national.com/pf/DP/DP83840A.html
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*/
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#define MII_NSPHY_DCR 0x12 /* Disconnect counter */
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#define MII_NSPHY_FCSCR 0x13 /* False carrier sense counter */
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#define MII_NSPHY_RECR 0x15 /* Receive error counter */
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#define MII_NSPHY_SRR 0x16 /* Silicon revision */
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#define MII_NSPHY_PCR 0x17 /* PCS sub-layer configuration */
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#define PCR_NRZI 0x8000 /* NRZI encoding enabled for 100TX */
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#define PCR_DESCRTOSEL 0x4000 /* descrambler t/o select (2ms) */
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#define PCR_DESCRTODIS 0x2000 /* descrambler t/o disable */
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#define PCR_REPEATER 0x1000 /* repeater mode */
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#define PCR_ENCSEL 0x0800 /* encoder mode select */
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#define PCR_TXREADYSEL 0x0400 /* use internal txrdy signal */
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#define PCR_CONGCTRL 0x0100 /* congestion control */
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#define PCR_CLK25MDIS 0x0080 /* CLK25M disable */
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#define PCR_FLINK100 0x0040 /* force good link in 100mbps */
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#define PCR_CIMDIS 0x0020 /* carrier integrity monitor disable */
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#define PCR_TXOFF 0x0010 /* force transmit off */
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#define PCR_LED1MODE 0x0004 /* LED1 mode: see below */
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#define PCR_LED4MODE 0x0002 /* LED4 mode: see below */
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/*
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* LED1 Mode:
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*
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* 1 LED1 output configured to PAR's CON_STATUS, useful for
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* network management in 100baseTX mode.
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*
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* 0 Normal LED1 operation - 10baseTX and 100baseTX transmission
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* activity.
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*
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* LED4 Mode:
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*
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* 1 LED4 output configured to indicate full-duplex in both
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* 10baseT and 100baseTX modes.
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*
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* 0 LED4 output configured to indicate polarity in 10baseT
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* mode and full-duplex in 100baseTX mode.
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*/
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#define MII_NSPHY_LBREMR 0x18 /* Loopback, bypass, error mask */
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#define LBREMR_BADSSDEN 0x8000 /* enable bad SSD detection */
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#define LBREMR_BP4B5B 0x4000 /* bypass 4b/5b encoding */
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#define LBREMR_BPSCR 0x2000 /* bypass scrambler */
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#define LBREMR_BPALIGN 0x1000 /* bypass alignment function */
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#define LBREMR_10LOOP 0x0800 /* 10baseT loopback */
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#define LBREMR_LB1 0x0200 /* loopback ctl 1 */
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#define LBREMR_LB0 0x0100 /* loopback ctl 0 */
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#define LBREMR_ALTCRS 0x0040 /* alt crs operation */
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#define LBREMR_LOOPXMTDIS 0x0020 /* disable transmit in 100TX loopbk */
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#define LBREMR_CODEERR 0x0010 /* code errors */
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#define LBREMR_PEERR 0x0008 /* premature end errors */
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#define LBREMR_LINKERR 0x0004 /* link errors */
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#define LBREMR_PKTERR 0x0002 /* packet errors */
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#define MII_NSPHY_PAR 0x19 /* Physical address and status */
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#define PAR_DISCRSJAB 0x0800 /* disable car sense during jab */
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#define PAR_ANENSTAT 0x0400 /* autoneg mode status */
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#define PAR_FEFIEN 0x0100 /* far end fault enable */
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#define PAR_FDX 0x0080 /* full duplex status */
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#define PAR_10 0x0040 /* 10mbps mode */
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#define PAR_CON 0x0020 /* connect status */
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#define PAR_AMASK 0x001f /* PHY address bits */
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#define MII_NSPHY_10BTSR 0x1b /* 10baseT status */
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#define MII_NSPHY_10BTCR 0x1c /* 10baseT configuration */
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#endif /* _DEV_MII_NSPHYREG_H_ */
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