291 lines
8.3 KiB
C
291 lines
8.3 KiB
C
/* $OpenBSD: xhci_pci.c,v 1.12 2023/04/18 21:22:00 patrick Exp $ */
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/*
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* Copyright (c) 2001, 2002 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Lennart Augustsson (lennart@augustsson.net).
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/rwlock.h>
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#include <sys/device.h>
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#include <sys/timeout.h>
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#include <sys/queue.h>
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#include <machine/bus.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/pci/pcivar.h>
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#include <dev/usb/usb.h>
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#include <dev/usb/usbdi.h>
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#include <dev/usb/usbdivar.h>
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#include <dev/usb/usb_mem.h>
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#include <dev/usb/xhcireg.h>
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#include <dev/usb/xhcivar.h>
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#ifdef XHCI_DEBUG
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#define DPRINTF(x) if (xhcidebug) printf x
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extern int xhcidebug;
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#else
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#define DPRINTF(x)
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#endif
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struct xhci_pci_softc {
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struct xhci_softc sc;
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pci_chipset_tag_t sc_pc;
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pcitag_t sc_tag;
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pcireg_t sc_id;
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void *sc_ih; /* interrupt vectoring */
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};
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int xhci_pci_match(struct device *, void *, void *);
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void xhci_pci_attach(struct device *, struct device *, void *);
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int xhci_pci_detach(struct device *, int);
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int xhci_pci_activate(struct device *, int);
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void xhci_pci_takecontroller(struct xhci_pci_softc *, int);
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const struct cfattach xhci_pci_ca = {
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sizeof(struct xhci_pci_softc), xhci_pci_match, xhci_pci_attach,
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xhci_pci_detach, xhci_pci_activate
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};
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int
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xhci_pci_match(struct device *parent, void *match, void *aux)
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{
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struct pci_attach_args *pa = (struct pci_attach_args *) aux;
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if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SERIALBUS &&
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PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SERIALBUS_USB &&
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PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_XHCI)
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return (1);
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return (0);
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}
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static int
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xhci_pci_port_route(struct xhci_pci_softc *psc)
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{
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pcireg_t val;
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/*
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* Check USB3 Port Routing Mask register that indicates the ports
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* can be changed from OS, and turn on by USB3 Port SS Enable register.
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*/
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val = pci_conf_read(psc->sc_pc, psc->sc_tag, PCI_XHCI_INTEL_USB3PRM);
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DPRINTF(("%s: USB3PRM / USB3.0 configurable ports: 0x%08x\n",
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psc->sc.sc_bus.bdev.dv_xname, val));
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pci_conf_write(psc->sc_pc, psc->sc_tag, PCI_XHCI_INTEL_USB3_PSSEN, val);
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val = pci_conf_read(psc->sc_pc, psc->sc_tag, PCI_XHCI_INTEL_USB3_PSSEN);
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DPRINTF(("%s: USB3_PSSEN / Enabled USB3.0 ports under xHCI: 0x%08x\n",
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psc->sc.sc_bus.bdev.dv_xname, val));
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/*
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* Check USB2 Port Routing Mask register that indicates the USB2.0
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* ports to be controlled by xHCI HC, and switch them to xHCI HC.
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*/
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val = pci_conf_read(psc->sc_pc, psc->sc_tag, PCI_XHCI_INTEL_XUSB2PRM);
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DPRINTF(("%s: XUSB2PRM / USB2.0 ports can switch from EHCI to xHCI:"
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"0x%08x\n", psc->sc.sc_bus.bdev.dv_xname, val));
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pci_conf_write(psc->sc_pc, psc->sc_tag, PCI_XHCI_INTEL_XUSB2PR, val);
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val = pci_conf_read(psc->sc_pc, psc->sc_tag, PCI_XHCI_INTEL_XUSB2PR);
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DPRINTF(("%s: XUSB2PR / USB2.0 ports under xHCI: 0x%08x\n",
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psc->sc.sc_bus.bdev.dv_xname, val));
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return (0);
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}
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void
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xhci_pci_attach(struct device *parent, struct device *self, void *aux)
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{
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struct xhci_pci_softc *psc = (struct xhci_pci_softc *)self;
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struct pci_attach_args *pa = (struct pci_attach_args *)aux;
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const char *intrstr;
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const char *vendor;
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pci_intr_handle_t ih;
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pcireg_t reg;
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int error;
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reg = pci_mapreg_type(pa->pa_pc, pa->pa_tag, PCI_CBMEM);
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if (pci_mapreg_map(pa, PCI_CBMEM, reg, 0, &psc->sc.iot, &psc->sc.ioh,
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NULL, &psc->sc.sc_size, 0)) {
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printf(": can't map mem space\n");
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return;
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}
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psc->sc_pc = pa->pa_pc;
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psc->sc_tag = pa->pa_tag;
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psc->sc_id = pa->pa_id;
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psc->sc.sc_bus.dmatag = pa->pa_dmat;
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/* Handle quirks */
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switch (PCI_VENDOR(pa->pa_id)) {
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case PCI_VENDOR_FRESCO:
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/* FL1000 / FL1400 claim MSI support but do not support MSI */
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if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_FRESCO_FL1000 ||
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PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_FRESCO_FL1400)
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pa->pa_flags &= ~PCI_FLAGS_MSI_ENABLED;
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break;
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}
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/* Map and establish the interrupt. */
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if (pci_intr_map_msix(pa, 0, &ih) != 0 &&
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pci_intr_map_msi(pa, &ih) != 0 && pci_intr_map(pa, &ih) != 0) {
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printf(": couldn't map interrupt\n");
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goto unmap_ret;
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}
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intrstr = pci_intr_string(pa->pa_pc, ih);
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psc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_USB | IPL_MPSAFE,
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xhci_intr, psc, psc->sc.sc_bus.bdev.dv_xname);
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if (psc->sc_ih == NULL) {
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printf(": couldn't establish interrupt");
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if (intrstr != NULL)
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printf(" at %s", intrstr);
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printf("\n");
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goto unmap_ret;
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}
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printf(": %s", intrstr);
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/* Figure out vendor for root hub descriptor. */
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vendor = pci_findvendor(pa->pa_id);
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psc->sc.sc_id_vendor = PCI_VENDOR(pa->pa_id);
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if (vendor)
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strlcpy(psc->sc.sc_vendor, vendor, sizeof(psc->sc.sc_vendor));
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else
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snprintf(psc->sc.sc_vendor, sizeof(psc->sc.sc_vendor),
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"vendor 0x%04x", PCI_VENDOR(pa->pa_id));
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xhci_pci_takecontroller(psc, 0);
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if ((error = xhci_init(&psc->sc)) != 0) {
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printf("%s: init failed, error=%d\n",
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psc->sc.sc_bus.bdev.dv_xname, error);
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goto disestablish_ret;
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}
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if (PCI_VENDOR(psc->sc_id) == PCI_VENDOR_INTEL)
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xhci_pci_port_route(psc);
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/* Attach usb device. */
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config_found(self, &psc->sc.sc_bus, usbctlprint);
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/* Now that the stack is ready, config' the HC and enable interrupts. */
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xhci_config(&psc->sc);
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return;
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disestablish_ret:
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pci_intr_disestablish(psc->sc_pc, psc->sc_ih);
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unmap_ret:
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bus_space_unmap(psc->sc.iot, psc->sc.ioh, psc->sc.sc_size);
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}
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int
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xhci_pci_detach(struct device *self, int flags)
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{
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struct xhci_pci_softc *psc = (struct xhci_pci_softc *)self;
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int rv;
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rv = xhci_detach(self, flags);
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if (rv)
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return (rv);
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if (psc->sc_ih != NULL) {
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pci_intr_disestablish(psc->sc_pc, psc->sc_ih);
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psc->sc_ih = NULL;
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}
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if (psc->sc.sc_size) {
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bus_space_unmap(psc->sc.iot, psc->sc.ioh, psc->sc.sc_size);
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psc->sc.sc_size = 0;
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}
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return (0);
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}
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int
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xhci_pci_activate(struct device *self, int act)
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{
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struct xhci_pci_softc *psc = (struct xhci_pci_softc *)self;
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switch (act) {
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case DVACT_RESUME:
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if (PCI_VENDOR(psc->sc_id) == PCI_VENDOR_INTEL)
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xhci_pci_port_route(psc);
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break;
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default:
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break;
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}
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return (xhci_activate(self, act));
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}
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void
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xhci_pci_takecontroller(struct xhci_pci_softc *psc, int silent)
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{
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uint32_t cparams, xecp, eec;
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uint8_t bios_sem;
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int i;
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cparams = XREAD4(&psc->sc, XHCI_HCCPARAMS);
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if (cparams == 0xffffffff)
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return;
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eec = -1;
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/* Synchronise with the BIOS if it owns the controller. */
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for (xecp = XHCI_HCC_XECP(cparams) << 2;
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xecp != 0 && XHCI_XECP_NEXT(eec);
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xecp += XHCI_XECP_NEXT(eec) << 2) {
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eec = XREAD4(&psc->sc, xecp);
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if (eec == 0xffffffff)
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return;
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if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY)
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continue;
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bios_sem = XREAD1(&psc->sc, xecp + XHCI_XECP_BIOS_SEM);
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if (bios_sem) {
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XWRITE1(&psc->sc, xecp + XHCI_XECP_OS_SEM, 1);
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DPRINTF(("%s: waiting for BIOS to give up control\n",
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psc->sc.sc_bus.bdev.dv_xname));
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for (i = 0; i < 5000; i++) {
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bios_sem = XREAD1(&psc->sc, xecp +
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XHCI_XECP_BIOS_SEM);
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if (bios_sem == 0)
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break;
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DELAY(1000);
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}
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if (silent == 0 && bios_sem)
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printf("%s: timed out waiting for BIOS\n",
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psc->sc.sc_bus.bdev.dv_xname);
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}
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}
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}
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