293 lines
14 KiB
C
293 lines
14 KiB
C
/* $OpenBSD: ahcireg.h,v 1.6 2024/04/23 13:09:21 jsg Exp $ */
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/*
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* Copyright (c) 2006 David Gwynne <dlg@openbsd.org>
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* Copyright (c) 2010 Conformal Systems LLC <info@conformal.com>
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* Copyright (c) 2010 Jonathan Matthew <jonathan@d14n.org>
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#define AHCI_REG_CAP 0x000 /* HBA Capabilities */
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#define AHCI_REG_CAP_NP(_r) (((_r) & 0x1f)+1) /* Number of Ports */
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#define AHCI_REG_CAP_SXS (1<<5) /* External SATA */
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#define AHCI_REG_CAP_EMS (1<<6) /* Enclosure Mgmt */
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#define AHCI_REG_CAP_CCCS (1<<7) /* Cmd Coalescing */
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#define AHCI_REG_CAP_NCS(_r) ((((_r) & 0x1f00)>>8)+1) /* NCmds*/
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#define AHCI_REG_CAP_PSC (1<<13) /* Partial State Capable */
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#define AHCI_REG_CAP_SSC (1<<14) /* Slumber State Capable */
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#define AHCI_REG_CAP_PMD (1<<15) /* PIO Multiple DRQ Block */
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#define AHCI_REG_CAP_FBSS (1<<16) /* FIS-Based Switching */
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#define AHCI_REG_CAP_SPM (1<<17) /* Port Multiplier */
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#define AHCI_REG_CAP_SAM (1<<18) /* AHCI Only mode */
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#define AHCI_REG_CAP_SNZO (1<<19) /* Non Zero DMA Offsets */
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#define AHCI_REG_CAP_ISS (0xf<<20) /* Interface Speed Support */
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#define AHCI_REG_CAP_ISS_G1 (0x1<<20) /* Gen 1 (1.5 Gbps) */
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#define AHCI_REG_CAP_ISS_G2 (0x2<<20) /* Gen 2 (3 Gbps) */
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#define AHCI_REG_CAP_ISS_G3 (0x3<<20) /* Gen 3 (6 Gbps) */
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#define AHCI_REG_CAP_SCLO (1<<24) /* Cmd List Override */
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#define AHCI_REG_CAP_SAL (1<<25) /* Activity LED */
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#define AHCI_REG_CAP_SALP (1<<26) /* Aggressive Link Pwr Mgmt */
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#define AHCI_REG_CAP_SSS (1<<27) /* Staggered Spinup */
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#define AHCI_REG_CAP_SMPS (1<<28) /* Mech Presence Switch */
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#define AHCI_REG_CAP_SSNTF (1<<29) /* SNotification Register */
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#define AHCI_REG_CAP_SNCQ (1<<30) /* Native Cmd Queuing */
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#define AHCI_REG_CAP_S64A (1U<<31) /* 64bit Addressing */
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#define AHCI_FMT_CAP "\020" "\040S64A" "\037NCQ" "\036SSNTF" \
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"\035SMPS" "\034SSS" "\033SALP" "\032SAL" \
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"\031SCLO" "\024SNZO" "\023SAM" "\022SPM" \
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"\021FBSS" "\020PMD" "\017SSC" "\016PSC" \
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"\010CCCS" "\007EMS" "\006SXS"
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#define AHCI_REG_GHC 0x004 /* Global HBA Control */
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#define AHCI_REG_GHC_HR (1<<0) /* HBA Reset */
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#define AHCI_REG_GHC_IE (1<<1) /* Interrupt Enable */
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#define AHCI_REG_GHC_MRSM (1<<2) /* MSI Revert to Single Msg */
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#define AHCI_REG_GHC_AE (1U<<31) /* AHCI Enable */
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#define AHCI_FMT_GHC "\020" "\040AE" "\003MRSM" "\002IE" "\001HR"
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#define AHCI_REG_IS 0x008 /* Interrupt Status */
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#define AHCI_REG_PI 0x00c /* Ports Implemented */
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#define AHCI_REG_VS 0x010 /* AHCI Version */
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#define AHCI_REG_VS_0_95 0x00000905 /* 0.95 */
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#define AHCI_REG_VS_1_0 0x00010000 /* 1.0 */
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#define AHCI_REG_VS_1_1 0x00010100 /* 1.1 */
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#define AHCI_REG_VS_1_2 0x00010200 /* 1.2 */
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#define AHCI_REG_VS_1_3 0x00010300 /* 1.3 */
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#define AHCI_REG_VS_1_3_1 0x00010301 /* 1.3.1 */
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#define AHCI_REG_CCC_CTL 0x014 /* Coalescing Control */
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#define AHCI_REG_CCC_CTL_INT(_r) (((_r) & 0xf8) >> 3) /* CCC INT slot */
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#define AHCI_REG_CCC_PORTS 0x018 /* Coalescing Ports */
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#define AHCI_REG_EM_LOC 0x01c /* Enclosure Mgmt Location */
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#define AHCI_REG_EM_CTL 0x020 /* Enclosure Mgmt Control */
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#define AHCI_REG_CAP2 0x024 /* HBA Capabilities Extended */
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#define AHCI_REG_CAP2_DESO (1<<5) /* DevSlp from slumber only */
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#define AHCI_REG_CAP2_SADM (1<<4) /* Aggro DevSlp mgmt */
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#define AHCI_REG_CAP2_SDS (1<<3) /* Supports DevSlp */
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#define AHCI_REG_CAP2_APST (1<<2) /* Auto partial->slumber */
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#define AHCI_REG_CAP2_NVMP (1<<1) /* NVMHCI present */
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#define AHCI_REG_CAP2_BOH (1<<0) /* BIOS/OS handoff */
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#define AHCI_FMT_CAP2 "\020" "\006DESO" "\005SADM" "\004SDS" \
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"\003APST" "\002NVMP" "\001BOH"
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#define AHCI_PORT_REGION(_p) (0x100 + ((_p) * 0x80))
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#define AHCI_PORT_SIZE 0x80
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#define AHCI_PREG_CLB 0x00 /* Cmd List Base Addr */
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#define AHCI_PREG_CLBU 0x04 /* Cmd List Base Hi Addr */
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#define AHCI_PREG_FB 0x08 /* FIS Base Addr */
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#define AHCI_PREG_FBU 0x0c /* FIS Base Hi Addr */
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#define AHCI_PREG_IS 0x10 /* Interrupt Status */
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#define AHCI_PREG_IS_DHRS (1<<0) /* Device to Host FIS */
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#define AHCI_PREG_IS_PSS (1<<1) /* PIO Setup FIS */
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#define AHCI_PREG_IS_DSS (1<<2) /* DMA Setup FIS */
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#define AHCI_PREG_IS_SDBS (1<<3) /* Set Device Bits FIS */
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#define AHCI_PREG_IS_UFS (1<<4) /* Unknown FIS */
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#define AHCI_PREG_IS_DPS (1<<5) /* Descriptor Processed */
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#define AHCI_PREG_IS_PCS (1<<6) /* Port Change */
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#define AHCI_PREG_IS_DMPS (1<<7) /* Device Mechanical Presence */
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#define AHCI_PREG_IS_PRCS (1<<22) /* PhyRdy Change */
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#define AHCI_PREG_IS_IPMS (1<<23) /* Incorrect Port Multiplier */
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#define AHCI_PREG_IS_OFS (1<<24) /* Overflow */
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#define AHCI_PREG_IS_INFS (1<<26) /* Interface Non-fatal Error */
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#define AHCI_PREG_IS_IFS (1<<27) /* Interface Fatal Error */
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#define AHCI_PREG_IS_HBDS (1<<28) /* Host Bus Data Error */
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#define AHCI_PREG_IS_HBFS (1<<29) /* Host Bus Fatal Error */
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#define AHCI_PREG_IS_TFES (1<<30) /* Task File Error */
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#define AHCI_PREG_IS_CPDS (1U<<31) /* Cold Presence Detect */
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#define AHCI_PFMT_IS "\20" "\040CPDS" "\037TFES" "\036HBFS" \
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"\035HBDS" "\034IFS" "\033INFS" "\031OFS" \
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"\030IPMS" "\027PRCS" "\010DMPS" "\006DPS" \
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"\007PCS" "\005UFS" "\004SDBS" "\003DSS" \
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"\002PSS" "\001DHRS"
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#define AHCI_PREG_IE 0x14 /* Interrupt Enable */
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#define AHCI_PREG_IE_DHRE (1<<0) /* Device to Host FIS */
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#define AHCI_PREG_IE_PSE (1<<1) /* PIO Setup FIS */
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#define AHCI_PREG_IE_DSE (1<<2) /* DMA Setup FIS */
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#define AHCI_PREG_IE_SDBE (1<<3) /* Set Device Bits FIS */
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#define AHCI_PREG_IE_UFE (1<<4) /* Unknown FIS */
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#define AHCI_PREG_IE_DPE (1<<5) /* Descriptor Processed */
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#define AHCI_PREG_IE_PCE (1<<6) /* Port Change */
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#define AHCI_PREG_IE_DMPE (1<<7) /* Device Mechanical Presence */
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#define AHCI_PREG_IE_PRCE (1<<22) /* PhyRdy Change */
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#define AHCI_PREG_IE_IPME (1<<23) /* Incorrect Port Multiplier */
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#define AHCI_PREG_IE_OFE (1<<24) /* Overflow */
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#define AHCI_PREG_IE_INFE (1<<26) /* Interface Non-fatal Error */
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#define AHCI_PREG_IE_IFE (1<<27) /* Interface Fatal Error */
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#define AHCI_PREG_IE_HBDE (1<<28) /* Host Bus Data Error */
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#define AHCI_PREG_IE_HBFE (1<<29) /* Host Bus Fatal Error */
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#define AHCI_PREG_IE_TFEE (1<<30) /* Task File Error */
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#define AHCI_PREG_IE_CPDE (1U<<31) /* Cold Presence Detect */
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#define AHCI_PFMT_IE "\20" "\040CPDE" "\037TFEE" "\036HBFE" \
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"\035HBDE" "\034IFE" "\033INFE" "\031OFE" \
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"\030IPME" "\027PRCE" "\010DMPE" "\007PCE" \
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"\006DPE" "\005UFE" "\004SDBE" "\003DSE" \
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"\002PSE" "\001DHRE"
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#define AHCI_PREG_CMD 0x18 /* Command and Status */
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#define AHCI_PREG_CMD_ST (1<<0) /* Start */
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#define AHCI_PREG_CMD_SUD (1<<1) /* Spin Up Device */
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#define AHCI_PREG_CMD_POD (1<<2) /* Power On Device */
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#define AHCI_PREG_CMD_CLO (1<<3) /* Command List Override */
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#define AHCI_PREG_CMD_FRE (1<<4) /* FIS Receive Enable */
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#define AHCI_PREG_CMD_CCS(_r) (((_r) >> 8) & 0x1f) /* Curr CmdSlot# */
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#define AHCI_PREG_CMD_MPSS (1<<13) /* Mech Presence State */
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#define AHCI_PREG_CMD_FR (1<<14) /* FIS Receive Running */
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#define AHCI_PREG_CMD_CR (1<<15) /* Command List Running */
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#define AHCI_PREG_CMD_CPS (1<<16) /* Cold Presence State */
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#define AHCI_PREG_CMD_PMA (1<<17) /* Port Multiplier Attached */
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#define AHCI_PREG_CMD_HPCP (1<<18) /* Hot Plug Capable */
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#define AHCI_PREG_CMD_MPSP (1<<19) /* Mech Presence Switch */
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#define AHCI_PREG_CMD_CPD (1<<20) /* Cold Presence Detection */
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#define AHCI_PREG_CMD_ESP (1<<21) /* External SATA Port */
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#define AHCI_PREG_CMD_ATAPI (1<<24) /* Device is ATAPI */
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#define AHCI_PREG_CMD_DLAE (1<<25) /* Drv LED on ATAPI Enable */
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#define AHCI_PREG_CMD_ALPE (1<<26) /* Aggro Pwr Mgmt Enable */
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#define AHCI_PREG_CMD_ASP (1<<27) /* Aggro Slumber/Partial */
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#define AHCI_PREG_CMD_ICC 0xf0000000 /* Interface Comm Ctrl */
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#define AHCI_PREG_CMD_ICC_SLUMBER 0x60000000
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#define AHCI_PREG_CMD_ICC_PARTIAL 0x20000000
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#define AHCI_PREG_CMD_ICC_ACTIVE 0x10000000
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#define AHCI_PREG_CMD_ICC_IDLE 0x00000000
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#define AHCI_PFMT_CMD "\020" "\034ASP" "\033ALPE" "\032DLAE" \
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"\031ATAPI" "\026ESP" "\025CPD" "\024MPSP" \
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"\023HPCP" "\022PMA" "\021CPS" "\020CR" \
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"\017FR" "\016MPSS" "\005FRE" "\004CLO" \
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"\003POD" "\002SUD" "\001ST"
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#define AHCI_PREG_TFD 0x20 /* Task File Data*/
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#define AHCI_PREG_TFD_STS 0xff
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#define AHCI_PREG_TFD_STS_ERR (1<<0)
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#define AHCI_PREG_TFD_STS_DRQ (1<<3)
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#define AHCI_PREG_TFD_STS_BSY (1<<7)
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#define AHCI_PREG_TFD_ERR 0xff00
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#define AHCI_PFMT_TFD_STS "\20" "\010BSY" "\004DRQ" "\001ERR"
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#define AHCI_PREG_SIG 0x24 /* Signature */
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#define AHCI_PREG_SSTS 0x28 /* SATA Status */
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#define AHCI_PREG_SSTS_DET 0xf /* Device Detection */
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#define AHCI_PREG_SSTS_DET_NONE 0x0
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#define AHCI_PREG_SSTS_DET_DEV_NE 0x1
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#define AHCI_PREG_SSTS_DET_DEV 0x3
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#define AHCI_PREG_SSTS_DET_PHYOFFLINE 0x4
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#define AHCI_PREG_SSTS_SPD 0xf0 /* Current Interface Speed */
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#define AHCI_PREG_SSTS_SPD_NONE 0x00
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#define AHCI_PREG_SSTS_SPD_GEN1 0x10
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#define AHCI_PREG_SSTS_SPD_GEN2 0x20
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#define AHCI_PREG_SSTS_SPD_GEN3 0x30
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#define AHCI_PREG_SSTS_IPM 0xf00 /* Interface Power Management */
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#define AHCI_PREG_SSTS_IPM_NONE 0x000
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#define AHCI_PREG_SSTS_IPM_ACTIVE 0x100
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#define AHCI_PREG_SSTS_IPM_PARTIAL 0x200
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#define AHCI_PREG_SSTS_IPM_SLUMBER 0x600
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#define AHCI_PREG_SCTL 0x2c /* SATA Control */
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#define AHCI_PREG_SCTL_DET 0xf /* Device Detection */
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#define AHCI_PREG_SCTL_DET_NONE 0x0
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#define AHCI_PREG_SCTL_DET_INIT 0x1
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#define AHCI_PREG_SCTL_DET_DISABLE 0x4
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#define AHCI_PREG_SCTL_SPD 0xf0 /* Speed Allowed */
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#define AHCI_PREG_SCTL_SPD_ANY 0x00
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#define AHCI_PREG_SCTL_SPD_GEN1 0x10
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#define AHCI_PREG_SCTL_SPD_GEN2 0x20
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#define AHCI_PREG_SCTL_SPD_GEN3 0x30
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#define AHCI_PREG_SCTL_IPM 0xf00 /* Interface Power Management */
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#define AHCI_PREG_SCTL_IPM_NONE 0x000
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#define AHCI_PREG_SCTL_IPM_NOPARTIAL 0x100
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#define AHCI_PREG_SCTL_IPM_NOSLUMBER 0x200
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#define AHCI_PREG_SCTL_IPM_DISABLED 0x300
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#define AHCI_PREG_SERR 0x30 /* SATA Error */
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#define AHCI_PREG_SERR_ERR(_r) ((_r) & 0xffff)
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#define AHCI_PREG_SERR_ERR_I (1<<0) /* Recovered Data Integrity */
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#define AHCI_PREG_SERR_ERR_M (1<<1) /* Recovered Communications */
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#define AHCI_PREG_SERR_ERR_T (1<<8) /* Transient Data Integrity */
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#define AHCI_PREG_SERR_ERR_C (1<<9) /* Persistent Comm/Data */
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#define AHCI_PREG_SERR_ERR_P (1<<10) /* Protocol */
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#define AHCI_PREG_SERR_ERR_E (1<<11) /* Internal */
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#define AHCI_PFMT_SERR_ERR "\020" "\014E" "\013P" "\012C" "\011T" "\002M" \
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"\001I"
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#define AHCI_PREG_SERR_DIAG(_r) (((_r) >> 16) & 0xffff)
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#define AHCI_PREG_SERR_DIAG_N (1<<0) /* PhyRdy Change */
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#define AHCI_PREG_SERR_DIAG_I (1<<1) /* Phy Internal Error */
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#define AHCI_PREG_SERR_DIAG_W (1<<2) /* Comm Wake */
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#define AHCI_PREG_SERR_DIAG_B (1<<3) /* 10B to 8B Decode Error */
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#define AHCI_PREG_SERR_DIAG_D (1<<4) /* Disparity Error */
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#define AHCI_PREG_SERR_DIAG_C (1<<5) /* CRC Error */
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#define AHCI_PREG_SERR_DIAG_H (1<<6) /* Handshake Error */
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#define AHCI_PREG_SERR_DIAG_S (1<<7) /* Link Sequence Error */
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#define AHCI_PREG_SERR_DIAG_T (1<<8) /* Transport State Trans Err */
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#define AHCI_PREG_SERR_DIAG_F (1<<9) /* Unknown FIS Type */
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#define AHCI_PREG_SERR_DIAG_X (1<<10) /* Exchanged */
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#define AHCI_PFMT_SERR_DIAG "\020" "\013X" "\012F" "\011T" "\010S" "\007H" \
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"\006C" "\005D" "\004B" "\003W" "\002I" \
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"\001N"
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#define AHCI_PREG_SACT 0x34 /* SATA Active */
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#define AHCI_PREG_CI 0x38 /* Command Issue */
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#define AHCI_PREG_CI_ALL_SLOTS 0xffffffff
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#define AHCI_PREG_SNTF 0x3c /* SNotification */
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#define AHCI_PREG_FBS 0x40 /* FIS-based Switching Control */
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#define AHCI_PREG_FBS_DWE 0xf0000 /* Device With Error */
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#define AHCI_PREG_FBS_ADO 0xf000 /* Active Device Optimization */
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#define AHCI_PREG_FBS_DEV 0xf00 /* Device To Issue */
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#define AHCI_PREG_FBS_SDE (1<<2) /* Single Device Error */
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#define AHCI_PREG_FBS_DEC (1<<1) /* Device Error Clear */
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#define AHCI_PREG_FBS_EN (1<<0) /* Enable */
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struct ahci_cmd_hdr {
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u_int16_t flags;
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#define AHCI_CMD_LIST_FLAG_CFL 0x001f /* Command FIS Length */
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#define AHCI_CMD_LIST_FLAG_A (1<<5) /* ATAPI */
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#define AHCI_CMD_LIST_FLAG_W (1<<6) /* Write */
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#define AHCI_CMD_LIST_FLAG_P (1<<7) /* Prefetchable */
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#define AHCI_CMD_LIST_FLAG_R (1<<8) /* Reset */
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#define AHCI_CMD_LIST_FLAG_B (1<<9) /* BIST */
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#define AHCI_CMD_LIST_FLAG_C (1<<10) /* Clear Busy upon R_OK */
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#define AHCI_CMD_LIST_FLAG_PMP 0xf000 /* Port Multiplier Port */
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#define AHCI_CMD_LIST_FLAG_PMP_SHIFT 12
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u_int16_t prdtl; /* sgl len */
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u_int32_t prdbc; /* transferred byte count */
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u_int64_t ctba;
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u_int32_t reserved[4];
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} __packed __aligned(8);
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struct ahci_rfis {
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u_int8_t dsfis[28];
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u_int8_t reserved1[4];
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u_int8_t psfis[24];
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u_int8_t reserved2[8];
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u_int8_t rfis[24];
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u_int8_t reserved3[4];
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u_int8_t sdbfis[4];
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u_int8_t ufis[64];
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u_int8_t reserved4[96];
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} __packed;
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struct ahci_prdt {
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u_int64_t dba;
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u_int32_t reserved;
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u_int32_t flags;
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#define AHCI_PRDT_FLAG_INTR (1U<<31) /* interrupt on completion */
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} __packed __aligned(8);
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/* this makes ahci_cmd_table 512 bytes, supporting 128-byte alignment */
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#define AHCI_MAX_PRDT 24
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struct ahci_cmd_table {
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u_int8_t cfis[64]; /* Command FIS */
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u_int8_t acmd[16]; /* ATAPI Command */
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u_int8_t reserved[48];
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struct ahci_prdt prdt[AHCI_MAX_PRDT];
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} __packed __aligned(128);
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#define AHCI_MAX_PORTS 32
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