501 lines
14 KiB
C
501 lines
14 KiB
C
/* $OpenBSD: cissreg.h,v 1.12 2022/01/09 05:42:38 jsg Exp $ */
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/*
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* Copyright (c) 2005,2006 Michael Shalayeff
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* All rights reserved.
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF MIND, USE, DATA OR PROFITS, WHETHER IN
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* AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
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* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#define CISS_BIGBIT 0x80 /* texas radio and the big beat! */
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#define CISS_IDB 0x20
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#define CISS_IDB_CFG 0x01
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#define CISS_ISR 0x30
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#define CISS_IMR 0x34
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#define CISS_READYENAB 4
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#define CISS_READYENA 8
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#define CISS_INQ 0x40
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#define CISS_OUTQ 0x44
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#define CISS_CFG_BAR 0xb4
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#define CISS_CFG_OFF 0xb8
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/* 64bit FIFO mode input/output post queues */
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#define CISS_INQ64_LO 0xc0
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#define CISS_INQ64_HI 0xc4
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#define CISS_OUTQ64_LO 0xc8
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#define CISS_OUTQ64_HI 0xcc
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#define CISS_DRVMAP_SIZE (128 / 8)
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#define CISS_CMD_CTRL_GET 0x26
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#define CISS_CMD_CTRL_SET 0x27
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/* sub-commands for GET/SET */
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#define CISS_CMS_CTRL_LDID 0x10
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#define CISS_CMS_CTRL_CTRL 0x11
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#define CISS_CMS_CTRL_LDSTAT 0x12
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#define CISS_CMS_CTRL_PDID 0x15
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#define CISS_CMS_CTRL_PDBLINK 0x16
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#define CISS_CMS_CTRL_PDBLSENS 0x17
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#define CISS_CMS_CTRL_LDIDEXT 0x18
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#define CISS_CMS_CTRL_REDSTAT 0x82
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#define CISS_CMS_CTRL_FLUSH 0xc2
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#define CISS_CMS_CTRL_ACCEPT 0xe0
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#define CISS_CMD_READ 0xc0
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#define CISS_CMD_READ_EVENT 0xd0
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#define CISS_EVENT_RECENT 0x08 /* ignore previous events */
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#define CISS_EVENT_RSTOLD 0x04 /* start w/ the oldest one */
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#define CISS_EVENT_ORDER 0x02 /* keep the order */
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#define CISS_EVENT_SYNC 0x01 /* sync mode: wait till new come */
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#define CISS_CMD_LDMAP 0xc2
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#define CISS_CMD_PDMAP 0xc3
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#define ciss_bitset(d, v) ((v)[(d) >> 3] & (1 << ((d) & 7)))
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struct ciss_softc;
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struct ciss_config {
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u_int32_t signature;
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#define CISS_SIGNATURE (*(u_int32_t *)"CISS")
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u_int32_t version;
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u_int32_t methods;
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#define CISS_METH_READY 0x00000001 /* indicate to accept commands */
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#define CISS_METH_SIMPL 0x00000002 /* simple mode */
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#define CISS_METH_PERF 0x00000004 /* performant mode */
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#define CISS_METH_EMQ 0x00000008 /* MEMQ method */
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#define CISS_METH_BIT63 0x08000000 /* address bit 63 is valid */
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#define CISS_METH_FIFO64_RRO 0x10000000 /* 64bit FIFO reverse read order */
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#define CISS_METH_SHORT_TAG 0x20000000 /* short 4 byte tag support */
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#define CISS_METH_MSIX 0x40000000 /* directed MSI-X support */
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#define CISS_METH_FIFO64 0x80000000 /* 64bit FIFO support */
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u_int32_t amethod;
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u_int32_t rmethod;
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u_int32_t paddr_lim;
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u_int32_t int_delay;
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u_int32_t int_count;
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u_int32_t maxcmd;
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u_int32_t scsibus;
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#define CISS_BUS_U2 0x0001
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#define CISS_BUS_U3 0x0002
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#define CISS_BUS_FC1 0x0100
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#define CISS_BUS_FC2 0x0200
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u_int32_t troff;
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u_int8_t hostname[16];
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u_int32_t heartbeat;
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u_int32_t driverf;
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#define CISS_DRV_UATT 0x0001
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#define CISS_DRV_QINI 0x0002
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#define CISS_DRV_LCKINT 0x0004
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#define CISS_DRV_QTAGS 0x0008
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#define CISS_DRV_ALPHA 0x0010
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#define CISS_DRV_LUNS 0x0020
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#define CISS_DRV_MSGRQ 0x0080
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#define CISS_DRV_DBRD 0x0100
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#define CISS_DRV_PRF 0x0200
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u_int32_t maxsg;
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} __packed;
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struct ciss_inquiry {
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u_int8_t numld;
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u_int8_t sign[4];
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u_int8_t fw_running[4];
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u_int8_t fw_stored[4];
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u_int8_t hw_rev;
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u_int8_t resv0[12];
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u_int16_t pci_vendor;
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u_int16_t pci_product;
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u_int8_t resv1[10];
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u_int8_t market_rev;
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u_int8_t flags;
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#define CISS_INQ_WIDE 0x08
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#define CISS_INQ_BIGMAP 0x80
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#define CISS_INQ_BITS "\020\04WIDE\010BIGMAP"
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u_int8_t resv2[2];
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u_int8_t nscsi_bus;
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u_int8_t resv3[4];
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u_int8_t clk[4]; /* unaligned dumbness */
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u_int8_t buswidth;
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u_int8_t disks[CISS_DRVMAP_SIZE];
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u_int8_t extdisks[CISS_DRVMAP_SIZE];
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u_int8_t nondisks[CISS_DRVMAP_SIZE];
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} __packed;
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struct ciss_ldmap {
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u_int32_t size;
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u_int32_t resv;
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struct {
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u_int32_t tgt;
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u_int32_t tgt2;
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} map[1];
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} __packed;
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struct ciss_flush {
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u_int16_t flush;
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#define CISS_FLUSH_ENABLE 0
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#define CISS_FLUSH_DISABLE 1
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u_int16_t resv[255];
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} __packed;
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struct ciss_blink {
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u_int32_t duration; /* x100ms */
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u_int32_t elapsed; /* only for sense */
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u_int8_t pdtab[256];
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#define CISS_BLINK_ALL 1
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#define CISS_BLINK_TIMED 2
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u_int8_t res[248];
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} __packed;
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struct ciss_ldid {
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u_int16_t blksize;
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u_int16_t nblocks[2]; /* UNALIGNED! */
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u_int8_t params[16];
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u_int8_t type;
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#define CISS_LD_RAID0 0
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#define CISS_LD_RAID4 1
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#define CISS_LD_RAID1 2
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#define CISS_LD_RAID5 3
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#define CISS_LD_RAID51 4
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#define CISS_LD_RAIDADG 5
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u_int8_t res0;
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u_int8_t bios_dis;
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u_int8_t res1;
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u_int32_t id;
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u_int8_t label[64];
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u_int64_t nbigblocks;
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u_int8_t res2[410];
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} __packed;
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struct ciss_ldstat {
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u_int8_t stat;
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#define CISS_LD_OK 0
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#define CISS_LD_FAILED 1
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#define CISS_LD_UNCONF 2
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#define CISS_LD_DEGRAD 3
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#define CISS_LD_RBLDRD 4 /* ready for rebuild */
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#define CISS_LD_REBLD 5
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#define CISS_LD_PDINV 6 /* wrong phys drive replaced */
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#define CISS_LD_PDUNC 7 /* phys drive is not connected proper */
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#define CISS_LD_EXPND 10 /* expanding */
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#define CISS_LD_NORDY 11 /* volume is not ready */
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#define CISS_LD_QEXPND 12 /* queued for expansion */
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u_int8_t failed[4]; /* failed map */
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u_int8_t res0[416];
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u_int8_t prog[4]; /* blocks left to rebuild/expand */
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u_int8_t rebuild; /* drive that is rebuilding */
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u_int16_t remapcnt[32]; /* count of re3mapped blocks for pds */
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u_int8_t replaced[4]; /* replaced drives map */
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u_int8_t spare[4]; /* used spares map */
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u_int8_t sparestat; /* spare status */
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#define CISS_LD_CONF 0x01 /* spare configured */
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#define CISS_LD_RBLD 0x02 /* spare is used and rebuilding */
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#define CISS_LD_DONE 0x04 /* spare rebuild done */
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#define CISS_LD_FAIL 0x08 /* at least one spare drive has failed */
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#define CISS_LD_USED 0x10 /* at least one spare drive is used */
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#define CISS_LD_AVAIL 0x20 /* at least one spare is available */
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u_int8_t sparemap[32]; /* spare->pd replacement map */
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u_int8_t replok[4]; /* replaced failed map */
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u_int8_t readyok; /* ready to become ok */
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u_int8_t memfail; /* cache mem failure */
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u_int8_t expfail; /* expansion failure */
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u_int8_t rebldfail; /* rebuild failure */
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#define CISS_LD_RBLD_READ 0x01 /* read failed */
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#define CISS_LD_RBLD_WRITE 0x02 /* write fail */
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u_int8_t bigfailed[16]; /* bigmap vers of same of the above */
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u_int8_t bigremapcnt[256];
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u_int8_t bigreplaced[16];
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u_int8_t bigspare[16];
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u_int8_t bigsparemap[128];
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u_int8_t bigreplok[16];
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u_int8_t bigrebuild; /* big-number rebuilding driveno */
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} __packed;
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struct ciss_pdid {
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u_int8_t bus;
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u_int8_t target;
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u_int16_t blksz;
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u_int32_t nblocks;
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u_int32_t resblks;
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u_int8_t model[40];
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u_int8_t serial[40];
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u_int8_t revision[8];
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u_int8_t bits;
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u_int8_t res0[2];
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u_int8_t present;
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#define CISS_PD_PRESENT 0x01
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#define CISS_PD_NONDSK 0x02
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#define CISS_PD_WIDE 0x04
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#define CISS_PD_SYNC 0x08
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#define CISS_PD_NARROW 0x10
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#define CISS_PD_W2NARR 0x20 /* wide downgrade to narrow */
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#define CISS_PD_ULTRA 0x40
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#define CISS_PD_ULTRA2 0x80
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u_int8_t config;
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#define CISS_PD_SMART 0x01
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#define CISS_PD_SMERRR 0x02
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#define CISS_PD_SMERRE 0x04
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#define CISS_PD_SMERRD 0x08
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#define CISS_PD_EXT 0x10
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#define CISS_PD_CONF 0x20
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#define CISS_PD_SPARE 0x40
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#define CISS_PD_CASAVE 0x80
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u_int8_t res1;
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u_int8_t cache;
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#define CISS_PD_CACHE 0x01
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#define CISS_PD_CASAFE 0x01
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u_int8_t res2[5];
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u_int8_t connector[2];
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u_int8_t res3;
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u_int8_t bay;
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u_int16_t rpm;
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u_int8_t type;
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u_int8_t res4[393];
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} __packed;
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struct ciss_event {
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u_int32_t reltime; /* time since controller boot */
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u_int16_t event;
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#define CISS_EVCLS_PROTO 0
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#define CISS_EVCLS_PLUG 1
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#define CISS_EVCLS_HW 2
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#define CISS_EVCLS_ENV 3
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#define CISS_EVCLS_PD 4 /* ciss_evpdchg in details */
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#define CISS_EVCLS_LD 5
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#define CISS_EVCLS_CTRL 6
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#define CISS_EVCLS_CISS 8 /* funky errors */
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#define CISS_EVCLS_RESV 9
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u_int16_t subevent;
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#define CISS_EVPROTO_STAT 0
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#define CISS_EVPROTO_ERR 1
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#define CISS_EVPLUG_PDCHG 0 /* ciss_evpdchg */
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#define CISS_EVPLUG_POWER 1 /* ciss_evpschg */
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#define CISS_EVPLUG_FAN 2 /* ciss_evfanchg */
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#define CISS_EVPLUG_UPS 3 /* ciss_evupschg */
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#define CISS_EVPLUG_CTRL 4 /* ciss_evctrlchg: ctrl removed? (; */
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#define CISS_EVHW_CABLES 0
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#define CISS_EVHW_MEMORY 1
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#define CISS_EVHW_FAN 2 /* detail as in CISS_EVPLUG_FAN */
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#define CISS_EVHW_VRM 3
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#define CISS_EVENV_TEMP 0 /* ciss_evtempchg */
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#define CISS_EVENV_PS 1
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#define CISS_EVENV_CHASSIS 2
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#define CISS_EVENV_AC 3
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#define CISS_EVPD_STAT 0
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#define CISS_EVLD_STAT 0
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#define CISS_EVLD_ERR 1
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#define CISS_EVLD_CHECK 2 /* surface check */
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#define CISS_EVCTRL_STAT 0
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u_int16_t detail;
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#define CISS_EVSTAT_NONE 0
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#define CISS_EVSTAT_DISABLE 1
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#define CISS_EVSTAT_TMO 2 /* async event poll timeout */
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#define CISS_EVERR_OVERFLOW 0 /* event queue overflow */
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#define CISS_EVPLUG_REMOVE 0
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#define CISS_EVPLUG_INSERT 1
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#define CISS_EVFAN_FAULT 0
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#define CISS_EVFAN_DEGRADED 1
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#define CISS_EVFAN_OK 2
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#define CISS_EVVRM_REMOVE 0
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#define CISS_EVVRM_INSERT 1
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#define CISS_EVVRM_FAILED 2
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#define CISS_EVVRM_OK 3
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#define CISS_EVTEMP_LIMEX 0 /* limit exceeded */
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#define CISS_EVTEMP_WARN 1
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#define CISS_EVTEMP_OK 2
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#define CISS_EVPS_FAIL 0
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#define CISS_EVPS_OK 2
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#define CISS_EVCHAS_OPEN 0
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#define CISS_EVCHAS_CLOSE 2
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#define CISS_EVAC_FAIL 0
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#define CISS_EVAC_BATTLOW 1
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#define CISS_EVPDSTAT_FAIL 0
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#define CISS_EVLDSTAT_CHG 0 /* ciss_evldchg */
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#define CISS_EVLDSTAT_EXMEDIA 1 /* untolerant cfg got drive replaced */
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#define CISS_EVLDSTAT_RERDERR 2 /* ciss_evldrblderr */
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#define CISS_EVLDSTAT_REWRERR 3 /* ciss_evldrblderr */
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#define CISS_EVLDERR_FATAL 0 /* ciss_evlderr */
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#define CISS_EVCHECK_DONE 0 /* details have onle 16bit ld num */
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#define CISS_EVCTRLSTAT_CHG 0 /* ciss_evctrlstat */
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u_int8_t data[64];
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u_int8_t msg[80];
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u_int32_t tag;
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u_int16_t monday;
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u_int16_t year;
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u_int32_t time;
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u_int16_t presec; /* time for events before boot */
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u_int8_t device[8];
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u_int8_t resv[336];
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} __packed;
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struct ciss_evpdchg { /* details pointer */
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u_int16_t pd;
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u_int8_t flag; /* 1 for configured */
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u_int8_t spare;
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u_int8_t bigpd; /* big number of the pd */
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u_int8_t baynum;
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} __packed;
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struct ciss_evpschg { /* details pointer */
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u_int16_t port;
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u_int16_t psid;
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u_int16_t box;
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} __packed;
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struct ciss_evfanchg { /* details pointer */
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u_int16_t port;
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u_int16_t fanid;
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u_int16_t box;
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} __packed;
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struct ciss_evupschg { /* details pointer */
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u_int16_t port;
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u_int16_t upsid;
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} __packed;
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struct ciss_evctrlchg { /* details pointer */
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u_int16_t slot;
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} __packed;
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struct ciss_evtempchg { /* details pointer */
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u_int16_t port;
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u_int16_t sensid;
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u_int16_t box;
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} __packed;
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struct ciss_evldchg { /* details pointer */
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u_int16_t ld;
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u_int8_t prevstat; /* same as ldstat->state */
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u_int8_t newstat; /* same as ldstat->state */
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u_int8_t sparestat;
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} __packed;
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struct ciss_evldrblderr { /* details pointer */
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u_int16_t ld;
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u_int8_t replace;
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u_int8_t errpd;
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u_int8_t bigreplace;
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u_int8_t bigerrpd;
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} __packed;
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struct ciss_evlderr { /* details pointer */
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u_int16_t ld;
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u_int16_t blkno[2]; /* unaligned; if >2tb see big later */
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u_int16_t count;
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u_int8_t ldcmd;
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u_int8_t bus;
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u_int8_t target;
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u_int8_t bigblkno[8]; /* unaligned */
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} __packed;
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struct ciss_evctrlstat { /* details pointer */
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u_int8_t prefctrl;
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u_int8_t currmode;
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u_int8_t redctrl;
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u_int8_t redfail;
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u_int8_t prevctrl;
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u_int8_t prevmode;
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u_int8_t prevred;
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u_int8_t prevfail;
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} __packed;
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struct ciss_cmd {
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u_int8_t resv0; /* 00 */
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u_int8_t sgin; /* 01: #sg in the cmd */
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u_int16_t sglen; /* 02: #sg total */
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u_int32_t id; /* 04: cmd id << 2 and status bits */
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#define CISS_CMD_ERR 0x02
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u_int32_t id_hi; /* 08: not used */
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u_int32_t tgt; /* 0c: tgt:bus:mode or lun:mode */
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#define CISS_CMD_MODE_PERIPH 0x00000000
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#define CISS_CMD_MODE_LD 0x40000000
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#define CISS_CMD_TGT_MASK 0x40ffffff
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#define CISS_CMD_BUS_MASK 0x3f000000
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#define CISS_CMD_BUS_SHIFT 24
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u_int32_t tgt2; /* 10: scsi-3 address bytes */
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u_int8_t cdblen; /* 14: valid length of cdb */
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u_int8_t flags; /* 15 */
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#define CISS_CDB_CMD 0x00
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#define CISS_CDB_MSG 0x01
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#define CISS_CDB_NOTAG 0x00
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#define CISS_CDB_SIMPL 0x20
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#define CISS_CDB_QHEAD 0x28
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#define CISS_CDB_ORDR 0x30
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#define CISS_CDB_AUTO 0x38
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#define CISS_CDB_IN 0x80
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#define CISS_CDB_OUT 0x40
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u_int16_t tmo; /* 16: timeout in seconds */
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#define CISS_MAX_CDB 16
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u_int8_t cdb[CISS_MAX_CDB]; /* 18 */
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|
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u_int64_t err_pa; /* 28: pa(struct ciss_error *) */
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u_int32_t err_len;/* 30 */
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|
|
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struct { /* 34 */
|
|
u_int32_t addr_lo;
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u_int32_t addr_hi;
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u_int32_t len;
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u_int32_t flags;
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#define CISS_SG_EXT 0x0001
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} sgl[1];
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} __packed;
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|
|
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struct ciss_error {
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u_int8_t scsi_stat; /* SCSI_OK etc */
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u_int8_t senselen;
|
|
u_int16_t cmd_stat;
|
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#define CISS_ERR_OK 0
|
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#define CISS_ERR_TGTST 1 /* target status */
|
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#define CISS_ERR_UNRUN 2
|
|
#define CISS_ERR_OVRUN 3
|
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#define CISS_ERR_INVCMD 4
|
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#define CISS_ERR_PROTE 5
|
|
#define CISS_ERR_HWERR 6
|
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#define CISS_ERR_CLOSS 7
|
|
#define CISS_ERR_ABRT 8
|
|
#define CISS_ERR_FABRT 9
|
|
#define CISS_ERR_UABRT 10
|
|
#define CISS_ERR_TMO 11
|
|
#define CISS_ERR_NABRT 12
|
|
u_int32_t resid;
|
|
u_int8_t err_type[4];
|
|
u_int32_t err_info;
|
|
u_int8_t sense[32];
|
|
} __packed;
|
|
|
|
struct ciss_ccb {
|
|
SLIST_ENTRY(ciss_ccb) ccb_link;
|
|
struct ciss_softc *ccb_sc;
|
|
u_int64_t ccb_cmdpa;
|
|
enum {
|
|
CISS_CCB_FREE = 0x01,
|
|
CISS_CCB_READY = 0x02,
|
|
CISS_CCB_ONQ = 0x04,
|
|
CISS_CCB_PREQ = 0x08,
|
|
CISS_CCB_POLL = 0x10,
|
|
CISS_CCB_FAIL = 0x80
|
|
#define CISS_CCB_BITS "\020\01FREE\02READY\03ONQ\04PREQ\05POLL\010FAIL"
|
|
} ccb_state;
|
|
|
|
struct scsi_xfer *ccb_xs;
|
|
size_t ccb_len;
|
|
void *ccb_data;
|
|
bus_dmamap_t ccb_dmamap;
|
|
|
|
struct ciss_error ccb_err;
|
|
struct ciss_cmd ccb_cmd; /* followed by sgl */
|
|
};
|
|
|
|
SLIST_HEAD(ciss_ccb_list, ciss_ccb);
|
|
|