559 lines
16 KiB
C
559 lines
16 KiB
C
/* $OpenBSD: dp8390reg.h,v 1.9 2003/10/21 18:58:49 jmc Exp $ */
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/* $NetBSD: dp8390reg.h,v 1.3 1997/04/29 04:32:08 scottr Exp $ */
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/*
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* National Semiconductor DS8390 NIC register definitions.
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*
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* Copyright (C) 1993, David Greenman. This software may be used, modified,
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* copied, distributed, and sold, in both source and binary form provided that
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* the above copyright and these terms are retained. Under no circumstances is
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* the author responsible for the proper functioning of this software, nor does
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* the author assume any responsibility for damages incurred with its use.
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*/
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/*
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* Page 0 register offsets
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*/
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#define ED_P0_CR 0x00 /* Command Register */
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#define ED_P0_CLDA0 0x01 /* Current Local DMA Addr low (read) */
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#define ED_P0_PSTART 0x01 /* Page Start register (write) */
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#define ED_P0_CLDA1 0x02 /* Current Local DMA Addr high (read) */
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#define ED_P0_PSTOP 0x02 /* Page Stop register (write) */
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#define ED_P0_BNRY 0x03 /* Boundary Pointer */
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#define ED_P0_TSR 0x04 /* Transmit Status Register (read) */
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#define ED_P0_TPSR 0x04 /* Transmit Page Start (write) */
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#define ED_P0_NCR 0x05 /* Number of Collisions Reg (read) */
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#define ED_P0_TBCR0 0x05 /* Transmit Byte count, low (write) */
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#define ED_P0_FIFO 0x06 /* FIFO register (read) */
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#define ED_P0_TBCR1 0x06 /* Transmit Byte count, high (write) */
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#define ED_P0_ISR 0x07 /* Interrupt Status Register */
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#define ED_P0_CRDA0 0x08 /* Current Remote DMA Addr low (read) */
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#define ED_P0_RSAR0 0x08 /* Remote Start Address low (write) */
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#define ED_P0_CRDA1 0x09 /* Current Remote DMA Addr high (read) */
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#define ED_P0_RSAR1 0x09 /* Remote Start Address high (write) */
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#define ED_P0_RBCR0 0x0a /* Remote Byte Count low (write) */
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#define ED_P0_RBCR1 0x0b /* Remote Byte Count high (write) */
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#define ED_P0_RSR 0x0c /* Receive Status (read) */
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#define ED_P0_RCR 0x0c /* Receive Configuration Reg (write) */
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#define ED_P0_CNTR0 0x0d /* frame alignment error counter (read) */
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#define ED_P0_TCR 0x0d /* Transmit Configuration Reg (write) */
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#define ED_P0_CNTR1 0x0e /* CRC error counter (read) */
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#define ED_P0_DCR 0x0e /* Data Configuration Reg (write) */
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#define ED_P0_CNTR2 0x0f /* missed packet counter (read) */
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#define ED_P0_IMR 0x0f /* Interrupt Mask Register (write) */
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/*
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* Page 1 register offsets
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*/
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#define ED_P1_CR 0x00 /* Command Register */
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#define ED_P1_PAR0 0x01 /* Physical Address Register 0 */
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#define ED_P1_PAR1 0x02 /* Physical Address Register 1 */
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#define ED_P1_PAR2 0x03 /* Physical Address Register 2 */
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#define ED_P1_PAR3 0x04 /* Physical Address Register 3 */
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#define ED_P1_PAR4 0x05 /* Physical Address Register 4 */
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#define ED_P1_PAR5 0x06 /* Physical Address Register 5 */
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#define ED_P1_CURR 0x07 /* Current RX ring-buffer page */
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#define ED_P1_MAR0 0x08 /* Multicast Address Register 0 */
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#define ED_P1_MAR1 0x09 /* Multicast Address Register 1 */
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#define ED_P1_MAR2 0x0a /* Multicast Address Register 2 */
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#define ED_P1_MAR3 0x0b /* Multicast Address Register 3 */
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#define ED_P1_MAR4 0x0c /* Multicast Address Register 4 */
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#define ED_P1_MAR5 0x0d /* Multicast Address Register 5 */
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#define ED_P1_MAR6 0x0e /* Multicast Address Register 6 */
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#define ED_P1_MAR7 0x0f /* Multicast Address Register 7 */
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/*
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* Page 2 register offsets
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*/
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#define ED_P2_CR 0x00 /* Command Register */
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#define ED_P2_PSTART 0x01 /* Page Start (read) */
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#define ED_P2_CLDA0 0x01 /* Current Local DMA Addr 0 (write) */
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#define ED_P2_PSTOP 0x02 /* Page Stop (read) */
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#define ED_P2_CLDA1 0x02 /* Current Local DMA Addr 1 (write) */
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#define ED_P2_RNPP 0x03 /* Remote Next Packet Pointer */
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#define ED_P2_TPSR 0x04 /* Transmit Page Start (read) */
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#define ED_P2_LNPP 0x05 /* Local Next Packet Pointer */
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#define ED_P2_ACU 0x06 /* Address Counter Upper */
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#define ED_P2_ACL 0x07 /* Address Counter Lower */
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#define ED_P2_RCR 0x0c /* Receive Configuration Register (read) */
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#define ED_P2_TCR 0x0d /* Transmit Configuration Register (read) */
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#define ED_P2_DCR 0x0e /* Data Configuration Register (read) */
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#define ED_P2_IMR 0x0f /* Interrupt Mask Register (read) */
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/*
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* Command Register (CR) definitions
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*/
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/*
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* STP: SToP. Software reset command. Takes the controller offline. No
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* packets will be received or transmitted. Any reception or transmission in
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* progress will continue to completion before entering reset state. To exit
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* this state, the STP bit must reset and the STA bit must be set. The
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* software reset has executed only when indicated by the RST bit in the ISR
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* being set.
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*/
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#define ED_CR_STP 0x01
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/*
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* STA: STArt. This bit is used to activate the NIC after either power-up, or
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* when the NIC has been put in reset mode by software command or error.
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*/
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#define ED_CR_STA 0x02
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/*
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* TXP: Transmit Packet. This bit must be set to indicate transmission of a
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* packet. TXP is internally reset either after the transmission is completed
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* or aborted. This bit should be set only after the Transmit Byte Count and
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* Transmit Page Start register have been programmed.
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*/
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#define ED_CR_TXP 0x04
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/*
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* RD0, RD1, RD2: Remote DMA Command. These three bits control the operation
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* of the remote DMA channel. RD2 can be set to abort any remote DMA command
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* in progress. The Remote Byte Count registers should be cleared when a
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* remote DMA has been aborted. The Remote Start Addresses are not restored
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* to the starting address if the remote DMA is aborted.
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*
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* RD2 RD1 RD0 function
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* 0 0 0 not allowed
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* 0 0 1 remote read
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* 0 1 0 remote write
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* 0 1 1 send packet
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* 1 X X abort
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*/
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#define ED_CR_RD0 0x08
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#define ED_CR_RD1 0x10
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#define ED_CR_RD2 0x20
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/*
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* PS0, PS1: Page Select. The two bits select which register set or 'page' to
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* access.
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*
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* PS1 PS0 page
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* 0 0 0
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* 0 1 1
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* 1 0 2
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* 1 1 3 (only on chips which have extensions to the dp8390)
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*/
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#define ED_CR_PS0 0x40
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#define ED_CR_PS1 0x80
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/* bit encoded aliases */
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#define ED_CR_PAGE_0 0x00 /* (for consistency) */
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#define ED_CR_PAGE_1 (ED_CR_PS0)
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#define ED_CR_PAGE_2 (ED_CR_PS1)
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#define ED_CR_PAGE_3 (ED_CR_PS1|ED_CR_PS0)
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/*
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* Interrupt Status Register (ISR) definitions
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*/
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/*
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* PRX: Packet Received. Indicates packet received with no errors.
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*/
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#define ED_ISR_PRX 0x01
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/*
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* PTX: Packet Transmitted. Indicates packet transmitted with no errors.
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*/
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#define ED_ISR_PTX 0x02
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/*
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* RXE: Receive Error. Indicates that a packet was received with one or more
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* the following errors: CRC error, frame alignment error, FIFO overrun,
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* missed packet.
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*/
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#define ED_ISR_RXE 0x04
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/*
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* TXE: Transmission Error. Indicates that an attempt to transmit a packet
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* resulted in one or more of the following errors: excessive collisions, FIFO
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* underrun.
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*/
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#define ED_ISR_TXE 0x08
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/*
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* OVW: OverWrite. Indicates a receive ring-buffer overrun. Incoming network
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* would exceed (has exceeded?) the boundary pointer, resulting in data that
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* was previously received and not yet read from the buffer to be overwritten.
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*/
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#define ED_ISR_OVW 0x10
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/*
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* CNT: Counter Overflow. Set when the MSB of one or more of the Network Tally
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* Counters has been set.
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*/
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#define ED_ISR_CNT 0x20
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/*
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* RDC: Remote Data Complete. Indicates that a Remote DMA operation has
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* completed.
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*/
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#define ED_ISR_RDC 0x40
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/*
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* RST: Reset status. Set when the NIC enters the reset state and cleared when
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* a Start Command is issued to the CR. This bit is also set when a receive
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* ring-buffer overrun (OverWrite) occurs and is cleared when one or more
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* packets have been removed from the ring. This is a read-only bit.
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*/
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#define ED_ISR_RST 0x80
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/*
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* Interrupt Mask Register (IMR) definitions
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*/
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/*
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* PRXE: Packet Received interrupt Enable. If set, a received packet will
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* cause an interrupt.
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*/
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#define ED_IMR_PRXE 0x01
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/*
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* PTXE: Packet Transmit interrupt Enable. If set, an interrupt is generated
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* when a packet transmission completes.
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*/
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#define ED_IMR_PTXE 0x02
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/*
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* RXEE: Receive Error interrupt Enable. If set, an interrupt will occur
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* whenever a packet is received with an error.
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*/
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#define ED_IMR_RXEE 0x04
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/*
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* TXEE: Transmit Error interrupt Enable. If set, an interrupt will occur
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* whenever a transmission results in an error.
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*/
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#define ED_IMR_TXEE 0x08
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/*
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* OVWE: OverWrite error interrupt Enable. If set, an interrupt is generated
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* whenever the receive ring-buffer is overrun. i.e. when the boundary pointer
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* is exceeded.
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*/
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#define ED_IMR_OVWE 0x10
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/*
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* CNTE: Counter overflow interrupt Enable. If set, an interrupt is generated
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* whenever the MSB of one or more of the Network Statistics counters has been
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* set.
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*/
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#define ED_IMR_CNTE 0x20
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/*
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* RDCE: Remote DMA Complete interrupt Enable. If set, an interrupt is
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* generated when a remote DMA transfer has completed.
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*/
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#define ED_IMR_RDCE 0x40
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/*
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* Bit 7 is unused/reserved.
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*/
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/*
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* Data Configuration Register (DCR) definitions
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*/
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/*
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* WTS: Word Transfer Select. WTS establishes byte or word transfers for both
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* remote and local DMA transfers
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*/
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#define ED_DCR_WTS 0x01
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/*
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* BOS: Byte Order Select. BOS sets the byte order for the host. Should be 0
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* for 80x86, and 1 for 68000 series processors
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*/
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#define ED_DCR_BOS 0x02
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/*
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* LAS: Long Address Select. When LAS is 1, the contents of the remote DMA
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* registers RSAR0 and RSAR1 are used to provide A16-A31.
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*/
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#define ED_DCR_LAS 0x04
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/*
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* LS: Loopback Select. When 0, loopback mode is selected. Bits D1 and D2 of
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* the TCR must also be programmed for loopback operation. When 1, normal
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* operation is selected.
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*/
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#define ED_DCR_LS 0x08
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/*
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* AR: Auto-initialize Remote. When 0, data must be removed from ring-buffer
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* under program control. When 1, remote DMA is automatically initiated and
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* the boundary pointer is automatically updated.
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*/
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#define ED_DCR_AR 0x10
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/*
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* FT0, FT1: Fifo Threshold select.
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*
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* FT1 FT0 Word-width Byte-width
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* 0 0 1 word 2 bytes
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* 0 1 2 words 4 bytes
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* 1 0 4 words 8 bytes
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* 1 1 8 words 12 bytes
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*
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* During transmission, the FIFO threshold indicates the number of bytes or
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* words that the FIFO has filled from the local DMA before BREQ is asserted.
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* The transmission threshold is 16 bytes minus the receiver threshold.
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*/
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#define ED_DCR_FT0 0x20
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#define ED_DCR_FT1 0x40
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/*
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* bit 7 (0x80) is unused/reserved
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*/
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/*
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* Transmit Configuration Register (TCR) definitions
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*/
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/*
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* CRC: Inhibit CRC. If 0, CRC will be appended by the transmitter, if 0, CRC
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* is not appended by the transmitter.
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*/
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#define ED_TCR_CRC 0x01
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/*
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* LB0, LB1: Loopback control. These two bits set the type of loopback that is
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* to be performed.
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*
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* LB1 LB0 mode
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* 0 0 0 - normal operation (DCR_LS = 0)
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* 0 1 1 - internal loopback (DCR_LS = 0)
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* 1 0 2 - external loopback (DCR_LS = 1)
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* 1 1 3 - external loopback (DCR_LS = 0)
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*/
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#define ED_TCR_LB0 0x02
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#define ED_TCR_LB1 0x04
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/*
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* ATD: Auto Transmit Disable. Clear for normal operation. When set, allows
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* another station to disable the NIC's transmitter by transmitting to a
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* multicast address hashing to bit 62. Reception of a multicast address
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* hashing to bit 63 enables the transmitter.
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*/
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#define ED_TCR_ATD 0x08
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/*
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* OFST: Collision Offset enable. This bit when set modifies the backoff
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* algorithm to allow prioritization of nodes.
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*/
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#define ED_TCR_OFST 0x10
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/*
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* bits 5, 6, and 7 are unused/reserved
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*/
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/*
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* Transmit Status Register (TSR) definitions
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*/
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/*
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* PTX: Packet Transmitted. Indicates successful transmission of packet.
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*/
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#define ED_TSR_PTX 0x01
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/*
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* bit 1 (0x02) is unused/reserved
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*/
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/*
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* COL: Transmit Collided. Indicates that the transmission collided at least
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* once with another station on the network.
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*/
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#define ED_TSR_COL 0x04
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/*
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* ABT: Transmit aborted. Indicates that the transmission was aborted due to
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* excessive collisions.
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*/
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#define ED_TSR_ABT 0x08
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/*
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* CRS: Carrier Sense Lost. Indicates that carrier was lost during the
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* transmission of the packet. (Transmission is not aborted because of a loss
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* of carrier).
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*/
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#define ED_TSR_CRS 0x10
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/*
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* FU: FIFO Underrun. Indicates that the NIC wasn't able to access bus/
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* transmission memory before the FIFO emptied. Transmission of the packet was
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* aborted.
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*/
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#define ED_TSR_FU 0x20
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/*
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* CDH: CD Heartbeat. Indicates that the collision detection circuitry isn't
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* working correctly during a collision heartbeat test.
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*/
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#define ED_TSR_CDH 0x40
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/*
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* OWC: Out of Window Collision: Indicates that a collision occurred after a
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* slot time (51.2us). The transmission is rescheduled just as in normal
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* collisions.
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*/
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#define ED_TSR_OWC 0x80
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/*
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* Receiver Configuration Register (RCR) definitions
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*/
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/*
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* SEP: Save Errored Packets. If 0, error packets are discarded. If set to 1,
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* packets with CRC and frame errors are not discarded.
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*/
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#define ED_RCR_SEP 0x01
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/*
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* AR: Accept Runt packet. If 0, packet with less than 64 byte are discarded.
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* If set to 1, packets with less than 64 byte are not discarded.
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*/
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#define ED_RCR_AR 0x02
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/*
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* AB: Accept Broadcast. If set, packets sent to the broadcast address will be
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* accepted.
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*/
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#define ED_RCR_AB 0x04
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/*
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* AM: Accept Multicast. If set, packets sent to a multicast address are
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* checked for a match in the hashing array. If clear, multicast packets are
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* ignored.
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*/
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#define ED_RCR_AM 0x08
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/*
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* PRO: Promiscuous Physical. If set, all packets with a physical addresses
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* are accepted. If clear, a physical destination address must match this
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* station's address. Note: for full promiscuous mode, RCR_AB and RCR_AM must
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* also be set. In addition, the multicast hashing array must be set to all
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* 1's so that all multicast addresses are accepted.
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*/
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#define ED_RCR_PRO 0x10
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/*
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* MON: Monitor Mode. If set, packets will be checked for good CRC and
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* framing, but are not stored in the ring-buffer. If clear, packets are
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* stored (normal operation).
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*/
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#define ED_RCR_MON 0x20
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/*
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* INTT: Interrupt Trigger Mode. Must be set if AX88190.
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*/
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#define ED_RCR_INTT 0x40
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/*
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* Bit 7 is unused/reserved.
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*/
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/*
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* Receiver Status Register (RSR) definitions
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*/
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/*
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* PRX: Packet Received without error.
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*/
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#define ED_RSR_PRX 0x01
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/*
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* CRC: CRC error. Indicates that a packet has a CRC error. Also set for
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* frame alignment errors.
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*/
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#define ED_RSR_CRC 0x02
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/*
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* FAE: Frame Alignment Error. Indicates that the incoming packet did not end
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* on a byte boundary and the CRC did not match at the last byte boundary.
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*/
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#define ED_RSR_FAE 0x04
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/*
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* FO: FIFO Overrun. Indicates that the FIFO was not serviced (during local
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* DMA) causing it to overrun. Reception of the packet is aborted.
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*/
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#define ED_RSR_FO 0x08
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/*
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* MPA: Missed Packet. Indicates that the received packet couldn't be stored
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* in the ring-buffer because of insufficient buffer space (exceeding the
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* boundary pointer), or because the transfer to the ring-buffer was inhibited
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* by RCR_MON - monitor mode.
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*/
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#define ED_RSR_MPA 0x10
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/*
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* PHY: Physical address. If 0, the packet received was sent to a physical
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* address. If 1, the packet was accepted because of a multicast/broadcast
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* address match.
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*/
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#define ED_RSR_PHY 0x20
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/*
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* DIS: Receiver Disabled. Set to indicate that the receiver has entered
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* monitor mode. Cleared when the receiver exits monitor mode.
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*/
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#define ED_RSR_DIS 0x40
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/*
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* DFR: Deferring. Set to indicate a 'jabber' condition. The CRS and COL
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* inputs are active, and the transceiver has set the CD line as a result of
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* the jabber.
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*/
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#define ED_RSR_DFR 0x80
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/*
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* receive ring descriptor
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*
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* The National Semiconductor DS8390 Network interface controller uses the
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* following receive ring headers. The way this works is that the memory on
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* the interface card is chopped up into 256 bytes blocks. A contiguous
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* portion of those blocks are marked for receive packets by setting start and
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* end block #'s in the NIC. For each packet that is put into the receive
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* ring, one of these headers (4 bytes each) is tacked onto the front. The
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* first byte is a copy of the receiver status register at the time the packet
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* was received.
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*/
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struct dp8390_ring {
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u_int8_t rsr; /* receiver status */
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u_int8_t next_packet; /* pointer to next packet */
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u_int16_t count; /* bytes in packet (length + 4) */
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};
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/* Some drivers prefer to use byte-constants to get at this structure. */
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#define ED_RING_RSR 0 /* receiver status */
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#define ED_RING_NEXT_PACKET 1 /* pointer to next packet */
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#define ED_RING_COUNT 2 /* bytes in packet (length + 4) */
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#define ED_RING_HDRSZ 4 /* Header size */
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/*
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* Common constants
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|
*/
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#define ED_PAGE_SIZE 256 /* Size of RAM pages in bytes */
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#define ED_PAGE_MASK 255
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#define ED_PAGE_SHIFT 8
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#define ED_TXBUF_SIZE 6 /* Size of TX buffer in pages */
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