159 lines
5.0 KiB
C
159 lines
5.0 KiB
C
/* $OpenBSD: lm78var.h,v 1.20 2022/04/08 15:02:28 naddy Exp $ */
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/*
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* Copyright (c) 2005, 2006 Mark Kettenis
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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/*
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* National Semiconductor LM78/79/81 registers
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*/
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#define LM_POST_RAM 0x00 /* POST RAM occupies 0x00 -- 0x1f */
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#define LM_VALUE_RAM 0x20 /* Value RAM occupies 0x20 -- 0x3f */
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#define LM_FAN1 0x28 /* FAN1 reading */
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#define LM_FAN2 0x29 /* FAN2 reading */
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#define LM_FAN3 0x2a /* FAN3 reading */
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#define LM_CONFIG 0x40 /* Configuration */
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#define LM_ISR1 0x41 /* Interrupt Status 1 */
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#define LM_ISR2 0x42 /* Interrupt Status 2 */
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#define LM_SMI1 0x43 /* SMI# Mask 1 */
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#define LM_SMI2 0x44 /* SMI# Mask 2 */
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#define LM_NMI1 0x45 /* NMI Mask 1 */
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#define LM_NMI2 0x46 /* NMI Mask 2 */
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#define LM_VIDFAN 0x47 /* VID/Fan Divisor */
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#define LM_SBUSADDR 0x48 /* Serial Bus Address */
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#define LM_CHIPID 0x49 /* Chip Reset/ID */
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/* Chip IDs */
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#define LM_CHIPID_LM78 0x00
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#define LM_CHIPID_LM78J 0x40
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#define LM_CHIPID_LM79 0xC0
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#define LM_CHIPID_LM81 0x80
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#define LM_CHIPID_MASK 0xfe
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/*
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* Winbond registers
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*
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* Several models exists. The W83781D is mostly compatible with the
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* LM78, but has two extra temperatures. Later models add extra
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* voltage sensors, fans and bigger fan divisors to accommodate slow
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* running fans. To accommodate the extra sensors some models have
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* different memory banks.
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*/
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#define WB_T23ADDR 0x4a /* Temperature 2 and 3 Serial Bus Address */
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#define WB_PIN 0x4b /* Pin Control */
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#define WB_BANKSEL 0x4e /* Bank Select */
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#define WB_VENDID 0x4f /* Vendor ID */
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/* Bank 0 regs */
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#define WB_BANK0_CHIPID 0x58 /* Chip ID */
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#define WB_BANK0_FAN45 0x5c /* Fan 4/5 Divisor Control (W83791D only) */
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#define WB_BANK0_VBAT 0x5d /* VBAT Monitor Control */
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#define WB_BANK0_FAN4 0xba /* Fan 4 reading (W83791D only) */
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#define WB_BANK0_FAN5 0xbb /* Fan 5 reading (W83791D only) */
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#define WB_BANK0_CONFIG 0x18 /* VRM & OVT Config (W83627THF/W83637HF) */
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/* Bank 1 registers */
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#define WB_BANK1_T2H 0x50 /* Temperature 2 High Byte */
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#define WB_BANK1_T2L 0x51 /* Temperature 2 Low Byte */
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/* Bank 2 registers */
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#define WB_BANK2_T3H 0x50 /* Temperature 3 High Byte */
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#define WB_BANK2_T3L 0x51 /* Temperature 3 Low Byte */
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/* Bank 4 registers (W83782D/W83627HF and later models only) */
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#define WB_BANK4_T1OFF 0x54 /* Temperature 1 Offset */
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#define WB_BANK4_T2OFF 0x55 /* Temperature 2 Offset */
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#define WB_BANK4_T3OFF 0x56 /* Temperature 3 Offset */
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/* Bank 5 registers (W83782D/W83627HF and later models only) */
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#define WB_BANK5_5VSB 0x50 /* 5VSB reading */
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#define WB_BANK5_VBAT 0x51 /* VBAT reading */
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/* Bank selection */
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#define WB_BANKSEL_B0 0x00 /* Bank 0 */
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#define WB_BANKSEL_B1 0x01 /* Bank 1 */
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#define WB_BANKSEL_B2 0x02 /* Bank 2 */
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#define WB_BANKSEL_B3 0x03 /* Bank 3 */
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#define WB_BANKSEL_B4 0x04 /* Bank 4 */
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#define WB_BANKSEL_B5 0x05 /* Bank 5 */
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#define WB_BANKSEL_HBAC 0x80 /* Register 0x4f High Byte Access */
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/* Vendor IDs */
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#define WB_VENDID_WINBOND 0x5ca3 /* Winbond */
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#define WB_VENDID_ASUS 0x12c3 /* ASUS */
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/* Chip IDs */
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#define WB_CHIPID_W83781D 0x10
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#define WB_CHIPID_W83781D_2 0x11
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#define WB_CHIPID_W83627HF 0x21
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#define WB_CHIPID_AS99127F 0x31 /* Asus W83781D clone */
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#define WB_CHIPID_W83782D 0x30
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#define WB_CHIPID_W83783S 0x40
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#define WB_CHIPID_W83697HF 0x60
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#define WB_CHIPID_W83791D 0x71
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#define WB_CHIPID_W83791SD 0x72
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#define WB_CHIPID_W83792D 0x7a
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#define WB_CHIPID_W83637HF 0x80
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#define WB_CHIPID_W83627EHF_A 0x88 /* early version, only for ASUS MBs */
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#define WB_CHIPID_W83627THF 0x90
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#define WB_CHIPID_W83627EHF 0xa1
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#define WB_CHIPID_W83627DHG 0xc1 /* also used in WBSIO_ID_NCT6776F */
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/* Config bits */
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#define WB_CONFIG_VMR9 0x01
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/* Reference voltage (mV) */
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#define WB_VREF 3600
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#define WB_W83627EHF_VREF 2048
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#define WB_MAX_SENSORS 36
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struct lm_softc;
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struct lm_sensor {
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char *desc;
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enum sensor_type type;
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u_int8_t bank;
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u_int8_t reg;
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void (*refresh)(struct lm_softc *, int);
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int rfact;
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};
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struct lm_softc {
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struct device sc_dev;
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struct ksensor sensors[WB_MAX_SENSORS];
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struct ksensordev sensordev;
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struct sensor_task *sensortask;
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const struct lm_sensor *lm_sensors;
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u_int numsensors;
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void (*refresh_sensor_data) (struct lm_softc *);
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u_int8_t (*lm_readreg)(struct lm_softc *, int);
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void (*lm_writereg)(struct lm_softc *, int, int);
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u_int8_t sbusaddr;
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u_int8_t chipid;
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u_int8_t sioid;
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u_int8_t vrm9;
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};
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void lm_attach(struct lm_softc *);
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