304 lines
9.3 KiB
C
304 lines
9.3 KiB
C
/* $OpenBSD: p9000.h,v 1.4 2007/05/22 04:14:03 jsg Exp $ */
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/*
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* Copyright (c) 2003, Miodrag Vallat.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Weitek Power9000 and Power9100 definitions.
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*
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* Although the datasheet is not available anymore, a good source of
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* documentation is several code examples in XFree86 3.x (vga256/p9x00) and the
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* {Net,Open}BSD source trees.
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*/
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/*
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* Frame buffer control registers
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*
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* Offsets below are relative to the following locations:
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* P9000 at 0x00100000, P9100 at 0x000000
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*/
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/*
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* System control registers
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*/
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/* System configuration register */
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#define P9000_SYSTEM_CONFIG 0x00000004
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#define SCR_PIXEL_MASK 0x1c000000
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#define SCR_PIXEL_8BPP 0x08000000
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#define SCR_PIXEL_16BPP 0x0c000000
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#define SCR_PIXEL_24BPP 0x1c000000
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#define SCR_PIXEL_32BPP 0x14000000
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#define SCR_SWAP_WORDS 0x00002000
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#define SCR_SWAP_BYTES 0x00001000
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#define SCR_SWAP_BITS 0x00000800
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#define SCR_READ_BUFFER_MASK 0x00000400
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#define SCR_WRITE_BUFFER_MASK 0x00000200
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#define SCR_ID_MASK 0x00000007
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#define SCR_SC(sc0, sc1, sc2, sc3) \
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(((sc0) << 14) | ((sc1) << 17) | ((sc2) << 20) | ((sc3) << 29))
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/* Interrupt status register */
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#define P9000_INTERRUPT 0x00000008
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/* Interrupt enable register */
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#define P9000_INTERRUPT_ENABLE 0x0000000c
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#define IER_MASTER_ENABLE 0x00000080
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#define IER_MASTER_INTERRUPT 0x00000040
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#define IER_VBLANK_ENABLE 0x00000020
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#define IER_VBLANK_INTERRUPT 0x00000010
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#define IER_PICK_ENABLE 0x00000008
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#define IER_PICK_INTERRUPT 0x00000004
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#define IER_IDLE_ENABLE 0x00000002
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#define IER_IDLE_INTERRUPT 0x00000001
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/* Alternate read bank register (bits 16-22) */
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#define P9000_ALTBANK_READ 0x00000010
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/* Alternate write bank register (bits 16-22) */
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#define P9000_ALTBANK_WRITE 0x00000014
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/*
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* Video control registers
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*/
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/* Horizontal counter */
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#define P9000_HCR 0x00000104
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/* Horizontal total */
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#define P9000_HTR 0x00000108
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/* Horizontal sync rising edge */
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#define P9000_HSRE 0x0000010c
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/* Horizontal blank rising edge */
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#define P9000_HBRE 0x00000110
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/* Horizontal blank falling edge */
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#define P9000_HBFE 0x00000114
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/* Horizontal counter preload */
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#define P9000_HCP 0x00000118
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/* Vertical counter */
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#define P9000_VCR 0x0000011c
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/* Vertical length */
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#define P9000_VL 0x00000120
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/* Vertical sync rising edge */
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#define P9000_VSRE 0x00000124
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/* Vertical blank rising edge */
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#define P9000_VBRE 0x00000128
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/* Vertical blank falling edge */
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#define P9000_VBFE 0x0000012c
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/* Vertical counter preload */
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#define P9000_VCP 0x00000130
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/* Screen repaint address */
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#define P9000_SRA 0x00000134
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/* Screen repaint timing control #1 */
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#define P9000_SRTC1 0x00000138
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#define SRTC1_VSYNC_INTERNAL 0x00000100
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#define SRTC1_HSYNC_INTERNAL 0x00000080
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#define SRTC1_VIDEN 0x00000020
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#define SRTC1_RESTRICTED 0x00000010
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#define SRTC1_BUFFER1 0x00000008
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/* QSF counter. Film at 11 */
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#define P9000_QSF 0x0000013c
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/* Screen repaint timing control #2 */
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#define P9000_SRTC2 0x00000140
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/*
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* VRAM control registers
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*/
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/* Memory configuration */
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#define P9000_MCR 0x00000184
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/* Refresh period */
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#define P9000_REFRESH_PERIOD 0x00000188
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/* Refresh count */
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#define P9000_REFRESH_COUNT 0x0000018c
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/* RAS low maximum */
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#define P9000_RASLOW_MAXIMUM 0x00000190
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/* RAS low current */
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#define P9000_RASLOW_CURRENT 0x00000194
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/* RAMDAC free FIFO (P9100 only, bits 12-15) and power-up configuration */
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#define P9000_POWERUP_CONFIG 0x00000198
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#define P9100_FREE_FIFO 0x00000198
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/*
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* RAMDAC registers (P9100 only)
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*/
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#define P9100_RAMDAC_REGISTER(index) (0x00000200 + ((index) << 2))
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/*
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* Accelerated features
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*
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* Offsets below are relative to the following locations:
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* P9000 at 0x00180000, P9100 at 0x002000
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*/
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/*
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* Parameter engine
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*/
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/* Status register */
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#define P9000_PE_STATUS 0x00000000
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#define STATUS_QUAD_BUSY 0x80000000
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#define STATUS_BLIT_BUSY 0x40000000
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#define STATUS_PICK_DETECTED 0x00000080
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#define STATUS_PIXEL_ERROR 0x00000040
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#define STATUS_BLIT_ERROR 0x00000020
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#define STATUS_QUAD_ERROR 0x00000010
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#define STATUS_QUAD_CONCAVE 0x00000008
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#define STATUS_QUAD_OUTSIDE 0x00000004
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#define STATUS_QUAD_INSIDE 0x00000002
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#define STATUS_QUAD_STRADDLE 0x00000001
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/* Engine arguments / operation triggers */
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#define P9000_PE_BLIT 0x00000004
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#define P9000_PE_QUAD 0x00000008
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#define P9000_PE_PIXEL8 0x0000000c
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#define P9000_PE_NEXTPIXELS 0x00000014
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#define P9000_PE_PIXEL1(index) (0x00000080 + ((index) << 2))
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/* Control and conditions registers */
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/* Out of range */
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#define P9000_PE_OOR 0x00000184
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/* Index register (0-3, for meta coordinates) */
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#define P9000_PE_INDEX 0x0000018c
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/* Window offset (16x16)*/
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#define P9000_PE_WINOFFSET 0x00000190
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/* Clipping window */
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#define P9000_PE_WINMIN 0x00000194
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#define P9000_PE_WINMAX 0x00000198
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/* X Clip register */
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#define P9000_X_CLIPPING 0x000001a0
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/* Y Clip register */
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#define P9000_Y_CLIPPING 0x000001a4
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/* X Edge Less Than register */
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#define P9000_X_EDGE_LESS 0x000001a8
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/* X Edge Greater Than register */
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#define P9000_X_EDGE_GREATER 0x000001ac
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/* Y Edge Less Than register */
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#define P9000_Y_EDGE_LESS 0x000001b0
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/* Y Edge Greater Than register */
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#define P9000_Y_EDGE_GREATER 0x000001b4
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/*
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* Drawing engine
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*/
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/* Colors - 8 bit for P9000, 32 bit for P9100 */
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#define P9000_DE_FG_COLOR 0x00000200
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#define P9000_DE_BG_COLOR 0x00000204
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#define P9100_DE_COLOR0 0x00000200
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#define P9100_DE_COLOR1 0x00000204
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#define P9100_DE_COLOR2 0x00000238
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#define P9100_DE_COLOR3 0x0000023c
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/* How to encode a colors in 8 and 16 bit mode, for the P9100 */
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#define P9100_COLOR8(c) ((c) | ((c) << 8) | ((c) << 16) | ((c) << 24))
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#define P9100_COLOR16(c) ((c) | ((c) << 16))
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/* Plane mask (8 bits on P9000, 32 bits on P9100) */
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#define P9000_DE_PLANEMASK 0x00000208
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/* Drawing mode */
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#define P9000_DE_DRAWMODE 0x0000020c
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#define DM_PICK_CONTROL 0x00000008
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#define DM_PICK_ENABLE 0x00000004
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#define DM_BUFFER_CONTROL 0x00000002
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#define DM_BUFFER_ENABLE0 0x00000000
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#define DM_BUFFER_ENABLE1 0x00000001
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/* Pattern Origin (4 bit x 4 bit offset) */
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#define P9000_DE_PATTERN_ORIGIN_X 0x00000210
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#define P9000_DE_PATTERN_ORIGIN_Y 0x00000214
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/* Raster operation */
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#define P9000_DE_RASTER 0x00000218
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#define P9100_RASTER_NO_SOLID 0x00002000
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#define P9100_RASTER_PATTERN_4COLOR 0x00004000
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#define P9100_RASTER_PIXEL1_TRANSPARENT 0x00008000
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#define P9000_RASTER_QUAD_OVERSIZE 0x00010000
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#define P9000_RASTER_QUAD_PATTERN 0x00020000
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/* Raster minterms */
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#define P9000_RASTER_SRC 0xcccc
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#define P9000_RASTER_DST 0xaaaa
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#define P9000_RASTER_PATTERN 0xff00
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#define P9000_RASTER_MASK 0xffff
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#define P9100_RASTER_SRC 0x00cc
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#define P9100_RASTER_DST 0x00aa
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#define P9100_RASTER_PATTERN 0x00f0
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#define P9100_RASTER_MASK 0x00ff
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/* Pixel8 excess storage */
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#define P9000_DE_PIXEL8 0x0000021c
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/* Clipping window - same as in PE */
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#define P9000_DE_WINMIN 0x00000220
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#define P9000_DE_WINMAX 0x00000224
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/* Quad pattern - up to 4 items on P9000, 8 on P9100 */
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#define P9000_DE_PATTERN(index) (0x00000280 + ((index) << 2))
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/* User pattern - up to 4 items */
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#define P9000_DE_USER(index) (0x00000290 + ((index) << 2))
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/* Byte clipping window */
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#define P9100_DE_B_WINMIN 0x000002a0
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#define P9100_DE_B_WINMAX 0x000002a4
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/*
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* Coordinates
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*/
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/* 32 bit X value */
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#define P9000_COORD_X 0x00000008
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/* 32 bit Y value */
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#define P9000_COORD_Y 0x00000010
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/* 16 bit X, 16 bit Y values packed */
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#define P9000_COORD_XY 0x00000018
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/* Absolute (screen) coordinates */
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#define P9000_COORD_ABS 0x00000000
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/* Relative (in-window) coordinates */
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#define P9000_COORD_REL 0x00000020
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/* How to pack a x16y16 value - note that they are in fact 12 bit values */
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#define P9000_COORDS(x,y) ((((x) & 0x0fff) << 16) | ((y) & 0x0fff))
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/* Device coordinates - 4 edges */
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#define P9000_DC_COORD(index) (0x00001000 + ((index) * 0x40))
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/* Load coordinates */
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#define P9000_LC_POINT 0x00001200
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#define P9000_LC_LINE 0x00001240
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#define P9000_LC_TRI 0x00001280
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#define P9000_LC_QUAD 0x000012c0
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#define P9000_LC_RECT 0x00001300
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