231 lines
8.1 KiB
C
231 lines
8.1 KiB
C
/* $OpenBSD: uhareg.h,v 1.5 2010/06/30 19:06:16 mk Exp $ */
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/* $NetBSD: uhareg.h,v 1.2 1996/09/01 00:54:41 mycroft Exp $ */
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/*
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* Copyright (c) 1994, 1996 Charles M. Hannum. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Charles M. Hannum.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Ported for use with the UltraStor 14f by Gary Close (gclose@wvnvms.wvnet.edu)
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* Slight fixes to timeouts to run with the 34F
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* Thanks to Julian Elischer for advice and help with this port.
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*
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* Originally written by Julian Elischer (julian@tfs.com)
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* for TRW Financial Systems for use under the MACH(2.5) operating system.
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*
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* TRW Financial Systems, in accordance with their agreement with Carnegie
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* Mellon University, makes this software available to CMU to distribute
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* or use in any manner that they see fit as long as this message is kept with
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* the software. For this reason TFS also grants any other persons or
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* organisations permission to use or modify this software.
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*
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* TFS supplies this software to be publicly redistributed
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* on the understanding that TFS is not responsible for the correct
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* functioning of this software in any circumstances.
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*
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* commenced: Sun Sep 27 18:14:01 PDT 1992
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* slight mod to make work with 34F as well: Wed Jun 2 18:05:48 WST 1993
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*/
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typedef u_long physaddr;
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typedef u_long physlen;
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/************************** board definitions *******************************/
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/*
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* I/O Port Interface
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*/
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#define U14_LMASK 0x0000 /* local doorbell mask reg */
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#define U14_LINT 0x0001 /* local doorbell int/stat reg */
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#define U14_SMASK 0x0002 /* system doorbell mask reg */
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#define U14_SINT 0x0003 /* system doorbell int/stat reg */
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#define U14_ID 0x0004 /* product id reg (2 ports) */
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#define U14_CONFIG 0x0006 /* config reg (2 ports) */
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#define U14_OGMPTR 0x0008 /* outgoing mail ptr (4 ports) */
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#define U14_ICMPTR 0x000c /* incoming mail ptr (4 ports) */
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#define U24_CONFIG 0x0005 /* config reg (3 ports) */
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#define U24_LMASK 0x000c /* local doorbell mask reg */
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#define U24_LINT 0x000d /* local doorbell int/stat reg */
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#define U24_SMASK 0x000e /* system doorbell mask reg */
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#define U24_SINT 0x000f /* system doorbell int/stat reg */
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#define U24_OGMCMD 0x0016 /* outgoing commands */
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#define U24_OGMPTR 0x0017 /* outgoing mail ptr (4 ports) */
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#define U24_ICMCMD 0x001b /* incoming commands */
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#define U24_ICMPTR 0x001c /* incoming mail ptr (4 ports) */
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/*
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* UHA_LMASK bits (read only)
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*/
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#define UHA_LDIE 0x80 /* local doorbell int enabled */
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#define UHA_SRSTE 0x40 /* soft reset enabled */
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#define UHA_ABORTEN 0x10 /* abort MSCP enabled */
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#define UHA_OGMINTEN 0x01 /* outgoing mail interrupt enabled */
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/*
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* UHA_LINT bits (read only)
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*/
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#define U14_LDIP 0x80 /* local doorbell int pending */
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#define U24_LDIP 0x02 /* local doorbell int pending */
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/*
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* UHA_LINT bits (write only)
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*/
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#define U14_OGMFULL 0x01 /* outgoing mailbox is full */
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#define U14_ABORT 0x10 /* abort MSCP */
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#define U24_OGMFULL 0x02 /* outgoing mailbox is full */
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#define UHA_SBRST 0x40 /* scsi bus reset */
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#define UHA_ADRST 0x80 /* adapter soft reset */
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#define UHA_ASRST 0xc0 /* adapter and scsi reset */
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/*
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* UHA_SMASK bits (read/write)
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*/
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#define UHA_ENSINT 0x80 /* enable system doorbell interrupt */
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#define UHA_EN_ABORT_COMPLETE 0x10 /* enable abort MSCP complete int */
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#define UHA_ENICM 0x01 /* enable ICM interrupt */
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/*
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* UHA_SINT bits (read)
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*/
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#define U14_SDIP 0x80 /* system doorbell int pending */
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#define U24_SDIP 0x02 /* system doorbell int pending */
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#define UHA_ABORT_SUCC 0x10 /* abort MSCP successful */
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#define UHA_ABORT_FAIL 0x18 /* abort MSCP failed */
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/*
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* UHA_SINT bits (write)
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*/
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#define U14_ICM_ACK 0x01 /* acknowledge ICM and clear */
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#define U24_ICM_ACK 0x02 /* acknowledge ICM and clear */
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#define UHA_ABORT_ACK 0x18 /* acknowledge status and clear */
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/*
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* U14_CONFIG bits (read only)
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*/
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#define U14_DMA_CH5 0x0000 /* DMA channel 5 */
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#define U14_DMA_CH6 0x4000 /* 6 */
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#define U14_DMA_CH7 0x8000 /* 7 */
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#define U14_DMA_MASK 0xc000
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#define U14_IRQ15 0x0000 /* IRQ 15 */
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#define U14_IRQ14 0x1000 /* 14 */
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#define U14_IRQ11 0x2000 /* 11 */
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#define U14_IRQ10 0x3000 /* 10 */
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#define U14_IRQ_MASK 0x3000
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#define U14_HOSTID_MASK 0x0007
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/*
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* U24_CONFIG bits (read only)
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*/
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#define U24_MAGIC1 0x08
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#define U24_IRQ15 0x10
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#define U24_IRQ14 0x20
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#define U24_IRQ11 0x40
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#define U24_IRQ10 0x80
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#define U24_IRQ_MASK 0xf0
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#define U24_MAGIC2 0x04
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#define U24_HOSTID_MASK 0x07
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/*
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* EISA registers (offset from slot base)
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*/
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#define EISA_VENDOR 0x0c80 /* vendor ID (2 ports) */
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#define EISA_MODEL 0x0c82 /* model number (2 ports) */
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#define EISA_CONTROL 0x0c84
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#define EISA_RESET 0x04
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#define EISA_ERROR 0x02
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#define EISA_ENABLE 0x01
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/*
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* host_stat error codes
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*/
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#define UHA_NO_ERR 0x00 /* No error supposedly */
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#define UHA_SBUS_ABORT_ERR 0x84 /* scsi bus abort error */
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#define UHA_SBUS_TIMEOUT 0x91 /* scsi bus selection timeout */
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#define UHA_SBUS_OVER_UNDER 0x92 /* scsi bus over/underrun */
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#define UHA_BAD_SCSI_CMD 0x96 /* illegal scsi command */
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#define UHA_AUTO_SENSE_ERR 0x9b /* auto request sense err */
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#define UHA_SBUS_RES_ERR 0xa3 /* scsi bus reset error */
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#define UHA_BAD_SG_LIST 0xff /* invalid scatter gath list */
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#define UHA_NSEG 33 /* number of dma segments supported */
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struct uha_dma_seg {
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physaddr seg_addr;
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physlen seg_len;
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};
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struct uha_mscp {
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u_char opcode:3;
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#define UHA_HAC 0x01 /* host adapter command */
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#define UHA_TSP 0x02 /* target scsi pass through command */
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#define UHA_SDR 0x04 /* scsi device reset */
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u_char xdir:2; /* xfer direction */
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#define UHA_SDET 0x00 /* determined by scsi command */
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#define UHA_SDIN 0x01 /* scsi data in */
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#define UHA_SDOUT 0x02 /* scsi data out */
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#define UHA_NODATA 0x03 /* no data xfer */
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u_char dcn:1; /* disable disconnect for this command */
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u_char ca:1; /* cache control */
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u_char sgth:1; /* scatter gather flag */
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u_char target:3;
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u_char chan:2; /* scsi channel (always 0 for 14f) */
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u_char lun:3;
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physaddr data_addr;
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physlen data_length;
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physaddr link_addr;
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u_char link_id;
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u_char sg_num; /* number of scat gath segs */
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/*in s-g list if sg flag is */
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/*set. starts at 1, 8bytes per */
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u_char req_sense_length;
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u_char scsi_cmd_length;
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struct scsi_generic scsi_cmd;
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u_char host_stat;
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u_char target_stat;
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physaddr sense_ptr; /* if 0 no auto sense */
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struct uha_dma_seg uha_dma[UHA_NSEG];
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struct scsi_sense_data mscp_sense;
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/*-----------------end of hardware supported fields----------------*/
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SLIST_ENTRY(uha_mscp) chain;
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struct uha_mscp *nexthash;
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long hashkey;
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struct scsi_xfer *xs; /* the scsi_xfer for this cmd */
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int flags;
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#define MSCP_ALLOC 0x01
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#define MSCP_ABORT 0x02
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int timeout;
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} __packed;
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