313 lines
12 KiB
C
313 lines
12 KiB
C
/* $OpenBSD: dwiic_pci.c,v 1.24 2023/11/23 14:24:06 jsg Exp $ */
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/*
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* Synopsys DesignWare I2C controller
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* PCI attachment
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*
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* Copyright (c) 2015-2017 joshua stein <jcs@openbsd.org>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <dev/ic/dwiicvar.h>
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/* 13.3: I2C Additional Registers Summary */
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#define LPSS_RESETS 0x204
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#define LPSS_RESETS_I2C (1 << 0) | (1 << 1)
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#define LPSS_RESETS_IDMA (1 << 2)
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#define LPSS_ACTIVELTR 0x210
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#define LPSS_IDLELTR 0x214
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#define LPSS_CAPS 0x2fc
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#define LPSS_CAPS_NO_IDMA (1 << 8)
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#define LPSS_CAPS_TYPE_SHIFT 4
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#define LPSS_CAPS_TYPE_MASK (0xf << LPSS_CAPS_TYPE_SHIFT)
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int dwiic_pci_match(struct device *, void *, void *);
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void dwiic_pci_attach(struct device *, struct device *, void *);
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int dwiic_pci_activate(struct device *, int);
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void dwiic_pci_bus_scan(struct device *,
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struct i2cbus_attach_args *, void *);
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#include "acpi.h"
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#if NACPI > 0
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struct aml_node *acpi_pci_match(struct device *dev, struct pci_attach_args *pa);
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#endif
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const struct cfattach dwiic_pci_ca = {
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sizeof(struct dwiic_softc),
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dwiic_pci_match,
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dwiic_pci_attach,
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NULL,
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dwiic_pci_activate,
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};
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const struct pci_matchid dwiic_pci_ids[] = {
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_100SERIES_I2C0 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_100SERIES_I2C1 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_100SERIES_I2C2 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_100SERIES_I2C3 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_100SERIES_LP_I2C_1 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_100SERIES_LP_I2C_2 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_100SERIES_LP_I2C_3 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_100SERIES_LP_I2C_4 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_100SERIES_LP_I2C_5 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_100SERIES_LP_I2C_6 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_200SERIES_I2C_1 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_200SERIES_I2C_2 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_200SERIES_I2C_3 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_200SERIES_I2C_4 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_300SERIES_I2C_1 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_300SERIES_I2C_2 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_300SERIES_I2C_3 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_300SERIES_I2C_4 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_300SERIES_U_I2C_1 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_300SERIES_U_I2C_2 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_300SERIES_U_I2C_3 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_300SERIES_U_I2C_4 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_300SERIES_U_I2C_5 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_300SERIES_U_I2C_6 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_I2C_1 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_I2C_2 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_I2C_3 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_I2C_4 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_I2C_1 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_I2C_2 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_I2C_3 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_I2C_4 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_I2C_5 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_I2C_6 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_V_I2C_1 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_V_I2C_2 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_V_I2C_3 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_V_I2C_4 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_495SERIES_LP_I2C_1 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_495SERIES_LP_I2C_2 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_495SERIES_LP_I2C_3 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_495SERIES_LP_I2C_4 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_495SERIES_LP_I2C_5 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_495SERIES_LP_I2C_6 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_I2C_0 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_I2C_1 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_I2C_2 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_I2C_3 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_I2C_4 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_I2C_5 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_I2C_6 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_I2C_1 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_I2C_2 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_I2C_3 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_I2C_4 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_I2C_5 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_I2C_6 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_600SERIES_I2C_0 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_600SERIES_I2C_1 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_600SERIES_I2C_2 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_600SERIES_I2C_3 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_600SERIES_I2C_4 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_600SERIES_I2C_5 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_600SERIES_LP_I2C_0 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_600SERIES_LP_I2C_1 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_600SERIES_LP_I2C_2 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_600SERIES_LP_I2C_3 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_600SERIES_LP_I2C_4 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_600SERIES_LP_I2C_5 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_600SERIES_LP_I2C_6 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_600SERIES_LP_I2C_7 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_700SERIES_I2C_0 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_700SERIES_I2C_1 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_700SERIES_I2C_2 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_700SERIES_I2C_3 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_700SERIES_I2C_4 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_700SERIES_I2C_5 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_APOLLOLAKE_I2C_1 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_APOLLOLAKE_I2C_2 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_APOLLOLAKE_I2C_3 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_APOLLOLAKE_I2C_4 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_APOLLOLAKE_I2C_5 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_APOLLOLAKE_I2C_6 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_APOLLOLAKE_I2C_7 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_APOLLOLAKE_I2C_8 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_GLK_I2C_1 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_GLK_I2C_2 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_GLK_I2C_3 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_GLK_I2C_4 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_GLK_I2C_5 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_GLK_I2C_6 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_GLK_I2C_7 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_GLK_I2C_8 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_JSL_I2C_0 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_JSL_I2C_1 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_JSL_I2C_2 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_JSL_I2C_3 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_JSL_I2C_4 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_JSL_I2C_5 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EHL_SIO_I2C_0 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EHL_SIO_I2C_1 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EHL_SIO_I2C_2 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EHL_SIO_I2C_3 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EHL_SIO_I2C_4 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EHL_SIO_I2C_5 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EHL_SIO_I2C_6 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EHL_SIO_I2C_7 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ADL_N_I2C_0 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ADL_N_I2C_1 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ADL_N_I2C_2 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ADL_N_I2C_3 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ADL_N_I2C_4 },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ADL_N_I2C_5 },
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};
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int
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dwiic_pci_match(struct device *parent, void *match, void *aux)
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{
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return (pci_matchbyid(aux, dwiic_pci_ids, nitems(dwiic_pci_ids)));
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}
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void
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dwiic_pci_attach(struct device *parent, struct device *self, void *aux)
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{
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struct dwiic_softc *sc = (struct dwiic_softc *)self;
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struct pci_attach_args *pa = aux;
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#if NACPI > 0
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struct aml_node *node;
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#endif
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bus_size_t iosize;
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pci_intr_handle_t ih;
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const char *intrstr = NULL;
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uint8_t type;
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memcpy(&sc->sc_paa, pa, sizeof(sc->sc_paa));
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pci_set_powerstate(pa->pa_pc, pa->pa_tag, PCI_PMCSR_STATE_D0);
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if (pci_mapreg_map(pa, PCI_MAPREG_START, PCI_MAPREG_MEM_TYPE_64BIT, 0,
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&sc->sc_iot, &sc->sc_ioh, NULL, &iosize, 0)) {
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printf(": can't map mem space\n");
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return;
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}
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sc->sc_caps = bus_space_read_4(sc->sc_iot, sc->sc_ioh, LPSS_CAPS);
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type = sc->sc_caps & LPSS_CAPS_TYPE_MASK;
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type >>= LPSS_CAPS_TYPE_SHIFT;
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if (type != 0) {
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printf(": type %d not supported\n", type);
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return;
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}
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/* un-reset - page 958 */
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bus_space_write_4(sc->sc_iot, sc->sc_ioh, LPSS_RESETS,
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(LPSS_RESETS_I2C | LPSS_RESETS_IDMA));
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#if NACPI > 0
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/* fetch timing parameters from ACPI, if possible */
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node = acpi_pci_match(self, &sc->sc_paa);
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if (node != NULL) {
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sc->sc_devnode = node;
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dwiic_acpi_get_params(sc, "SSCN", &sc->ss_hcnt, &sc->ss_lcnt,
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NULL);
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dwiic_acpi_get_params(sc, "FMCN", &sc->fs_hcnt, &sc->fs_lcnt,
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&sc->sda_hold_time);
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}
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#endif
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if (dwiic_init(sc)) {
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printf(": failed initializing\n");
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return;
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}
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/* leave the controller disabled */
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dwiic_write(sc, DW_IC_INTR_MASK, 0);
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dwiic_enable(sc, 0);
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dwiic_read(sc, DW_IC_CLR_INTR);
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/* install interrupt handler */
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sc->sc_poll = 1;
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if (pci_intr_map(&sc->sc_paa, &ih) == 0) {
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intrstr = pci_intr_string(sc->sc_paa.pa_pc, ih);
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sc->sc_ih = pci_intr_establish(sc->sc_paa.pa_pc, ih, IPL_BIO,
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dwiic_intr, sc, sc->sc_dev.dv_xname);
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if (sc->sc_ih != NULL) {
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printf(": %s", intrstr);
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sc->sc_poll = 0;
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}
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}
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if (sc->sc_poll)
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printf(": polling");
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printf("\n");
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rw_init(&sc->sc_i2c_lock, "iiclk");
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/* setup and attach iic bus */
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sc->sc_i2c_tag.ic_cookie = sc;
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sc->sc_i2c_tag.ic_acquire_bus = dwiic_i2c_acquire_bus;
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sc->sc_i2c_tag.ic_release_bus = dwiic_i2c_release_bus;
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sc->sc_i2c_tag.ic_exec = dwiic_i2c_exec;
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sc->sc_i2c_tag.ic_intr_establish = dwiic_i2c_intr_establish;
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sc->sc_i2c_tag.ic_intr_string = dwiic_i2c_intr_string;
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bzero(&sc->sc_iba, sizeof(sc->sc_iba));
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sc->sc_iba.iba_name = "iic";
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sc->sc_iba.iba_tag = &sc->sc_i2c_tag;
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sc->sc_iba.iba_bus_scan = dwiic_pci_bus_scan;
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sc->sc_iba.iba_bus_scan_arg = sc;
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config_found((struct device *)sc, &sc->sc_iba, iicbus_print);
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#if NACPI > 0 && !defined(SMALL_KERNEL)
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if (sc->sc_devnode) {
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sc->sc_devnode->i2c = &sc->sc_i2c_tag;
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acpi_register_gsb(acpi_softc, sc->sc_devnode);
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}
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#endif
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}
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int
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dwiic_pci_activate(struct device *self, int act)
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{
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struct dwiic_softc *sc = (struct dwiic_softc *)self;
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switch (act) {
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case DVACT_WAKEUP:
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bus_space_write_4(sc->sc_iot, sc->sc_ioh, LPSS_RESETS,
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(LPSS_RESETS_I2C | LPSS_RESETS_IDMA));
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break;
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}
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dwiic_activate(self, act);
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return 0;
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}
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void
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dwiic_pci_bus_scan(struct device *iic, struct i2cbus_attach_args *iba,
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void *aux)
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{
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struct dwiic_softc *sc = (struct dwiic_softc *)aux;
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sc->sc_iic = iic;
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#if NACPI > 0
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if (sc->sc_devnode != NULL)
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aml_find_node(sc->sc_devnode, "_HID", dwiic_acpi_found_hid, sc);
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#endif
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}
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