255 lines
10 KiB
C
255 lines
10 KiB
C
/* $OpenBSD: pccbbreg.h,v 1.12 2012/10/18 21:40:49 deraadt Exp $ */
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/* $NetBSD: pccbbreg.h,v 1.5 2000/06/07 09:02:47 haya Exp $ */
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/*
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* Copyright (c) 1999 HAYAKAWA Koichi. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DEV_PCI_PCCBBREG_H_
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#define _DEV_PCI_PCCBBREG_H_
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#define PCI_SOCKBASE 0x10 /* Socket Base Address Register */
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#define PCI_BUSNUM 0x18 /* Latency timer, Subordinate bus number */
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#define PCI_BCR_INTR 0x3C /* Intr line, intr pin, bridge control regs */
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#define PCI_LEGACY 0x44 /* Legacy IO register address (32 bits) */
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#define PCI_SYSCTRL 0x80 /* System control */
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#define PCI_CBCTRL 0x90 /* Retry status, Card ctrl, Device ctrl */
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#define PCI_CLASS_INTERFACE_MASK 0xFFFFFF00
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#define PCI_CLASS_INTERFACE_YENTA 0x06070000
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/* CardBus latency timer, Subordinate bus no, CardBus bus no and PCI bus no */
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#define PCI_CB_LSCP_REG 0x18
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/* CardBus memory and io windows */
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#define PCI_CB_MEMBASE0 0x1C
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#define PCI_CB_MEMLIMIT0 0x20
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#define PCI_CB_MEMBASE1 0x24
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#define PCI_CB_MEMLIMIT1 0x28
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#define PCI_CB_IOBASE0 0x2C
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#define PCI_CB_IOLIMIT0 0x30
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#define PCI_CB_IOBASE1 0x34
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#define PCI_CB_IOLIMIT1 0x38
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/* PCI_CB_LSCP_REG */
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#define PCI_CB_LATENCY_SHIFT 24
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#define PCI_CB_LATENCY_MASK 0xFF
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#define PCI_CB_LATENCY(x)( \
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((x) >> PCI_CB_LATENCY_SHIFT) & PCI_CB_LATENCY_MASK)
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/*
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* Cardbus socket registers
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*/
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#define CB_SOCKET_EVENT 0x00 /* Event */
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#define CB_SOCKET_EVENT_CSTS 0x01 /* CARDSTS event occurs */
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#define CB_SOCKET_EVENT_CD 0x06 /* CD event occurs */
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#define CB_SOCKET_EVENT_CD1 0x02 /* CD1 event occurs */
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#define CB_SOCKET_EVENT_CD2 0x04 /* CD2 event occurs */
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#define CB_SOCKET_EVENT_POWER 0x08 /* Power cycle event occurs */
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#define CB_SOCKET_MASK 0x04 /* Mask */
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#define CB_SOCKET_MASK_CSTS 0x01 /* CARDSTS event mask */
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#define CB_SOCKET_MASK_CD 0x06 /* CD event mask */
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#define CB_SOCKET_MASK_POWER 0x08 /* Power cycle event mask */
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#define CB_SOCKET_STAT 0x08 /* Present-state */
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#define CB_SOCKET_STAT_CARDSTS 0x00000001 /* Card status change bit */
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#define CB_SOCKET_STAT_CD1 0x00000002 /* Card detect 1 */
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#define CB_SOCKET_STAT_CD2 0x00000004 /* Card detect 2 */
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#define CB_SOCKET_STAT_CD 0x00000006 /* Card detect 1 and 2 */
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#define CB_SOCKET_STAT_PWRCYCLE 0x00000008 /* Power cycle */
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#define CB_SOCKET_STAT_16BIT 0x00000010 /* 16-bit card */
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#define CB_SOCKET_STAT_CB 0x00000020 /* Cardbus card */
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#define CB_SOCKET_STAT_IREQ 0x00000040 /* READY(~IREQ)//(~CINT) */
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/* bit */
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#define CB_SOCKET_STAT_NOTCARD 0x00000080 /* Inserted card is */
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/* unrecognisable */
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#define CB_SOCKET_STAT_DATALOST 0x00000100 /* Data lost */
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#define CB_SOCKET_STAT_BADVCC 0x00000200 /* Bad Vcc Request */
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#define CB_SOCKET_STAT_5VCARD 0x00000400 /* 5 V Card */
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#define CB_SOCKET_STAT_3VCARD 0x00000800 /* 3.3 V Card */
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#define CB_SOCKET_STAT_XVCARD 0x00001000 /* X.X V Card */
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#define CB_SOCKET_STAT_YVCARD 0x00002000 /* Y.Y V Card */
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#define CB_SOCKET_STAT_5VSOCK 0x10000000 /* 5 V Socket */
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#define CB_SOCKET_STAT_3VSOCK 0x20000000 /* 3.3 V Socket */
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#define CB_SOCKET_STAT_XVSOCK 0x40000000 /* X.X V Socket */
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#define CB_SOCKET_STAT_YVSOCK 0x80000000 /* Y.Y V Socket */
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#define CB_SOCKET_FORCE 0x0C /* Force event */
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#define CB_SOCKET_FORCE_BADVCC 0x0200 /* Bad Vcc Request */
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#define CB_SOCKET_CTRL 0x10 /* Control */
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#define CB_SOCKET_CTRL_VPPMASK 0x007
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#define CB_SOCKET_CTRL_VPP_OFF 0x000
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#define CB_SOCKET_CTRL_VPP_12V 0x001
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#define CB_SOCKET_CTRL_VPP_5V 0x002
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#define CB_SOCKET_CTRL_VPP_3V 0x003
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#define CB_SOCKET_CTRL_VPP_XV 0x004
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#define CB_SOCKET_CTRL_VPP_YV 0x005
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#define CB_SOCKET_CTRL_VCCMASK 0x070
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#define CB_SOCKET_CTRL_VCC_OFF 0x000
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#define CB_SOCKET_CTRL_VCC_5V 0x020
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#define CB_SOCKET_CTRL_VCC_3V 0x030
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#define CB_SOCKET_CTRL_VCC_XV 0x040
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#define CB_SOCKET_CTRL_VCC_YV 0x050
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#define CB_SOCKET_CTRL_STOPCLK 0x080
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#define PCCBB_SOCKEVENT_BITS "\020\001CSTS\002CD1\003CD2\004PWR"
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#define PCCBB_SOCKSTATE_BITS \
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"\020\001CSTS\002CD1\003CD3\004PWR\00516BIT\006CB\007CINT\010NOTA" \
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"\011DLOST\012BADVCC\0135v\0143v\015Xv\016Yv\0355vS\0363vS\037XvS\040YvS"
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/* PCI_BCR_INTR bits for generic PCI-CardBus bridge */
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#define CB_BCR_RESET_ENABLE 0x00400000
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#define CB_BCR_INTR_IREQ_ENABLE 0x00800000
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#define CB_BCR_PREFETCH_MEMWIN0 0x01000000
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#define CB_BCR_PREFETCH_MEMWIN1 0x02000000
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#define CB_BCR_WRITE_POST_ENABLE 0x04000000
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/* TI [14][245]xx */
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#define PCI12XX_MMCTRL 0x84
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/* TI 12xx/14xx/15xx (except 1250, 1251, 1251B/1450) */
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#define PCI12XX_MFUNC 0x8c
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#define PCI12XX_MFUNC_PIN0 0x0000000F
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#define PCI12XX_MFUNC_PIN0_INTA 0x02
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#define PCI12XX_MFUNC_PIN1 0x000000F0
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#define PCI12XX_MFUNC_PIN1_INTB 0x20
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#define PCI12XX_MFUNC_PIN2 0x00000F00
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#define PCI12XX_MFUNC_PIN3 0x0000F000
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#define PCI12XX_MFUNC_PIN3_INTSER 0x00001000
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#define PCI12XX_MFUNC_PIN4 0x000F0000
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#define PCI12XX_MFUNC_PIN5 0x00F00000
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#define PCI12XX_MFUNC_PIN6 0x0F000000
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#define PCI12XX_MFUNC_DEFAULT PCI12XX_MFUNC_PIN3_INTSER
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/* PCI_CBCTRL bits for TI PCI113X */
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#define PCI113X_CBCTRL_INT_SERIAL 0x040000
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#define PCI113X_CBCTRL_INT_ISA 0x020000
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#define PCI113X_CBCTRL_INT_MASK 0x060000
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#define PCI113X_CBCTRL_RIENB 0x008000 /* Ring indicate output */
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/* enable */
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#define PCI113X_CBCTRL_ZVENAB 0x004000 /* ZV mode enable */
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#define PCI113X_CBCTRL_PCI_IRQ_ENA 0x002000 /* PCI intr enable */
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/* (funct and CSC) */
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#define PCI113X_CBCTRL_PCI_INTR 0x001000 /* PCI functional intr req */
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#define PCI113X_CBCTRL_PCI_CSC 0x000800 /* CSC intr route to PCI */
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#define PCI113X_CBCTRL_PCI_CSC_D 0x000400 /* Unknown */
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#define PCI113X_CBCTRL_SPK_ENA 0x000200 /* Speaker enable */
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#define PCI113X_CBCTRL_INTR_DET 0x000100 /* Functional interrupt */
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/* detect */
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/* PCI_CBCTRL bits for TI PCI12XX */
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#define PCI12XX_SYSCTRL_INTRTIE 0x20000000u
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#define PCI12XX_SYSCTRL_VCCPROT 0x200000
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#define PCI12XX_SYSCTRL_PWRSAVE 0x000040
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#define PCI12XX_SYSCTRL_SUBSYSRW 0x000020
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#define PCI12XX_SYSCTRL_CB_DPAR 0x000010
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#define PCI12XX_SYSCTRL_CDMA_EN 0x000008
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#define PCI12XX_SYSCTRL_KEEPCLK 0x000002
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#define PCI12XX_SYSCTRL_RIMUX 0x000001
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#define PCI12XX_CBCTRL_CSC 0x20000000u
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#define PCI12XX_CBCTRL_ASYNC_CSC 0x01000000u
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#define PCI12XX_CBCTRL_INT_SERIAL 0x060000
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#define PCI12XX_CBCTRL_INT_PCI_SERIAL 0x040000
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#define PCI12XX_CBCTRL_INT_ISA 0x020000
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#define PCI12XX_CBCTRL_INT_PCI 0x000000
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#define PCI12XX_CBCTRL_INT_MASK 0x060000
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#define PCI12XX_CBCTRL_RIENB 0x008000 /* Ring indicate output */
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/* enable */
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#define PCI12XX_CBCTRL_ZVENAB 0x004000 /* ZV mode enable */
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#define PCI12XX_CBCTRL_AUD2MUX 0x000400 /* Unknown */
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#define PCI12XX_CBCTRL_SPK_ENA 0x000200 /* Speaker enable */
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#define PCI12XX_CBCTRL_INTR_DET 0x000100 /* Functional interrupt */
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/* detect */
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/* PCI_BCR_INTR additional bit for Rx5C46[567] */
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#define CB_BCRI_RL_3E0_ENA 0x08000000
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#define CB_BCRI_RL_3E2_ENA 0x10000000
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/*
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* Special register definition for Toshiba ToPIC95/97
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* These values are borrowed from pcmcia-cs/Linux.
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*/
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#define TOPIC_SOCKET_CTRL 0x90
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#define TOPIC_SOCKET_CTRL_SCR_IRQSEL 0x00000001 /* PCI intr */
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#define TOPIC_SLOT_CTRL 0xA0
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#define TOPIC_SLOT_CTRL_SLOTON 0x00000080
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#define TOPIC_SLOT_CTRL_SLOTEN 0x00000040
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#define TOPIC_SLOT_CTRL_ID_LOCK 0x00000020
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#define TOPIC_SLOT_CTRL_ID_WP 0x00000010
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#define TOPIC_SLOT_CTRL_PORT_MASK 0x0000000C
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#define TOPIC_SLOT_CTRL_PORT_SHIFT 2
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#define TOPIC_SLOT_CTRL_OSF_MASK 0x00000003
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#define TOPIC_SLOT_CTRL_OSF_SHIFT 0
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#define TOPIC_SLOT_CTRL_INTB 0x00002000
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#define TOPIC_SLOT_CTRL_INTA 0x00001000
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#define TOPIC_SLOT_CTRL_INT_MASK 0x00003000
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#define TOPIC_SLOT_CTRL_CLOCK_MASK 0x00000C00
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#define TOPIC_SLOT_CTRL_CLOCK_2 0x00000800 /* PCI Clock/2 */
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#define TOPIC_SLOT_CTRL_CLOCK_1 0x00000400 /* PCI Clock */
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#define TOPIC_SLOT_CTRL_CLOCK_0 0x00000000 /* No clock */
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#define TOPIC97_SLOT_CTRL_STSIRQP 0x00000400 /* Status change intr */
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/* pulse */
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#define TOPIC97_SLOT_CTRL_IRQP 0x00000200 /* Function intr pulse */
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#define TOPIC97_SLOT_CTRL_PCIINT 0x00000100 /* Intr routing to PCI INT */
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#define TOPIC_SLOT_CTRL_CARDBUS 0x80000000
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#define TOPIC_SLOT_CTRL_VS1 0x04000000
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#define TOPIC_SLOT_CTRL_VS2 0x02000000
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#define TOPIC_SLOT_CTRL_SWDETECT 0x01000000
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#define TOPIC_REG_CTRL 0x00A4
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#define TOPIC_REG_CTRL_RESUME_RESET 0x80000000
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#define TOPIC_REG_CTRL_REMOVE_RESET 0x40000000
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#define TOPIC97_REG_CTRL_CLKRUN_ENA 0x20000000
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#define TOPIC97_REG_CTRL_TESTMODE 0x10000000
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#define TOPIC97_REG_CTRL_IOPLUP 0x08000000
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#define TOPIC_REG_CTRL_BUFOFF_PWROFF 0x02000000
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#define TOPIC_REG_CTRL_BUFOFF_SIGOFF 0x01000000
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#define TOPIC97_REG_CTRL_CB_DEV_MASK 0x0000F800
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#define TOPIC97_REG_CTRL_CB_DEV_SHIFT 11
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#define TOPIC97_REG_CTRL_RI_DISABLE 0x00000004
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#define TOPIC97_REG_CTRL_CAUDIO_OFF 0x00000002
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#define TOPIC_REG_CTRL_CAUDIO_INVERT 0x00000001
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/*
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* Additional O2Micro registers
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*
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* 'reserved' register at 0x94/D4. allows setting read prefetch and write
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* bursting. read prefetching for example makes the RME Hammerfall DSP
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* working. for some bridges it is at 0x94, for others at 0xD4. it's
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* ok to write to both registers on all O2 bridges.
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* from Eric Still, 02Micro.
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*/
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#define O2MICRO_RESERVED1 0x94
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#define O2MICRO_RESERVED2 0xD4
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#define O2MICRO_RES_READ_PREFETCH 0x02
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#define O2MICRO_RES_WRITE_BURST 0x08
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#endif /* _DEV_PCI_PCCBBREG_H_ */
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