1057 lines
25 KiB
C
1057 lines
25 KiB
C
/* $OpenBSD: spif.c,v 1.27 2022/07/02 08:50:42 visa Exp $ */
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/*
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* Copyright (c) 1999-2002 Jason L. Wright (jason@thought.net)
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* Effort sponsored in part by the Defense Advanced Research Projects
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* Agency (DARPA) and Air Force Research Laboratory, Air Force
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* Materiel Command, USAF, under agreement number F30602-01-2-0537.
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*
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*/
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/*
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* Driver for the SUNW,spif: 8 serial, 1 parallel sbus board
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* based heavily on Iain Hibbert's driver for the MAGMA cards
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/proc.h>
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#include <sys/device.h>
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#include <sys/kernel.h>
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#include <sys/fcntl.h>
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#include <sys/errno.h>
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#include <sys/ioctl.h>
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#include <sys/mbuf.h>
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#include <sys/socket.h>
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#include <sys/syslog.h>
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#include <sys/malloc.h>
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#include <sys/tty.h>
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#include <sys/conf.h>
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#include <machine/autoconf.h>
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#include <dev/sbus/sbusvar.h>
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#include <dev/sbus/spifreg.h>
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#include <dev/sbus/spifvar.h>
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int spifmatch(struct device *, void *, void *);
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void spifattach(struct device *, struct device *, void *);
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int sttymatch(struct device *, void *, void *);
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void sttyattach(struct device *, struct device *, void *);
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int sttyopen(dev_t, int, int, struct proc *);
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int sttyclose(dev_t, int, int, struct proc *);
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int sttyread(dev_t, struct uio *, int);
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int sttywrite(dev_t, struct uio *, int);
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int sttyioctl(dev_t, u_long, caddr_t, int, struct proc *);
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int sttystop(struct tty *, int);
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int spifstcintr(void *);
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int spifstcintr_mx(struct spif_softc *, int *);
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int spifstcintr_tx(struct spif_softc *, int *);
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int spifstcintr_rx(struct spif_softc *, int *);
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int spifstcintr_rxexception(struct spif_softc *, int *);
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void spifsoftintr(void *);
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int stty_param(struct tty *, struct termios *);
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struct tty *sttytty(dev_t);
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int stty_modem_control(struct stty_port *, int, int);
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void stty_write_ccr(struct spif_softc *, u_int8_t);
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int stty_compute_baud(speed_t, int, u_int8_t *, u_int8_t *);
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void stty_start(struct tty *);
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int sbppmatch(struct device *, void *, void *);
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void sbppattach(struct device *, struct device *, void *);
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int sbppopen(dev_t, int, int, struct proc *);
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int sbppclose(dev_t, int, int, struct proc *);
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int sbppread(dev_t, struct uio *, int);
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int sbppwrite(dev_t, struct uio *, int);
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int sbpp_rw(dev_t, struct uio *);
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int spifppcintr(void *);
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int sbppkqfilter(dev_t, struct knote *);
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int sbppioctl(dev_t, u_long, caddr_t, int, struct proc *);
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const struct cfattach spif_ca = {
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sizeof (struct spif_softc), spifmatch, spifattach
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};
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struct cfdriver spif_cd = {
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NULL, "spif", DV_DULL
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};
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const struct cfattach stty_ca = {
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sizeof(struct stty_softc), sttymatch, sttyattach
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};
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struct cfdriver stty_cd = {
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NULL, "stty", DV_TTY
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};
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const struct cfattach sbpp_ca = {
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sizeof(struct sbpp_softc), sbppmatch, sbppattach
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};
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struct cfdriver sbpp_cd = {
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NULL, "sbpp", DV_DULL
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};
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/* normal STC access */
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#define STC_WRITE(sc,r,v) \
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bus_space_write_1((sc)->sc_bustag, (sc)->sc_stch, (r), (v))
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#define STC_READ(sc,r) \
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bus_space_read_1((sc)->sc_bustag, (sc)->sc_stch, (r))
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/* IACK STC access */
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#define ISTC_WRITE(sc,r,v) \
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bus_space_write_1((sc)->sc_bustag, (sc)->sc_istch, (r), (v))
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#define ISTC_READ(sc,r) \
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bus_space_read_1((sc)->sc_bustag, (sc)->sc_istch, (r))
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/* PPC access */
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#define PPC_WRITE(sc,r,v) \
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bus_space_write_1((sc)->sc_bustag, (sc)->sc_ppch, (r), (v))
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#define PPC_READ(sc,r) \
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bus_space_read_1((sc)->sc_bustag, (sc)->sc_ppch, (r))
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#define DTR_WRITE(sc,port,v) \
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do { \
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sc->sc_ttys->sc_port[(port)].sp_dtr = v; \
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bus_space_write_1((sc)->sc_bustag, \
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sc->sc_dtrh, port, (v == 0) ? 1 : 0); \
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} while (0)
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#define DTR_READ(sc,port) ((sc)->sc_ttys->sc_port[(port)].sp_dtr)
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int
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spifmatch(struct device *parent, void *vcf, void *aux)
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{
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struct cfdata *cf = vcf;
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struct sbus_attach_args *sa = aux;
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if (strcmp(cf->cf_driver->cd_name, sa->sa_name) &&
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strcmp("SUNW,spif", sa->sa_name))
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return (0);
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return (1);
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}
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void
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spifattach(struct device *parent, struct device *self, void *aux)
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{
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struct spif_softc *sc = (struct spif_softc *)self;
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struct sbus_attach_args *sa = aux;
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if (sa->sa_nintr != 2) {
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printf(": expected %d interrupts, got %d\n", 2, sa->sa_nintr);
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return;
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}
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if (sa->sa_nreg != 1) {
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printf(": expected %d registers, got %d\n", 1, sa->sa_nreg);
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return;
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}
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sc->sc_bustag = sa->sa_bustag;
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if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[0].sbr_slot,
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sa->sa_reg[0].sbr_offset, sa->sa_reg[0].sbr_size,
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0, 0, &sc->sc_regh) != 0) {
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printf(": can't map registers\n");
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return;
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}
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if (bus_space_subregion(sc->sc_bustag, sc->sc_regh,
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DTR_REG_OFFSET, DTR_REG_LEN, &sc->sc_dtrh) != 0) {
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printf(": can't map dtr regs\n");
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goto fail_unmapregs;
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}
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if (bus_space_subregion(sc->sc_bustag, sc->sc_regh,
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STC_REG_OFFSET, STC_REG_LEN, &sc->sc_stch) != 0) {
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printf(": can't map dtr regs\n");
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goto fail_unmapregs;
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}
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if (bus_space_subregion(sc->sc_bustag, sc->sc_regh,
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ISTC_REG_OFFSET, ISTC_REG_LEN, &sc->sc_istch) != 0) {
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printf(": can't map dtr regs\n");
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goto fail_unmapregs;
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}
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if (bus_space_subregion(sc->sc_bustag, sc->sc_regh,
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PPC_REG_OFFSET, PPC_REG_LEN, &sc->sc_ppch) != 0) {
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printf(": can't map dtr regs\n");
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goto fail_unmapregs;
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}
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sc->sc_ppcih = bus_intr_establish(sa->sa_bustag,
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sa->sa_intr[PARALLEL_INTR].sbi_pri, IPL_TTY, 0, spifppcintr, sc,
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self->dv_xname);
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if (sc->sc_ppcih == NULL) {
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printf(": failed to establish ppc interrupt\n");
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goto fail_unmapregs;
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}
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sc->sc_stcih = bus_intr_establish(sa->sa_bustag,
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sa->sa_intr[SERIAL_INTR].sbi_pri, IPL_TTY, 0, spifstcintr, sc,
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self->dv_xname);
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if (sc->sc_stcih == NULL) {
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printf(": failed to establish stc interrupt\n");
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goto fail_unmapregs;
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}
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sc->sc_softih = softintr_establish(IPL_TTY, spifsoftintr, sc);
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if (sc->sc_softih == NULL) {
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printf(": can't get soft intr\n");
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goto fail_unmapregs;
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}
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sc->sc_node = sa->sa_node;
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sc->sc_rev = getpropint(sc->sc_node, "revlev", 0);
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sc->sc_osc = getpropint(sc->sc_node, "verosc", 0);
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switch (sc->sc_osc) {
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case SPIF_OSC10:
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sc->sc_osc = 10000000;
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break;
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case SPIF_OSC9:
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default:
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sc->sc_osc = 9830400;
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break;
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}
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sc->sc_nser = 8;
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sc->sc_npar = 1;
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sc->sc_rev2 = STC_READ(sc, STC_GFRCR);
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STC_WRITE(sc, STC_GSVR, 0);
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stty_write_ccr(sc, CD180_CCR_CMD_RESET | CD180_CCR_RESETALL);
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while (STC_READ(sc, STC_GSVR) != 0xff);
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while (STC_READ(sc, STC_GFRCR) != sc->sc_rev2);
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STC_WRITE(sc, STC_PPRH, CD180_PPRH);
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STC_WRITE(sc, STC_PPRL, CD180_PPRL);
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STC_WRITE(sc, STC_MSMR, SPIF_MSMR);
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STC_WRITE(sc, STC_TSMR, SPIF_TSMR);
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STC_WRITE(sc, STC_RSMR, SPIF_RSMR);
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STC_WRITE(sc, STC_GSVR, 0);
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STC_WRITE(sc, STC_GSCR1, 0);
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STC_WRITE(sc, STC_GSCR2, 0);
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STC_WRITE(sc, STC_GSCR3, 0);
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printf(": rev %x chiprev %x osc %sMHz\n",
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sc->sc_rev, sc->sc_rev2, clockfreq(sc->sc_osc));
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(void)config_found(self, sttymatch, NULL);
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(void)config_found(self, sbppmatch, NULL);
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return;
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fail_unmapregs:
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bus_space_unmap(sa->sa_bustag, sc->sc_regh, sa->sa_reg[0].sbr_size);
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}
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int
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sttymatch(struct device *parent, void *vcf, void *aux)
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{
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struct spif_softc *sc = (struct spif_softc *)parent;
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return (aux == sttymatch && sc->sc_ttys == NULL);
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}
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void
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sttyattach(struct device *parent, struct device *dev, void *aux)
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{
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struct spif_softc *sc = (struct spif_softc *)parent;
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struct stty_softc *ssc = (struct stty_softc *)dev;
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int port;
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sc->sc_ttys = ssc;
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for (port = 0; port < sc->sc_nser; port++) {
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struct stty_port *sp = &ssc->sc_port[port];
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struct tty *tp;
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DTR_WRITE(sc, port, 0);
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tp = ttymalloc(0);
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tp->t_oproc = stty_start;
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tp->t_param = stty_param;
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sp->sp_tty = tp;
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sp->sp_sc = sc;
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sp->sp_channel = port;
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sp->sp_rbuf = malloc(STTY_RBUF_SIZE, M_DEVBUF, M_NOWAIT);
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if(sp->sp_rbuf == NULL)
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break;
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sp->sp_rend = sp->sp_rbuf + STTY_RBUF_SIZE;
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}
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ssc->sc_nports = port;
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printf(": %d tty%s\n", port, port == 1 ? "" : "s");
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}
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int
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sttyopen(dev_t dev, int flags, int mode, struct proc *p)
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{
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struct spif_softc *csc;
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struct stty_softc *sc;
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struct stty_port *sp;
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struct tty *tp;
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int card = SPIF_CARD(dev);
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int port = SPIF_PORT(dev);
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int s;
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if (card >= stty_cd.cd_ndevs || card >= spif_cd.cd_ndevs)
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return (ENXIO);
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sc = stty_cd.cd_devs[card];
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csc = spif_cd.cd_devs[card];
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if (sc == NULL || csc == NULL)
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return (ENXIO);
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if (port >= sc->sc_nports)
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return (ENXIO);
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sp = &sc->sc_port[port];
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tp = sp->sp_tty;
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tp->t_dev = dev;
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if (!ISSET(tp->t_state, TS_ISOPEN)) {
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SET(tp->t_state, TS_WOPEN);
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ttychars(tp);
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tp->t_iflag = TTYDEF_IFLAG;
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tp->t_oflag = TTYDEF_OFLAG;
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tp->t_cflag = TTYDEF_CFLAG;
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if (ISSET(sp->sp_openflags, TIOCFLAG_CLOCAL))
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SET(tp->t_cflag, CLOCAL);
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if (ISSET(sp->sp_openflags, TIOCFLAG_CRTSCTS))
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SET(tp->t_cflag, CRTSCTS);
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if (ISSET(sp->sp_openflags, TIOCFLAG_MDMBUF))
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SET(tp->t_cflag, MDMBUF);
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tp->t_lflag = TTYDEF_LFLAG;
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tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED;
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sp->sp_rput = sp->sp_rget = sp->sp_rbuf;
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s = spltty();
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STC_WRITE(csc, STC_CAR, sp->sp_channel);
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stty_write_ccr(csc, CD180_CCR_CMD_RESET|CD180_CCR_RESETCHAN);
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STC_WRITE(csc, STC_CAR, sp->sp_channel);
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stty_param(tp, &tp->t_termios);
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ttsetwater(tp);
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STC_WRITE(csc, STC_SRER, CD180_SRER_CD | CD180_SRER_RXD);
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if (ISSET(sp->sp_openflags, TIOCFLAG_SOFTCAR) || sp->sp_carrier)
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SET(tp->t_state, TS_CARR_ON);
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else
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CLR(tp->t_state, TS_CARR_ON);
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}
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else if (ISSET(tp->t_state, TS_XCLUDE) && suser(p) != 0) {
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return (EBUSY);
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} else {
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s = spltty();
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}
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if (!ISSET(flags, O_NONBLOCK)) {
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while (!ISSET(tp->t_cflag, CLOCAL) &&
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!ISSET(tp->t_state, TS_CARR_ON)) {
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int error;
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SET(tp->t_state, TS_WOPEN);
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error = ttysleep(tp, &tp->t_rawq, TTIPRI | PCATCH,
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ttopen);
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if (error != 0) {
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splx(s);
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CLR(tp->t_state, TS_WOPEN);
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return (error);
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}
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}
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}
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splx(s);
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return ((*linesw[tp->t_line].l_open)(dev, tp, p));
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}
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int
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sttyclose(dev_t dev, int flags, int mode, struct proc *p)
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{
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struct stty_softc *sc = stty_cd.cd_devs[SPIF_CARD(dev)];
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struct stty_port *sp = &sc->sc_port[SPIF_PORT(dev)];
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struct spif_softc *csc = sp->sp_sc;
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struct tty *tp = sp->sp_tty;
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int port = SPIF_PORT(dev);
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int s;
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(*linesw[tp->t_line].l_close)(tp, flags, p);
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s = spltty();
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if (ISSET(tp->t_cflag, HUPCL) || !ISSET(tp->t_state, TS_ISOPEN)) {
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stty_modem_control(sp, 0, DMSET);
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STC_WRITE(csc, STC_CAR, port);
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STC_WRITE(csc, STC_CCR,
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CD180_CCR_CMD_RESET|CD180_CCR_RESETCHAN);
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}
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splx(s);
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ttyclose(tp);
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return (0);
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}
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int
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sttyioctl(dev_t dev, u_long cmd, caddr_t data, int flags, struct proc *p)
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{
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struct stty_softc *stc = stty_cd.cd_devs[SPIF_CARD(dev)];
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struct stty_port *sp = &stc->sc_port[SPIF_PORT(dev)];
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struct spif_softc *sc = sp->sp_sc;
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struct tty *tp = sp->sp_tty;
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int error;
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error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flags, p);
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if (error >= 0)
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return (error);
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error = ttioctl(tp, cmd, data, flags, p);
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if (error >= 0)
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return (error);
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error = 0;
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switch (cmd) {
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case TIOCSBRK:
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SET(sp->sp_flags, STTYF_SET_BREAK);
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STC_WRITE(sc, STC_CAR, sp->sp_channel);
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STC_WRITE(sc, STC_SRER,
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STC_READ(sc, STC_SRER) | CD180_SRER_TXD);
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break;
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case TIOCCBRK:
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SET(sp->sp_flags, STTYF_CLR_BREAK);
|
|
STC_WRITE(sc, STC_CAR, sp->sp_channel);
|
|
STC_WRITE(sc, STC_SRER,
|
|
STC_READ(sc, STC_SRER) | CD180_SRER_TXD);
|
|
break;
|
|
case TIOCSDTR:
|
|
stty_modem_control(sp, TIOCM_DTR, DMBIS);
|
|
break;
|
|
case TIOCCDTR:
|
|
stty_modem_control(sp, TIOCM_DTR, DMBIC);
|
|
break;
|
|
case TIOCMBIS:
|
|
stty_modem_control(sp, *((int *)data), DMBIS);
|
|
break;
|
|
case TIOCMBIC:
|
|
stty_modem_control(sp, *((int *)data), DMBIC);
|
|
break;
|
|
case TIOCMGET:
|
|
*((int *)data) = stty_modem_control(sp, 0, DMGET);
|
|
break;
|
|
case TIOCMSET:
|
|
stty_modem_control(sp, *((int *)data), DMSET);
|
|
break;
|
|
case TIOCGFLAGS:
|
|
*((int *)data) = sp->sp_openflags;
|
|
break;
|
|
case TIOCSFLAGS:
|
|
if (suser(p))
|
|
error = EPERM;
|
|
else
|
|
sp->sp_openflags = *((int *)data) &
|
|
(TIOCFLAG_SOFTCAR | TIOCFLAG_CLOCAL |
|
|
TIOCFLAG_CRTSCTS | TIOCFLAG_MDMBUF);
|
|
break;
|
|
default:
|
|
error = ENOTTY;
|
|
}
|
|
|
|
return (error);
|
|
}
|
|
|
|
int
|
|
stty_modem_control(struct stty_port *sp, int bits, int how)
|
|
{
|
|
struct spif_softc *csc = sp->sp_sc;
|
|
struct tty *tp = sp->sp_tty;
|
|
int s, msvr;
|
|
|
|
s = spltty();
|
|
STC_WRITE(csc, STC_CAR, sp->sp_channel);
|
|
|
|
switch (how) {
|
|
case DMGET:
|
|
bits = TIOCM_LE;
|
|
if (DTR_READ(csc, sp->sp_channel))
|
|
bits |= TIOCM_DTR;
|
|
msvr = STC_READ(csc, STC_MSVR);
|
|
if (ISSET(msvr, CD180_MSVR_DSR))
|
|
bits |= TIOCM_DSR;
|
|
if (ISSET(msvr, CD180_MSVR_CD))
|
|
bits |= TIOCM_CD;
|
|
if (ISSET(msvr, CD180_MSVR_CTS))
|
|
bits |= TIOCM_CTS;
|
|
if (ISSET(msvr, CD180_MSVR_RTS))
|
|
bits |= TIOCM_RTS;
|
|
break;
|
|
case DMSET:
|
|
DTR_WRITE(csc, sp->sp_channel, ISSET(bits, TIOCM_DTR) ? 1 : 0);
|
|
if (ISSET(bits, TIOCM_RTS))
|
|
STC_WRITE(csc, STC_MSVR,
|
|
STC_READ(csc, STC_MSVR) & (~CD180_MSVR_RTS));
|
|
else
|
|
STC_WRITE(csc, STC_MSVR,
|
|
STC_READ(csc, STC_MSVR) | CD180_MSVR_RTS);
|
|
break;
|
|
case DMBIS:
|
|
if (ISSET(bits, TIOCM_DTR))
|
|
DTR_WRITE(csc, sp->sp_channel, 1);
|
|
if (ISSET(bits, TIOCM_RTS) && !ISSET(tp->t_cflag, CRTSCTS))
|
|
STC_WRITE(csc, STC_MSVR,
|
|
STC_READ(csc, STC_MSVR) & (~CD180_MSVR_RTS));
|
|
break;
|
|
case DMBIC:
|
|
if (ISSET(bits, TIOCM_DTR))
|
|
DTR_WRITE(csc, sp->sp_channel, 0);
|
|
if (ISSET(bits, TIOCM_RTS))
|
|
STC_WRITE(csc, STC_MSVR,
|
|
STC_READ(csc, STC_MSVR) | CD180_MSVR_RTS);
|
|
break;
|
|
}
|
|
|
|
splx(s);
|
|
return (bits);
|
|
}
|
|
|
|
int
|
|
stty_param(struct tty *tp, struct termios *t)
|
|
{
|
|
struct stty_softc *st = stty_cd.cd_devs[SPIF_CARD(tp->t_dev)];
|
|
struct stty_port *sp = &st->sc_port[SPIF_PORT(tp->t_dev)];
|
|
struct spif_softc *sc = sp->sp_sc;
|
|
u_int8_t rbprl, rbprh, tbprl, tbprh;
|
|
int s, opt;
|
|
|
|
if (t->c_ospeed &&
|
|
stty_compute_baud(t->c_ospeed, sc->sc_osc, &tbprl, &tbprh))
|
|
return (EINVAL);
|
|
|
|
if (t->c_ispeed &&
|
|
stty_compute_baud(t->c_ispeed, sc->sc_osc, &rbprl, &rbprh))
|
|
return (EINVAL);
|
|
|
|
s = spltty();
|
|
|
|
/* hang up line if ospeed is zero, otherwise raise DTR */
|
|
stty_modem_control(sp, TIOCM_DTR,
|
|
(t->c_ospeed == 0 ? DMBIC : DMBIS));
|
|
|
|
STC_WRITE(sc, STC_CAR, sp->sp_channel);
|
|
|
|
opt = 0;
|
|
if (ISSET(t->c_cflag, PARENB)) {
|
|
opt |= CD180_COR1_PARMODE_NORMAL;
|
|
opt |= (ISSET(t->c_cflag, PARODD) ?
|
|
CD180_COR1_ODDPAR :
|
|
CD180_COR1_EVENPAR);
|
|
}
|
|
else
|
|
opt |= CD180_COR1_PARMODE_NO;
|
|
|
|
if (!ISSET(t->c_iflag, INPCK))
|
|
opt |= CD180_COR1_IGNPAR;
|
|
|
|
if (ISSET(t->c_cflag, CSTOPB))
|
|
opt |= CD180_COR1_STOP2;
|
|
|
|
switch (t->c_cflag & CSIZE) {
|
|
case CS5:
|
|
opt |= CD180_COR1_CS5;
|
|
break;
|
|
case CS6:
|
|
opt |= CD180_COR1_CS6;
|
|
break;
|
|
case CS7:
|
|
opt |= CD180_COR1_CS7;
|
|
break;
|
|
default:
|
|
opt |= CD180_COR1_CS8;
|
|
break;
|
|
}
|
|
STC_WRITE(sc, STC_COR1, opt);
|
|
stty_write_ccr(sc, CD180_CCR_CMD_COR|CD180_CCR_CORCHG1);
|
|
|
|
opt = CD180_COR2_ETC;
|
|
if (ISSET(t->c_cflag, CRTSCTS))
|
|
opt |= CD180_COR2_CTSAE;
|
|
STC_WRITE(sc, STC_COR2, opt);
|
|
stty_write_ccr(sc, CD180_CCR_CMD_COR|CD180_CCR_CORCHG2);
|
|
|
|
STC_WRITE(sc, STC_COR3, STTY_RX_FIFO_THRESHOLD);
|
|
stty_write_ccr(sc, CD180_CCR_CMD_COR|CD180_CCR_CORCHG3);
|
|
|
|
STC_WRITE(sc, STC_SCHR1, 0x11);
|
|
STC_WRITE(sc, STC_SCHR2, 0x13);
|
|
STC_WRITE(sc, STC_SCHR3, 0x11);
|
|
STC_WRITE(sc, STC_SCHR4, 0x13);
|
|
STC_WRITE(sc, STC_RTPR, 0x12);
|
|
|
|
STC_WRITE(sc, STC_MCOR1, CD180_MCOR1_CDZD | STTY_RX_DTR_THRESHOLD);
|
|
STC_WRITE(sc, STC_MCOR2, CD180_MCOR2_CDOD);
|
|
STC_WRITE(sc, STC_MCR, 0);
|
|
|
|
if (t->c_ospeed) {
|
|
STC_WRITE(sc, STC_TBPRH, tbprh);
|
|
STC_WRITE(sc, STC_TBPRL, tbprl);
|
|
}
|
|
|
|
if (t->c_ispeed) {
|
|
STC_WRITE(sc, STC_RBPRH, rbprh);
|
|
STC_WRITE(sc, STC_RBPRL, rbprl);
|
|
}
|
|
|
|
stty_write_ccr(sc, CD180_CCR_CMD_CHAN |
|
|
CD180_CCR_CHAN_TXEN | CD180_CCR_CHAN_RXEN);
|
|
|
|
sp->sp_carrier = STC_READ(sc, STC_MSVR) & CD180_MSVR_CD;
|
|
|
|
splx(s);
|
|
return (0);
|
|
}
|
|
|
|
int
|
|
sttyread(dev_t dev, struct uio *uio, int flags)
|
|
{
|
|
struct stty_softc *sc = stty_cd.cd_devs[SPIF_CARD(dev)];
|
|
struct stty_port *sp = &sc->sc_port[SPIF_PORT(dev)];
|
|
struct tty *tp = sp->sp_tty;
|
|
|
|
return ((*linesw[tp->t_line].l_read)(tp, uio, flags));
|
|
}
|
|
|
|
int
|
|
sttywrite(dev_t dev, struct uio *uio, int flags)
|
|
{
|
|
struct stty_softc *sc = stty_cd.cd_devs[SPIF_CARD(dev)];
|
|
struct stty_port *sp = &sc->sc_port[SPIF_PORT(dev)];
|
|
struct tty *tp = sp->sp_tty;
|
|
|
|
return ((*linesw[tp->t_line].l_write)(tp, uio, flags));
|
|
}
|
|
|
|
struct tty *
|
|
sttytty(dev_t dev)
|
|
{
|
|
struct stty_softc *sc = stty_cd.cd_devs[SPIF_CARD(dev)];
|
|
struct stty_port *sp = &sc->sc_port[SPIF_PORT(dev)];
|
|
|
|
return (sp->sp_tty);
|
|
}
|
|
|
|
int
|
|
sttystop(struct tty *tp, int flags)
|
|
{
|
|
struct stty_softc *sc = stty_cd.cd_devs[SPIF_CARD(tp->t_dev)];
|
|
struct stty_port *sp = &sc->sc_port[SPIF_PORT(tp->t_dev)];
|
|
int s;
|
|
|
|
s = spltty();
|
|
if (ISSET(tp->t_state, TS_BUSY)) {
|
|
if (!ISSET(tp->t_state, TS_TTSTOP))
|
|
SET(tp->t_state, TS_FLUSH);
|
|
SET(sp->sp_flags, STTYF_STOP);
|
|
}
|
|
splx(s);
|
|
return (0);
|
|
}
|
|
|
|
void
|
|
stty_start(struct tty *tp)
|
|
{
|
|
struct stty_softc *stc = stty_cd.cd_devs[SPIF_CARD(tp->t_dev)];
|
|
struct stty_port *sp = &stc->sc_port[SPIF_PORT(tp->t_dev)];
|
|
struct spif_softc *sc = sp->sp_sc;
|
|
int s;
|
|
|
|
s = spltty();
|
|
|
|
if (!ISSET(tp->t_state, TS_TTSTOP | TS_TIMEOUT | TS_BUSY)) {
|
|
ttwakeupwr(tp);
|
|
if (tp->t_outq.c_cc) {
|
|
sp->sp_txc = ndqb(&tp->t_outq, 0);
|
|
sp->sp_txp = tp->t_outq.c_cf;
|
|
SET(tp->t_state, TS_BUSY);
|
|
STC_WRITE(sc, STC_CAR, sp->sp_channel);
|
|
STC_WRITE(sc, STC_SRER,
|
|
STC_READ(sc, STC_SRER) | CD180_SRER_TXD);
|
|
}
|
|
}
|
|
|
|
splx(s);
|
|
}
|
|
|
|
int
|
|
spifstcintr_rxexception(struct spif_softc *sc, int *needsoftp)
|
|
{
|
|
struct stty_port *sp;
|
|
u_int8_t channel, *ptr;
|
|
|
|
channel = CD180_GSCR_CHANNEL(STC_READ(sc, STC_GSCR1));
|
|
sp = &sc->sc_ttys->sc_port[channel];
|
|
ptr = sp->sp_rput;
|
|
*ptr++ = STC_READ(sc, STC_RCSR);
|
|
*ptr++ = STC_READ(sc, STC_RDR);
|
|
if (ptr == sp->sp_rend)
|
|
ptr = sp->sp_rbuf;
|
|
if (ptr == sp->sp_rget) {
|
|
if (ptr == sp->sp_rbuf)
|
|
ptr = sp->sp_rend;
|
|
ptr -= 2;
|
|
SET(sp->sp_flags, STTYF_RING_OVERFLOW);
|
|
}
|
|
STC_WRITE(sc, STC_EOSRR, 0);
|
|
*needsoftp = 1;
|
|
sp->sp_rput = ptr;
|
|
return (1);
|
|
}
|
|
|
|
int
|
|
spifstcintr_rx(struct spif_softc *sc, int *needsoftp)
|
|
{
|
|
struct stty_port *sp;
|
|
u_int8_t channel, *ptr, cnt, rcsr;
|
|
int i;
|
|
|
|
channel = CD180_GSCR_CHANNEL(STC_READ(sc, STC_GSCR1));
|
|
sp = &sc->sc_ttys->sc_port[channel];
|
|
ptr = sp->sp_rput;
|
|
cnt = STC_READ(sc, STC_RDCR);
|
|
for (i = 0; i < cnt; i++) {
|
|
*ptr++ = 0;
|
|
rcsr = STC_READ(sc, STC_RCSR);
|
|
*ptr++ = STC_READ(sc, STC_RDR);
|
|
if (ptr == sp->sp_rend)
|
|
ptr = sp->sp_rbuf;
|
|
if (ptr == sp->sp_rget) {
|
|
if (ptr == sp->sp_rbuf)
|
|
ptr = sp->sp_rend;
|
|
ptr -= 2;
|
|
SET(sp->sp_flags, STTYF_RING_OVERFLOW);
|
|
break;
|
|
}
|
|
}
|
|
STC_WRITE(sc, STC_EOSRR, 0);
|
|
if (cnt) {
|
|
*needsoftp = 1;
|
|
sp->sp_rput = ptr;
|
|
}
|
|
return (1);
|
|
}
|
|
|
|
int
|
|
spifstcintr_tx(struct spif_softc *sc, int *needsoftp)
|
|
{
|
|
struct stty_port *sp;
|
|
u_int8_t channel, ch;
|
|
int cnt = 0;
|
|
|
|
channel = CD180_GSCR_CHANNEL(STC_READ(sc, STC_GSCR1));
|
|
sp = &sc->sc_ttys->sc_port[channel];
|
|
if (!ISSET(sp->sp_flags, STTYF_STOP)) {
|
|
if (ISSET(sp->sp_flags, STTYF_SET_BREAK)) {
|
|
STC_WRITE(sc, STC_TDR, 0);
|
|
STC_WRITE(sc, STC_TDR, 0x81);
|
|
CLR(sp->sp_flags, STTYF_SET_BREAK);
|
|
cnt += 2;
|
|
}
|
|
if (ISSET(sp->sp_flags, STTYF_CLR_BREAK)) {
|
|
STC_WRITE(sc, STC_TDR, 0);
|
|
STC_WRITE(sc, STC_TDR, 0x83);
|
|
CLR(sp->sp_flags, STTYF_CLR_BREAK);
|
|
cnt += 2;
|
|
}
|
|
|
|
while (sp->sp_txc > 0 && cnt < (CD180_TX_FIFO_SIZE-1)) {
|
|
ch = *sp->sp_txp;
|
|
sp->sp_txc--;
|
|
sp->sp_txp++;
|
|
|
|
if (ch == 0) {
|
|
STC_WRITE(sc, STC_TDR, ch);
|
|
cnt++;
|
|
}
|
|
STC_WRITE(sc, STC_TDR, ch);
|
|
cnt++;
|
|
}
|
|
}
|
|
|
|
if (sp->sp_txc == 0 ||
|
|
ISSET(sp->sp_flags, STTYF_STOP)) {
|
|
STC_WRITE(sc, STC_SRER, STC_READ(sc, STC_SRER) &
|
|
(~CD180_SRER_TXD));
|
|
CLR(sp->sp_flags, STTYF_STOP);
|
|
SET(sp->sp_flags, STTYF_DONE);
|
|
*needsoftp = 1;
|
|
}
|
|
|
|
STC_WRITE(sc, STC_EOSRR, 0);
|
|
|
|
return (1);
|
|
}
|
|
|
|
int
|
|
spifstcintr_mx(struct spif_softc *sc, int *needsoftp)
|
|
{
|
|
struct stty_port *sp;
|
|
u_int8_t channel, mcr;
|
|
|
|
channel = CD180_GSCR_CHANNEL(STC_READ(sc, STC_GSCR1));
|
|
sp = &sc->sc_ttys->sc_port[channel];
|
|
mcr = STC_READ(sc, STC_MCR);
|
|
if (mcr & CD180_MCR_CD) {
|
|
SET(sp->sp_flags, STTYF_CDCHG);
|
|
*needsoftp = 1;
|
|
}
|
|
STC_WRITE(sc, STC_MCR, 0);
|
|
STC_WRITE(sc, STC_EOSRR, 0);
|
|
return (1);
|
|
}
|
|
|
|
int
|
|
spifstcintr(void *vsc)
|
|
{
|
|
struct spif_softc *sc = (struct spif_softc *)vsc;
|
|
int needsoft = 0, r = 0, i;
|
|
u_int8_t ar;
|
|
|
|
for (i = 0; i < 8; i++) {
|
|
ar = ISTC_READ(sc, STC_RRAR) & CD180_GSVR_IMASK;
|
|
if (ar == CD180_GSVR_RXGOOD)
|
|
r |= spifstcintr_rx(sc, &needsoft);
|
|
else if (ar == CD180_GSVR_RXEXCEPTION)
|
|
r |= spifstcintr_rxexception(sc, &needsoft);
|
|
}
|
|
|
|
for (i = 0; i < 8; i++) {
|
|
ar = ISTC_READ(sc, STC_TRAR) & CD180_GSVR_IMASK;
|
|
if (ar == CD180_GSVR_TXDATA)
|
|
r |= spifstcintr_tx(sc, &needsoft);
|
|
}
|
|
|
|
for (i = 0; i < 8; i++) {
|
|
ar = ISTC_READ(sc, STC_MRAR) & CD180_GSVR_IMASK;
|
|
if (ar == CD180_GSVR_STATCHG)
|
|
r |= spifstcintr_mx(sc, &needsoft);
|
|
}
|
|
|
|
if (needsoft)
|
|
softintr_schedule(sc->sc_softih);
|
|
return (r);
|
|
}
|
|
|
|
void
|
|
spifsoftintr(void *vsc)
|
|
{
|
|
struct spif_softc *sc = (struct spif_softc *)vsc;
|
|
struct stty_softc *stc = sc->sc_ttys;
|
|
int r = 0, i, data, s, flags;
|
|
u_int8_t stat, msvr;
|
|
struct stty_port *sp;
|
|
struct tty *tp;
|
|
|
|
if (stc != NULL) {
|
|
for (i = 0; i < stc->sc_nports; i++) {
|
|
sp = &stc->sc_port[i];
|
|
tp = sp->sp_tty;
|
|
|
|
if (!ISSET(tp->t_state, TS_ISOPEN))
|
|
continue;
|
|
|
|
while (sp->sp_rget != sp->sp_rput) {
|
|
stat = sp->sp_rget[0];
|
|
data = sp->sp_rget[1];
|
|
sp->sp_rget += 2;
|
|
if (sp->sp_rget == sp->sp_rend)
|
|
sp->sp_rget = sp->sp_rbuf;
|
|
|
|
if (stat & (CD180_RCSR_BE | CD180_RCSR_FE))
|
|
data |= TTY_FE;
|
|
|
|
if (stat & CD180_RCSR_PE)
|
|
data |= TTY_PE;
|
|
|
|
(*linesw[tp->t_line].l_rint)(data, tp);
|
|
r = 1;
|
|
}
|
|
|
|
s = splhigh();
|
|
flags = sp->sp_flags;
|
|
CLR(sp->sp_flags, STTYF_DONE | STTYF_CDCHG |
|
|
STTYF_RING_OVERFLOW);
|
|
splx(s);
|
|
|
|
if (ISSET(flags, STTYF_CDCHG)) {
|
|
s = spltty();
|
|
STC_WRITE(sc, STC_CAR, i);
|
|
msvr = STC_READ(sc, STC_MSVR);
|
|
splx(s);
|
|
|
|
sp->sp_carrier = msvr & CD180_MSVR_CD;
|
|
(*linesw[tp->t_line].l_modem)(tp,
|
|
sp->sp_carrier);
|
|
r = 1;
|
|
}
|
|
|
|
if (ISSET(flags, STTYF_RING_OVERFLOW)) {
|
|
log(LOG_WARNING, "%s-%x: ring overflow\n",
|
|
stc->sc_dev.dv_xname, i);
|
|
r = 1;
|
|
}
|
|
|
|
if (ISSET(flags, STTYF_DONE)) {
|
|
ndflush(&tp->t_outq,
|
|
sp->sp_txp - tp->t_outq.c_cf);
|
|
CLR(tp->t_state, TS_BUSY);
|
|
(*linesw[tp->t_line].l_start)(tp);
|
|
r = 1;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
void
|
|
stty_write_ccr(struct spif_softc *sc, u_int8_t val)
|
|
{
|
|
int tries = 100000;
|
|
|
|
while (STC_READ(sc, STC_CCR) && tries--)
|
|
/*EMPTY*/;
|
|
if (tries == 0)
|
|
printf("%s: ccr timeout\n", sc->sc_dev.dv_xname);
|
|
STC_WRITE(sc, STC_CCR, val);
|
|
}
|
|
|
|
int
|
|
stty_compute_baud(speed_t speed, int clock, u_int8_t *bprlp, u_int8_t *bprhp)
|
|
{
|
|
u_int32_t rate;
|
|
|
|
rate = (2 * clock) / (16 * speed);
|
|
if (rate & 1)
|
|
rate = (rate >> 1) + 1;
|
|
else
|
|
rate = rate >> 1;
|
|
|
|
if (rate > 0xffff || rate == 0)
|
|
return (1);
|
|
|
|
*bprlp = rate & 0xff;
|
|
*bprhp = (rate >> 8) & 0xff;
|
|
return (0);
|
|
}
|
|
|
|
int
|
|
sbppmatch(struct device *parent, void *vcf, void *aux)
|
|
{
|
|
struct spif_softc *sc = (struct spif_softc *)parent;
|
|
|
|
return (aux == sbppmatch && sc->sc_bpps == NULL);
|
|
}
|
|
|
|
void
|
|
sbppattach(struct device *parent, struct device *dev, void *aux)
|
|
{
|
|
struct spif_softc *sc = (struct spif_softc *)parent;
|
|
struct sbpp_softc *psc = (struct sbpp_softc *)dev;
|
|
int port;
|
|
|
|
sc->sc_bpps = psc;
|
|
|
|
for (port = 0; port < sc->sc_npar; port++) {
|
|
}
|
|
|
|
psc->sc_nports = port;
|
|
printf(": %d port%s\n", port, port == 1 ? "" : "s");
|
|
}
|
|
|
|
int
|
|
sbppopen(dev_t dev, int flags, int mode, struct proc *p)
|
|
{
|
|
return (ENXIO);
|
|
}
|
|
|
|
int
|
|
sbppclose(dev_t dev, int flags, int mode, struct proc *p)
|
|
{
|
|
return (ENXIO);
|
|
}
|
|
|
|
int
|
|
spifppcintr(void *v)
|
|
{
|
|
return (0);
|
|
}
|
|
|
|
int
|
|
sbppread(dev_t dev, struct uio *uio, int flags)
|
|
{
|
|
return (sbpp_rw(dev, uio));
|
|
}
|
|
|
|
int
|
|
sbppwrite(dev_t dev, struct uio *uio, int flags)
|
|
{
|
|
return (sbpp_rw(dev, uio));
|
|
}
|
|
|
|
int
|
|
sbpp_rw(dev_t dev, struct uio *uio)
|
|
{
|
|
return (ENXIO);
|
|
}
|
|
|
|
int
|
|
sbppkqfilter(dev_t dev, struct knote *kn)
|
|
{
|
|
return (seltrue_kqfilter(dev, kn));
|
|
}
|
|
|
|
int
|
|
sbppioctl(dev_t dev, u_long cmd, caddr_t data, int flags, struct proc *p)
|
|
{
|
|
int error;
|
|
|
|
error = ENOTTY;
|
|
|
|
return (error);
|
|
}
|