102 lines
4.5 KiB
C
102 lines
4.5 KiB
C
/* $OpenBSD: mc6845.h,v 1.5 2005/12/12 12:35:49 mickey Exp $ */
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/*
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* Copyright (c) 1992, 1995 Hellmuth Michaelis and Joerg Wunsch.
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* Copyright (c) 1992, 1993 Brian Dunford-Shore.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by
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* Hellmuth Michaelis, Brian Dunford-Shore and Joerg Wunsch.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#define MONO_BASE 0x3B4 /* crtc index register address mono */
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#define CGA_BASE 0x3D4 /* crtc index register address color */
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#define CRTC_ADDR 0x00 /* index register */
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#define CRTC_HTOTAL 0x00 /* horizontal total */
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#define CRTC_HDISPLE 0x01 /* horizontal display end */
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#define CRTC_HBLANKS 0x02 /* horizontal blank start */
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#define CRTC_HBLANKE 0x03 /* horizontal blank end */
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#define CRTC_HSYNCS 0x04 /* horizontal sync start */
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#define CRTC_HSYNCE 0x05 /* horizontal sync end */
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#define CRTC_VTOTAL 0x06 /* vertical total */
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#define CRTC_OVERFLL 0x07 /* overflow low */
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#define CRTC_IROWADDR 0x08 /* initial row address */
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#define CRTC_MAXROW 0x09 /* maximum row address */
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#define CRTC_CURSTART 0x0A /* cursor start row address */
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#define CRTC_CUREND 0x0B /* cursor end row address */
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#define CRTC_STARTADRH 0x0C /* linear start address mid */
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#define CRTC_STARTADRL 0x0D /* linear start address low */
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#define CRTC_CURSORH 0x0E /* cursor address mid */
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#define CRTC_CURSORL 0x0F /* cursor address low */
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#define CRTC_VSYNCS 0x10 /* vertical sync start */
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#define CRTC_VSYNCE 0x11 /* vertical sync end */
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#define CRTC_VDE 0x12 /* vertical display end */
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#define CRTC_OFFSET 0x13 /* row offset */
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#define CRTC_ULOC 0x14 /* underline row address */
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#define CRTC_VBSTART 0x15 /* vertical blank start */
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#define CRTC_VBEND 0x16 /* vertical blank end */
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#define CRTC_MODE 0x17 /* CRTC mode register */
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#define CRTC_SPLITL 0x18 /* split screen start low */
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/* start of ET4000 extensions */
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#define CRTC_RASCAS 0x32 /* ras/cas configuration */
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#define CRTC_EXTSTART 0x33 /* extended start address */
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#define CRTC_COMPAT6845 0x34 /* 6845 compatibility control */
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#define CRTC_OVFLHIGH 0x35 /* overflow high */
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#define CRTC_SYSCONF1 0x36 /* video system configuration 1 */
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#define CRTC_SYSCONF2 0x36 /* video system configuration 2 */
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/* start of WD/Paradise extensions */
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#define CRTC_PR10 0x29 /* r/w unlocking */
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#define CRTC_PR11 0x2A /* ega switches */
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#define CRTC_PR12 0x2B /* scratch pad */
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#define CRTC_PR13 0x2C /* interlace h/2 start */
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#define CRTC_PR14 0x2D /* interlace h/2 end */
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#define CRTC_PR15 0x2E /* misc control #1 */
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#define CRTC_PR16 0x2F /* misc control #2 */
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#define CRTC_PR17 0x30 /* misc control #3 */
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/* 0x31 .. 0x3f reserved */
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/* Video 7 */
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#define CRTC_V7ID 0x1f /* identification register */
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/* Trident */
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#define CRTC_MTEST 0x1e /* module test register */
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#define CRTC_SOFTPROG 0x1f /* software programming */
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#define CRTC_LATCHRDB 0x22 /* latch read back register */
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#define CRTC_ATTRSRDB 0x24 /* attribute state read back register*/
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#define CRTC_ATTRIRDB 0x26 /* attribute index read back register*/
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#define CRTC_HOSTAR 0x27 /* high order start address register */
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