836 lines
30 KiB
C
836 lines
30 KiB
C
/*
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* Copyright 2021 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "dccg.h"
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#include "clk_mgr_internal.h"
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#include "dcn32/dcn32_clk_mgr_smu_msg.h"
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#include "dcn20/dcn20_clk_mgr.h"
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#include "dce100/dce_clk_mgr.h"
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#include "dcn31/dcn31_clk_mgr.h"
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#include "reg_helper.h"
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#include "core_types.h"
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#include "dm_helpers.h"
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#include "dc_link_dp.h"
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#include "atomfirmware.h"
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#include "smu13_driver_if.h"
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#include "dcn/dcn_3_2_0_offset.h"
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#include "dcn/dcn_3_2_0_sh_mask.h"
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#include "dcn32/dcn32_clk_mgr.h"
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#include "dml/dcn32/dcn32_fpu.h"
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#define DCN_BASE__INST0_SEG1 0x000000C0
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#define mmCLK1_CLK_PLL_REQ 0x16E37
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#define mmCLK1_CLK0_DFS_CNTL 0x16E69
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#define mmCLK1_CLK1_DFS_CNTL 0x16E6C
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#define mmCLK1_CLK2_DFS_CNTL 0x16E6F
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#define mmCLK1_CLK3_DFS_CNTL 0x16E72
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#define mmCLK1_CLK4_DFS_CNTL 0x16E75
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#define CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001ffUL
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#define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000f000UL
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#define CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xffff0000UL
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#define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x00000000
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#define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0x0000000c
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#define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x00000010
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#define mmCLK01_CLK0_CLK_PLL_REQ 0x16E37
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#define mmCLK01_CLK0_CLK0_DFS_CNTL 0x16E64
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#define mmCLK01_CLK0_CLK1_DFS_CNTL 0x16E67
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#define mmCLK01_CLK0_CLK2_DFS_CNTL 0x16E6A
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#define mmCLK01_CLK0_CLK3_DFS_CNTL 0x16E6D
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#define mmCLK01_CLK0_CLK4_DFS_CNTL 0x16E70
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#define CLK0_CLK_PLL_REQ__FbMult_int_MASK 0x000001ffL
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#define CLK0_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000f000L
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#define CLK0_CLK_PLL_REQ__FbMult_frac_MASK 0xffff0000L
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#define CLK0_CLK_PLL_REQ__FbMult_int__SHIFT 0x00000000
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#define CLK0_CLK_PLL_REQ__PllSpineDiv__SHIFT 0x0000000c
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#define CLK0_CLK_PLL_REQ__FbMult_frac__SHIFT 0x00000010
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#undef FN
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#define FN(reg_name, field_name) \
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clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
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#define REG(reg) \
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(clk_mgr->regs->reg)
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#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
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#define BASE(seg) BASE_INNER(seg)
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#define SR(reg_name)\
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.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
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reg ## reg_name
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#define CLK_SR_DCN32(reg_name)\
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.reg_name = mm ## reg_name
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static const struct clk_mgr_registers clk_mgr_regs_dcn32 = {
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CLK_REG_LIST_DCN32()
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};
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static const struct clk_mgr_shift clk_mgr_shift_dcn32 = {
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CLK_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
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};
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static const struct clk_mgr_mask clk_mgr_mask_dcn32 = {
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CLK_COMMON_MASK_SH_LIST_DCN32(_MASK)
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};
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#define CLK_SR_DCN321(reg_name, block, inst)\
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.reg_name = mm ## block ## _ ## reg_name
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static const struct clk_mgr_registers clk_mgr_regs_dcn321 = {
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CLK_REG_LIST_DCN321()
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};
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static const struct clk_mgr_shift clk_mgr_shift_dcn321 = {
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CLK_COMMON_MASK_SH_LIST_DCN321(__SHIFT)
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};
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static const struct clk_mgr_mask clk_mgr_mask_dcn321 = {
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CLK_COMMON_MASK_SH_LIST_DCN321(_MASK)
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};
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/* Query SMU for all clock states for a particular clock */
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static void dcn32_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, unsigned int *entry_0,
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unsigned int *num_levels)
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{
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unsigned int i;
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char *entry_i = (char *)entry_0;
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uint32_t ret = dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, 0xFF);
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if (ret & (1 << 31))
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/* fine-grained, only min and max */
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*num_levels = 2;
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else
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/* discrete, a number of fixed states */
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/* will set num_levels to 0 on failure */
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*num_levels = ret & 0xFF;
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/* if the initial message failed, num_levels will be 0 */
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for (i = 0; i < *num_levels; i++) {
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*((unsigned int *)entry_i) = (dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, i) & 0xFFFF);
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entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]);
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}
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}
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static void dcn32_build_wm_range_table(struct clk_mgr_internal *clk_mgr)
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{
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DC_FP_START();
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dcn32_build_wm_range_table_fpu(clk_mgr);
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DC_FP_END();
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}
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void dcn32_init_clocks(struct clk_mgr *clk_mgr_base)
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{
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struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
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unsigned int num_levels;
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struct clk_limit_num_entries *num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entries_per_clk;
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unsigned int i;
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memset(&(clk_mgr_base->clks), 0, sizeof(struct dc_clocks));
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clk_mgr_base->clks.p_state_change_support = true;
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clk_mgr_base->clks.prev_p_state_change_support = true;
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clk_mgr_base->clks.fclk_prev_p_state_change_support = true;
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clk_mgr->smu_present = false;
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clk_mgr->dpm_present = false;
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if (!clk_mgr_base->bw_params)
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return;
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if (!clk_mgr_base->force_smu_not_present && dcn30_smu_get_smu_version(clk_mgr, &clk_mgr->smu_ver))
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clk_mgr->smu_present = true;
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if (!clk_mgr->smu_present)
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return;
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dcn30_smu_check_driver_if_version(clk_mgr);
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dcn30_smu_check_msg_header_version(clk_mgr);
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/* DCFCLK */
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dcn32_init_single_clock(clk_mgr, PPCLK_DCFCLK,
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&clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz,
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&num_entries_per_clk->num_dcfclk_levels);
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/* SOCCLK */
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dcn32_init_single_clock(clk_mgr, PPCLK_SOCCLK,
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&clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz,
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&num_entries_per_clk->num_socclk_levels);
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/* DTBCLK */
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if (!clk_mgr->base.ctx->dc->debug.disable_dtb_ref_clk_switch)
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dcn32_init_single_clock(clk_mgr, PPCLK_DTBCLK,
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&clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz,
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&num_entries_per_clk->num_dtbclk_levels);
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/* DISPCLK */
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dcn32_init_single_clock(clk_mgr, PPCLK_DISPCLK,
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&clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz,
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&num_entries_per_clk->num_dispclk_levels);
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num_levels = num_entries_per_clk->num_dispclk_levels;
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if (num_entries_per_clk->num_dcfclk_levels &&
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num_entries_per_clk->num_dtbclk_levels &&
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num_entries_per_clk->num_dispclk_levels)
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clk_mgr->dpm_present = true;
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if (clk_mgr_base->ctx->dc->debug.min_disp_clk_khz) {
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for (i = 0; i < num_levels; i++)
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if (clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz
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< khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz))
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clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz
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= khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz);
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}
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for (i = 0; i < num_levels; i++)
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if (clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz > 1950)
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clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz = 1950;
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if (clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz) {
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for (i = 0; i < num_levels; i++)
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if (clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz
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< khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz))
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clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz
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= khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz);
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}
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/* Get UCLK, update bounding box */
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clk_mgr_base->funcs->get_memclk_states_from_smu(clk_mgr_base);
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DC_FP_START();
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/* WM range table */
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dcn32_build_wm_range_table(clk_mgr);
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DC_FP_END();
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}
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static void dcn32_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr,
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struct dc_state *context,
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int ref_dtbclk_khz)
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{
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struct dccg *dccg = clk_mgr->dccg;
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uint32_t tg_mask = 0;
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int i;
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for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
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struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
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struct dtbclk_dto_params dto_params = {0};
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/* use mask to program DTO once per tg */
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if (pipe_ctx->stream_res.tg &&
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!(tg_mask & (1 << pipe_ctx->stream_res.tg->inst))) {
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tg_mask |= (1 << pipe_ctx->stream_res.tg->inst);
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dto_params.otg_inst = pipe_ctx->stream_res.tg->inst;
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dto_params.ref_dtbclk_khz = ref_dtbclk_khz;
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if (is_dp_128b_132b_signal(pipe_ctx)) {
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dto_params.pixclk_khz = pipe_ctx->stream->phy_pix_clk;
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if (pipe_ctx->stream_res.audio != NULL)
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dto_params.req_audio_dtbclk_khz = 24000;
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}
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if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
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dto_params.is_hdmi = true;
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dccg->funcs->set_dtbclk_dto(clk_mgr->dccg, &dto_params);
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//dccg->funcs->set_audio_dtbclk_dto(clk_mgr->dccg, &dto_params);
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}
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}
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}
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/* Since DPPCLK request to PMFW needs to be exact (due to DPP DTO programming),
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* update DPPCLK to be the exact frequency that will be set after the DPPCLK
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* divider is updated. This will prevent rounding issues that could cause DPP
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* refclk and DPP DTO to not match up.
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*/
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static void dcn32_update_dppclk_dispclk_freq(struct clk_mgr_internal *clk_mgr, struct dc_clocks *new_clocks)
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{
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int dpp_divider = 0;
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int disp_divider = 0;
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if (new_clocks->dppclk_khz) {
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dpp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
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* clk_mgr->base.dentist_vco_freq_khz / new_clocks->dppclk_khz;
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new_clocks->dppclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / dpp_divider;
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}
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if (new_clocks->dispclk_khz > 0) {
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disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
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* clk_mgr->base.dentist_vco_freq_khz / new_clocks->dispclk_khz;
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new_clocks->dispclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / disp_divider;
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}
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}
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static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
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struct dc_state *context,
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bool safe_to_lower)
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{
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struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
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struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
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struct dc *dc = clk_mgr_base->ctx->dc;
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int display_count;
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bool update_dppclk = false;
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bool update_dispclk = false;
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bool enter_display_off = false;
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bool dpp_clock_lowered = false;
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struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
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bool force_reset = false;
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bool update_uclk = false, update_fclk = false;
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bool p_state_change_support;
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bool fclk_p_state_change_support;
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int total_plane_count;
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if (dc->work_arounds.skip_clock_update)
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return;
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if (clk_mgr_base->clks.dispclk_khz == 0 ||
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(dc->debug.force_clock_mode & 0x1)) {
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/* This is from resume or boot up, if forced_clock cfg option used,
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* we bypass program dispclk and DPPCLK, but need set them for S3.
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*/
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force_reset = true;
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dcn2_read_clocks_from_hw_dentist(clk_mgr_base);
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/* Force_clock_mode 0x1: force reset the clock even it is the same clock
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* as long as it is in Passive level.
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*/
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}
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display_count = clk_mgr_helper_get_active_display_cnt(dc, context);
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if (display_count == 0)
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enter_display_off = true;
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if (clk_mgr->smu_present) {
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if (enter_display_off == safe_to_lower)
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dcn30_smu_set_num_of_displays(clk_mgr, display_count);
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clk_mgr_base->clks.fclk_prev_p_state_change_support = clk_mgr_base->clks.fclk_p_state_change_support;
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total_plane_count = clk_mgr_helper_get_active_plane_cnt(dc, context);
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fclk_p_state_change_support = new_clocks->fclk_p_state_change_support || (total_plane_count == 0);
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if (should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_p_state_change_support)) {
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clk_mgr_base->clks.fclk_p_state_change_support = fclk_p_state_change_support;
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/* To enable FCLK P-state switching, send FCLK_PSTATE_SUPPORTED message to PMFW */
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if (clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21 && clk_mgr_base->clks.fclk_p_state_change_support) {
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/* Handle the code for sending a message to PMFW that FCLK P-state change is supported */
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dcn32_smu_send_fclk_pstate_message(clk_mgr, FCLK_PSTATE_SUPPORTED);
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}
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}
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if (dc->debug.force_min_dcfclk_mhz > 0)
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new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?
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new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000);
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if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
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clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
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dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCFCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz));
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}
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if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
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clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
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dcn30_smu_set_min_deep_sleep_dcef_clk(clk_mgr, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_sleep_khz));
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}
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if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz))
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/* We don't actually care about socclk, don't notify SMU of hard min */
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clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz;
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clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support;
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clk_mgr_base->clks.prev_num_ways = clk_mgr_base->clks.num_ways;
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if (clk_mgr_base->clks.num_ways != new_clocks->num_ways &&
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clk_mgr_base->clks.num_ways < new_clocks->num_ways) {
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clk_mgr_base->clks.num_ways = new_clocks->num_ways;
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dcn32_smu_send_cab_for_uclk_message(clk_mgr, clk_mgr_base->clks.num_ways);
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}
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p_state_change_support = new_clocks->p_state_change_support || (total_plane_count == 0);
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if (should_update_pstate_support(safe_to_lower, p_state_change_support, clk_mgr_base->clks.p_state_change_support)) {
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|
clk_mgr_base->clks.p_state_change_support = p_state_change_support;
|
|
|
|
/* to disable P-State switching, set UCLK min = max */
|
|
if (!clk_mgr_base->clks.p_state_change_support)
|
|
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
|
|
clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_memclk_levels - 1].memclk_mhz);
|
|
}
|
|
|
|
/* Always update saved value, even if new value not set due to P-State switching unsupported. Also check safe_to_lower for FCLK */
|
|
if (safe_to_lower && (clk_mgr_base->clks.fclk_p_state_change_support != clk_mgr_base->clks.fclk_prev_p_state_change_support)) {
|
|
update_fclk = true;
|
|
}
|
|
|
|
if (clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21 && !clk_mgr_base->clks.fclk_p_state_change_support && update_fclk) {
|
|
/* Handle code for sending a message to PMFW that FCLK P-state change is not supported */
|
|
dcn32_smu_send_fclk_pstate_message(clk_mgr, FCLK_PSTATE_NOTSUPPORTED);
|
|
}
|
|
|
|
/* Always update saved value, even if new value not set due to P-State switching unsupported */
|
|
if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) {
|
|
clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz;
|
|
update_uclk = true;
|
|
}
|
|
|
|
/* set UCLK to requested value if P-State switching is supported, or to re-enable P-State switching */
|
|
if (clk_mgr_base->clks.p_state_change_support &&
|
|
(update_uclk || !clk_mgr_base->clks.prev_p_state_change_support))
|
|
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
|
|
|
|
if (clk_mgr_base->clks.num_ways != new_clocks->num_ways &&
|
|
clk_mgr_base->clks.num_ways > new_clocks->num_ways) {
|
|
clk_mgr_base->clks.num_ways = new_clocks->num_ways;
|
|
dcn32_smu_send_cab_for_uclk_message(clk_mgr, clk_mgr_base->clks.num_ways);
|
|
}
|
|
}
|
|
|
|
dcn32_update_dppclk_dispclk_freq(clk_mgr, new_clocks);
|
|
if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) {
|
|
if (clk_mgr_base->clks.dppclk_khz > new_clocks->dppclk_khz)
|
|
dpp_clock_lowered = true;
|
|
|
|
clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
|
|
|
|
if (clk_mgr->smu_present && !dpp_clock_lowered)
|
|
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DPPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz));
|
|
|
|
update_dppclk = true;
|
|
}
|
|
|
|
if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
|
|
clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
|
|
|
|
if (clk_mgr->smu_present)
|
|
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dispclk_khz));
|
|
|
|
update_dispclk = true;
|
|
}
|
|
|
|
if (!new_clocks->dtbclk_en) {
|
|
new_clocks->ref_dtbclk_khz = clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz * 1000;
|
|
}
|
|
|
|
/* clock limits are received with MHz precision, divide by 1000 to prevent setting clocks at every call */
|
|
if (!dc->debug.disable_dtb_ref_clk_switch &&
|
|
should_set_clock(safe_to_lower, new_clocks->ref_dtbclk_khz / 1000, clk_mgr_base->clks.ref_dtbclk_khz / 1000)) {
|
|
/* DCCG requires KHz precision for DTBCLK */
|
|
clk_mgr_base->clks.ref_dtbclk_khz =
|
|
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DTBCLK, khz_to_mhz_ceil(new_clocks->ref_dtbclk_khz));
|
|
|
|
dcn32_update_clocks_update_dtb_dto(clk_mgr, context, clk_mgr_base->clks.ref_dtbclk_khz);
|
|
}
|
|
|
|
if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {
|
|
if (dpp_clock_lowered) {
|
|
/* if clock is being lowered, increase DTO before lowering refclk */
|
|
dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
|
|
dcn20_update_clocks_update_dentist(clk_mgr, context);
|
|
if (clk_mgr->smu_present)
|
|
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DPPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz));
|
|
} else {
|
|
/* if clock is being raised, increase refclk before lowering DTO */
|
|
if (update_dppclk || update_dispclk)
|
|
dcn20_update_clocks_update_dentist(clk_mgr, context);
|
|
/* There is a check inside dcn20_update_clocks_update_dpp_dto which ensures
|
|
* that we do not lower dto when it is not safe to lower. We do not need to
|
|
* compare the current and new dppclk before calling this function.
|
|
*/
|
|
dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
|
|
}
|
|
}
|
|
|
|
if (update_dispclk && dmcu && dmcu->funcs->is_dmcu_initialized(dmcu))
|
|
/*update dmcu for wait_loop count*/
|
|
dmcu->funcs->set_psr_wait_loop(dmcu,
|
|
clk_mgr_base->clks.dispclk_khz / 1000 / 7);
|
|
}
|
|
|
|
static uint32_t dcn32_get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
|
|
{
|
|
struct fixed31_32 pll_req;
|
|
uint32_t pll_req_reg = 0;
|
|
|
|
/* get FbMult value */
|
|
if (ASICREV_IS_GC_11_0_2(clk_mgr->base.ctx->asic_id.hw_internal_rev))
|
|
pll_req_reg = REG_READ(CLK0_CLK_PLL_REQ);
|
|
else
|
|
pll_req_reg = REG_READ(CLK1_CLK_PLL_REQ);
|
|
|
|
/* set up a fixed-point number
|
|
* this works because the int part is on the right edge of the register
|
|
* and the frac part is on the left edge
|
|
*/
|
|
pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int);
|
|
pll_req.value |= pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_frac;
|
|
|
|
/* multiply by REFCLK period */
|
|
pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
|
|
|
|
return dc_fixpt_floor(pll_req);
|
|
}
|
|
|
|
static void dcn32_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
|
|
struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
|
|
{
|
|
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
|
|
uint32_t dprefclk_did = 0;
|
|
uint32_t dcfclk_did = 0;
|
|
uint32_t dtbclk_did = 0;
|
|
uint32_t dispclk_did = 0;
|
|
uint32_t dppclk_did = 0;
|
|
uint32_t target_div = 0;
|
|
|
|
if (ASICREV_IS_GC_11_0_2(clk_mgr->base.ctx->asic_id.hw_internal_rev)) {
|
|
/* DFS Slice 0 is used for DISPCLK */
|
|
dispclk_did = REG_READ(CLK0_CLK0_DFS_CNTL);
|
|
/* DFS Slice 1 is used for DPPCLK */
|
|
dppclk_did = REG_READ(CLK0_CLK1_DFS_CNTL);
|
|
/* DFS Slice 2 is used for DPREFCLK */
|
|
dprefclk_did = REG_READ(CLK0_CLK2_DFS_CNTL);
|
|
/* DFS Slice 3 is used for DCFCLK */
|
|
dcfclk_did = REG_READ(CLK0_CLK3_DFS_CNTL);
|
|
/* DFS Slice 4 is used for DTBCLK */
|
|
dtbclk_did = REG_READ(CLK0_CLK4_DFS_CNTL);
|
|
} else {
|
|
/* DFS Slice 0 is used for DISPCLK */
|
|
dispclk_did = REG_READ(CLK1_CLK0_DFS_CNTL);
|
|
/* DFS Slice 1 is used for DPPCLK */
|
|
dppclk_did = REG_READ(CLK1_CLK1_DFS_CNTL);
|
|
/* DFS Slice 2 is used for DPREFCLK */
|
|
dprefclk_did = REG_READ(CLK1_CLK2_DFS_CNTL);
|
|
/* DFS Slice 3 is used for DCFCLK */
|
|
dcfclk_did = REG_READ(CLK1_CLK3_DFS_CNTL);
|
|
/* DFS Slice 4 is used for DTBCLK */
|
|
dtbclk_did = REG_READ(CLK1_CLK4_DFS_CNTL);
|
|
}
|
|
|
|
/* Convert DISPCLK DFS Slice DID to divider*/
|
|
target_div = dentist_get_divider_from_did(dispclk_did);
|
|
//Get dispclk in khz
|
|
regs_and_bypass->dispclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
|
|
* clk_mgr->base.dentist_vco_freq_khz) / target_div;
|
|
|
|
/* Convert DISPCLK DFS Slice DID to divider*/
|
|
target_div = dentist_get_divider_from_did(dppclk_did);
|
|
//Get dppclk in khz
|
|
regs_and_bypass->dppclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
|
|
* clk_mgr->base.dentist_vco_freq_khz) / target_div;
|
|
|
|
/* Convert DPREFCLK DFS Slice DID to divider*/
|
|
target_div = dentist_get_divider_from_did(dprefclk_did);
|
|
//Get dprefclk in khz
|
|
regs_and_bypass->dprefclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
|
|
* clk_mgr->base.dentist_vco_freq_khz) / target_div;
|
|
|
|
/* Convert DCFCLK DFS Slice DID to divider*/
|
|
target_div = dentist_get_divider_from_did(dcfclk_did);
|
|
//Get dcfclk in khz
|
|
regs_and_bypass->dcfclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
|
|
* clk_mgr->base.dentist_vco_freq_khz) / target_div;
|
|
|
|
/* Convert DTBCLK DFS Slice DID to divider*/
|
|
target_div = dentist_get_divider_from_did(dtbclk_did);
|
|
//Get dtbclk in khz
|
|
regs_and_bypass->dtbclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
|
|
* clk_mgr->base.dentist_vco_freq_khz) / target_div;
|
|
}
|
|
|
|
static void dcn32_clock_read_ss_info(struct clk_mgr_internal *clk_mgr)
|
|
{
|
|
struct dc_bios *bp = clk_mgr->base.ctx->dc_bios;
|
|
int ss_info_num = bp->funcs->get_ss_entry_number(
|
|
bp, AS_SIGNAL_TYPE_GPU_PLL);
|
|
|
|
if (ss_info_num) {
|
|
struct spread_spectrum_info info = { { 0 } };
|
|
enum bp_result result = bp->funcs->get_spread_spectrum_info(
|
|
bp, AS_SIGNAL_TYPE_GPU_PLL, 0, &info);
|
|
|
|
/* SSInfo.spreadSpectrumPercentage !=0 would be sign
|
|
* that SS is enabled
|
|
*/
|
|
if (result == BP_RESULT_OK &&
|
|
info.spread_spectrum_percentage != 0) {
|
|
clk_mgr->ss_on_dprefclk = true;
|
|
clk_mgr->dprefclk_ss_divider = info.spread_percentage_divider;
|
|
|
|
if (info.type.CENTER_MODE == 0) {
|
|
/* Currently for DP Reference clock we
|
|
* need only SS percentage for
|
|
* downspread
|
|
*/
|
|
clk_mgr->dprefclk_ss_percentage =
|
|
info.spread_spectrum_percentage;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
static void dcn32_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
|
|
{
|
|
unsigned int i;
|
|
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
|
|
WatermarksExternal_t *table = (WatermarksExternal_t *) clk_mgr->wm_range_table;
|
|
|
|
if (!clk_mgr->smu_present)
|
|
return;
|
|
|
|
if (!table)
|
|
return;
|
|
|
|
memset(table, 0, sizeof(*table));
|
|
|
|
/* collect valid ranges, place in pmfw table */
|
|
for (i = 0; i < WM_SET_COUNT; i++)
|
|
if (clk_mgr->base.bw_params->wm_table.nv_entries[i].valid) {
|
|
table->Watermarks.WatermarkRow[i].WmSetting = i;
|
|
table->Watermarks.WatermarkRow[i].Flags = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.wm_type;
|
|
}
|
|
dcn30_smu_set_dram_addr_high(clk_mgr, clk_mgr->wm_range_table_addr >> 32);
|
|
dcn30_smu_set_dram_addr_low(clk_mgr, clk_mgr->wm_range_table_addr & 0xFFFFFFFF);
|
|
dcn32_smu_transfer_wm_table_dram_2_smu(clk_mgr);
|
|
}
|
|
|
|
/* Set min memclk to minimum, either constrained by the current mode or DPM0 */
|
|
static void dcn32_set_hard_min_memclk(struct clk_mgr *clk_mgr_base, bool current_mode)
|
|
{
|
|
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
|
|
|
|
if (!clk_mgr->smu_present)
|
|
return;
|
|
|
|
if (current_mode) {
|
|
if (clk_mgr_base->clks.p_state_change_support)
|
|
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
|
|
khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
|
|
else
|
|
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
|
|
clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_memclk_levels - 1].memclk_mhz);
|
|
} else {
|
|
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
|
|
clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz);
|
|
}
|
|
}
|
|
|
|
/* Set max memclk to highest DPM value */
|
|
static void dcn32_set_hard_max_memclk(struct clk_mgr *clk_mgr_base)
|
|
{
|
|
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
|
|
|
|
if (!clk_mgr->smu_present)
|
|
return;
|
|
|
|
dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK,
|
|
clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_memclk_levels - 1].memclk_mhz);
|
|
}
|
|
|
|
/* Get current memclk states, update bounding box */
|
|
static void dcn32_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base)
|
|
{
|
|
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
|
|
struct clk_limit_num_entries *num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entries_per_clk;
|
|
unsigned int num_levels;
|
|
|
|
if (!clk_mgr->smu_present)
|
|
return;
|
|
|
|
/* Refresh memclk and fclk states */
|
|
dcn32_init_single_clock(clk_mgr, PPCLK_UCLK,
|
|
&clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz,
|
|
&num_entries_per_clk->num_memclk_levels);
|
|
|
|
/* memclk must have at least one level */
|
|
num_entries_per_clk->num_memclk_levels = num_entries_per_clk->num_memclk_levels ? num_entries_per_clk->num_memclk_levels : 1;
|
|
|
|
dcn32_init_single_clock(clk_mgr, PPCLK_FCLK,
|
|
&clk_mgr_base->bw_params->clk_table.entries[0].fclk_mhz,
|
|
&num_entries_per_clk->num_fclk_levels);
|
|
|
|
if (num_entries_per_clk->num_memclk_levels >= num_entries_per_clk->num_fclk_levels) {
|
|
num_levels = num_entries_per_clk->num_memclk_levels;
|
|
} else {
|
|
num_levels = num_entries_per_clk->num_fclk_levels;
|
|
}
|
|
|
|
clk_mgr_base->bw_params->clk_table.num_entries = num_levels ? num_levels : 1;
|
|
|
|
if (clk_mgr->dpm_present && !num_levels)
|
|
clk_mgr->dpm_present = false;
|
|
|
|
if (!clk_mgr->dpm_present)
|
|
dcn32_patch_dpm_table(clk_mgr_base->bw_params);
|
|
|
|
DC_FP_START();
|
|
/* Refresh bounding box */
|
|
clk_mgr_base->ctx->dc->res_pool->funcs->update_bw_bounding_box(
|
|
clk_mgr->base.ctx->dc, clk_mgr_base->bw_params);
|
|
DC_FP_END();
|
|
}
|
|
|
|
static bool dcn32_are_clock_states_equal(struct dc_clocks *a,
|
|
struct dc_clocks *b)
|
|
{
|
|
if (a->dispclk_khz != b->dispclk_khz)
|
|
return false;
|
|
else if (a->dppclk_khz != b->dppclk_khz)
|
|
return false;
|
|
else if (a->dcfclk_khz != b->dcfclk_khz)
|
|
return false;
|
|
else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
|
|
return false;
|
|
else if (a->dramclk_khz != b->dramclk_khz)
|
|
return false;
|
|
else if (a->p_state_change_support != b->p_state_change_support)
|
|
return false;
|
|
else if (a->fclk_p_state_change_support != b->fclk_p_state_change_support)
|
|
return false;
|
|
|
|
return true;
|
|
}
|
|
|
|
static void dcn32_enable_pme_wa(struct clk_mgr *clk_mgr_base)
|
|
{
|
|
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
|
|
|
|
if (!clk_mgr->smu_present)
|
|
return;
|
|
|
|
dcn32_smu_set_pme_workaround(clk_mgr);
|
|
}
|
|
|
|
static bool dcn32_is_smu_present(struct clk_mgr *clk_mgr_base)
|
|
{
|
|
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
|
|
return clk_mgr->smu_present;
|
|
}
|
|
|
|
|
|
static struct clk_mgr_funcs dcn32_funcs = {
|
|
.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
|
|
.get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz,
|
|
.update_clocks = dcn32_update_clocks,
|
|
.dump_clk_registers = dcn32_dump_clk_registers,
|
|
.init_clocks = dcn32_init_clocks,
|
|
.notify_wm_ranges = dcn32_notify_wm_ranges,
|
|
.set_hard_min_memclk = dcn32_set_hard_min_memclk,
|
|
.set_hard_max_memclk = dcn32_set_hard_max_memclk,
|
|
.get_memclk_states_from_smu = dcn32_get_memclk_states_from_smu,
|
|
.are_clock_states_equal = dcn32_are_clock_states_equal,
|
|
.enable_pme_wa = dcn32_enable_pme_wa,
|
|
.is_smu_present = dcn32_is_smu_present,
|
|
};
|
|
|
|
void dcn32_clk_mgr_construct(
|
|
struct dc_context *ctx,
|
|
struct clk_mgr_internal *clk_mgr,
|
|
struct pp_smu_funcs *pp_smu,
|
|
struct dccg *dccg)
|
|
{
|
|
struct clk_log_info log_info = {0};
|
|
|
|
clk_mgr->base.ctx = ctx;
|
|
clk_mgr->base.funcs = &dcn32_funcs;
|
|
if (ASICREV_IS_GC_11_0_2(clk_mgr->base.ctx->asic_id.hw_internal_rev)) {
|
|
clk_mgr->regs = &clk_mgr_regs_dcn321;
|
|
clk_mgr->clk_mgr_shift = &clk_mgr_shift_dcn321;
|
|
clk_mgr->clk_mgr_mask = &clk_mgr_mask_dcn321;
|
|
} else {
|
|
clk_mgr->regs = &clk_mgr_regs_dcn32;
|
|
clk_mgr->clk_mgr_shift = &clk_mgr_shift_dcn32;
|
|
clk_mgr->clk_mgr_mask = &clk_mgr_mask_dcn32;
|
|
}
|
|
|
|
clk_mgr->dccg = dccg;
|
|
clk_mgr->dfs_bypass_disp_clk = 0;
|
|
|
|
clk_mgr->dprefclk_ss_percentage = 0;
|
|
clk_mgr->dprefclk_ss_divider = 1000;
|
|
clk_mgr->ss_on_dprefclk = false;
|
|
clk_mgr->dfs_ref_freq_khz = 100000;
|
|
|
|
/* Changed from DCN3.2_clock_frequency doc to match
|
|
* dcn32_dump_clk_registers from 4 * dentist_vco_freq_khz /
|
|
* dprefclk DID divider
|
|
*/
|
|
clk_mgr->base.dprefclk_khz = 716666;
|
|
if (ctx->dc->debug.disable_dtb_ref_clk_switch) {
|
|
//initialize DTB ref clock value if DPM disabled
|
|
if (ctx->dce_version == DCN_VERSION_3_21)
|
|
clk_mgr->base.clks.ref_dtbclk_khz = 477800;
|
|
else
|
|
clk_mgr->base.clks.ref_dtbclk_khz = 268750;
|
|
}
|
|
|
|
|
|
/* integer part is now VCO frequency in kHz */
|
|
clk_mgr->base.dentist_vco_freq_khz = dcn32_get_vco_frequency_from_reg(clk_mgr);
|
|
|
|
/* in case we don't get a value from the register, use default */
|
|
if (clk_mgr->base.dentist_vco_freq_khz == 0)
|
|
clk_mgr->base.dentist_vco_freq_khz = 4300000; /* Updated as per HW docs */
|
|
|
|
dcn32_dump_clk_registers(&clk_mgr->base.boot_snapshot, &clk_mgr->base, &log_info);
|
|
|
|
if (ctx->dc->debug.disable_dtb_ref_clk_switch &&
|
|
clk_mgr->base.clks.ref_dtbclk_khz != clk_mgr->base.boot_snapshot.dtbclk) {
|
|
clk_mgr->base.clks.ref_dtbclk_khz = clk_mgr->base.boot_snapshot.dtbclk;
|
|
}
|
|
|
|
if (clk_mgr->base.boot_snapshot.dprefclk != 0) {
|
|
clk_mgr->base.dprefclk_khz = clk_mgr->base.boot_snapshot.dprefclk;
|
|
}
|
|
dcn32_clock_read_ss_info(clk_mgr);
|
|
|
|
clk_mgr->dfs_bypass_enabled = false;
|
|
|
|
clk_mgr->smu_present = false;
|
|
|
|
clk_mgr->base.bw_params = kzalloc(sizeof(*clk_mgr->base.bw_params), GFP_KERNEL);
|
|
|
|
/* need physical address of table to give to PMFW */
|
|
clk_mgr->wm_range_table = dm_helpers_allocate_gpu_mem(clk_mgr->base.ctx,
|
|
DC_MEM_ALLOC_TYPE_GART, sizeof(WatermarksExternal_t),
|
|
&clk_mgr->wm_range_table_addr);
|
|
}
|
|
|
|
void dcn32_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr)
|
|
{
|
|
if (clk_mgr->base.bw_params)
|
|
kfree(clk_mgr->base.bw_params);
|
|
|
|
if (clk_mgr->wm_range_table)
|
|
dm_helpers_free_gpu_mem(clk_mgr->base.ctx, DC_MEM_ALLOC_TYPE_GART,
|
|
clk_mgr->wm_range_table);
|
|
}
|
|
|