183 lines
6.4 KiB
C
183 lines
6.4 KiB
C
/*
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* Copyright 2015 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DC_HW_SEQUENCER_PRIVATE_H__
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#define __DC_HW_SEQUENCER_PRIVATE_H__
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#include "dc_types.h"
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enum pipe_gating_control {
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PIPE_GATING_CONTROL_DISABLE = 0,
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PIPE_GATING_CONTROL_ENABLE,
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PIPE_GATING_CONTROL_INIT
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};
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struct dce_hwseq_wa {
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bool blnd_crtc_trigger;
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bool DEGVIDCN10_253;
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bool false_optc_underflow;
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bool DEGVIDCN10_254;
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bool DEGVIDCN21;
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bool disallow_self_refresh_during_multi_plane_transition;
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bool dp_hpo_and_otg_sequence;
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bool wait_hubpret_read_start_during_mpo_transition;
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};
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struct hwseq_wa_state {
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bool DEGVIDCN10_253_applied;
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bool disallow_self_refresh_during_multi_plane_transition_applied;
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unsigned int disallow_self_refresh_during_multi_plane_transition_applied_on_frame;
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};
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struct pipe_ctx;
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struct dc_state;
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struct dc_stream_status;
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struct dc_writeback_info;
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struct dchub_init_data;
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struct dc_static_screen_params;
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struct resource_pool;
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struct resource_context;
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struct stream_resource;
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struct dc_phy_addr_space_config;
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struct dc_virtual_addr_space_config;
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struct hubp;
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struct dpp;
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struct dce_hwseq;
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struct timing_generator;
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struct tg_color;
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struct output_pixel_processor;
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struct mpcc_blnd_cfg;
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struct hwseq_private_funcs {
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void (*disable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
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void (*enable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
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void (*init_pipes)(struct dc *dc, struct dc_state *context);
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void (*reset_hw_ctx_wrap)(struct dc *dc, struct dc_state *context);
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void (*update_plane_addr)(const struct dc *dc,
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struct pipe_ctx *pipe_ctx);
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void (*plane_atomic_disconnect)(struct dc *dc,
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struct pipe_ctx *pipe_ctx);
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void (*update_mpcc)(struct dc *dc, struct pipe_ctx *pipe_ctx);
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bool (*set_input_transfer_func)(struct dc *dc,
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struct pipe_ctx *pipe_ctx,
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const struct dc_plane_state *plane_state);
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bool (*set_output_transfer_func)(struct dc *dc,
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struct pipe_ctx *pipe_ctx,
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const struct dc_stream_state *stream);
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void (*power_down)(struct dc *dc);
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void (*enable_display_pipe_clock_gating)(struct dc_context *ctx,
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bool clock_gating);
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bool (*enable_display_power_gating)(struct dc *dc,
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uint8_t controller_id,
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struct dc_bios *dcb,
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enum pipe_gating_control power_gating);
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void (*blank_pixel_data)(struct dc *dc,
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struct pipe_ctx *pipe_ctx,
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bool blank);
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enum dc_status (*enable_stream_timing)(
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struct pipe_ctx *pipe_ctx,
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struct dc_state *context,
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struct dc *dc);
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void (*edp_backlight_control)(struct dc_link *link,
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bool enable);
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void (*setup_vupdate_interrupt)(struct dc *dc,
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struct pipe_ctx *pipe_ctx);
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bool (*did_underflow_occur)(struct dc *dc, struct pipe_ctx *pipe_ctx);
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void (*init_blank)(struct dc *dc, struct timing_generator *tg);
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void (*disable_vga)(struct dce_hwseq *hws);
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void (*bios_golden_init)(struct dc *dc);
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void (*plane_atomic_power_down)(struct dc *dc,
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struct dpp *dpp,
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struct hubp *hubp);
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void (*plane_atomic_disable)(struct dc *dc, struct pipe_ctx *pipe_ctx);
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void (*enable_power_gating_plane)(struct dce_hwseq *hws,
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bool enable);
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void (*dpp_root_clock_control)(
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struct dce_hwseq *hws,
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unsigned int dpp_inst,
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bool clock_on);
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void (*dpp_pg_control)(struct dce_hwseq *hws,
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unsigned int dpp_inst,
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bool power_on);
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void (*hubp_pg_control)(struct dce_hwseq *hws,
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unsigned int hubp_inst,
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bool power_on);
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void (*dsc_pg_control)(struct dce_hwseq *hws,
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unsigned int dsc_inst,
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bool power_on);
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bool (*dsc_pg_status)(struct dce_hwseq *hws,
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unsigned int dsc_inst);
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void (*update_odm)(struct dc *dc, struct dc_state *context,
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struct pipe_ctx *pipe_ctx);
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void (*program_all_writeback_pipes_in_tree)(struct dc *dc,
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const struct dc_stream_state *stream,
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struct dc_state *context);
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bool (*s0i3_golden_init_wa)(struct dc *dc);
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void (*set_hdr_multiplier)(struct pipe_ctx *pipe_ctx);
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void (*verify_allow_pstate_change_high)(struct dc *dc);
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void (*program_pipe)(struct dc *dc,
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struct pipe_ctx *pipe_ctx,
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struct dc_state *context);
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bool (*wait_for_blank_complete)(struct output_pixel_processor *opp);
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void (*dccg_init)(struct dce_hwseq *hws);
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bool (*set_blend_lut)(struct pipe_ctx *pipe_ctx,
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const struct dc_plane_state *plane_state);
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bool (*set_shaper_3dlut)(struct pipe_ctx *pipe_ctx,
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const struct dc_plane_state *plane_state);
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bool (*set_mcm_luts)(struct pipe_ctx *pipe_ctx,
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const struct dc_plane_state *plane_state);
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void (*PLAT_58856_wa)(struct dc_state *context,
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struct pipe_ctx *pipe_ctx);
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void (*setup_hpo_hw_control)(const struct dce_hwseq *hws, bool enable);
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#ifdef CONFIG_DRM_AMD_DC_DCN
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void (*program_mall_pipe_config)(struct dc *dc, struct dc_state *context);
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void (*subvp_update_force_pstate)(struct dc *dc, struct dc_state *context);
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void (*update_mall_sel)(struct dc *dc, struct dc_state *context);
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unsigned int (*calculate_dccg_k1_k2_values)(struct pipe_ctx *pipe_ctx,
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unsigned int *k1_div,
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unsigned int *k2_div);
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void (*set_pixels_per_cycle)(struct pipe_ctx *pipe_ctx);
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bool (*is_dp_dig_pixel_rate_div_policy)(struct pipe_ctx *pipe_ctx);
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#endif
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};
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struct dce_hwseq {
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struct dc_context *ctx;
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const struct dce_hwseq_registers *regs;
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const struct dce_hwseq_shift *shifts;
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const struct dce_hwseq_mask *masks;
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struct dce_hwseq_wa wa;
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struct hwseq_wa_state wa_state;
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struct hwseq_private_funcs funcs;
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PHYSICAL_ADDRESS_LOC fb_base;
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PHYSICAL_ADDRESS_LOC fb_top;
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PHYSICAL_ADDRESS_LOC fb_offset;
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PHYSICAL_ADDRESS_LOC uma_top;
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};
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#endif /* __DC_HW_SEQUENCER_PRIVATE_H__ */
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