216 lines
8.8 KiB
C
216 lines
8.8 KiB
C
/* $OpenBSD: mtd8xxreg.h,v 1.2 2003/10/21 18:58:49 jmc Exp $ */
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/*
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* Copyright (c) 2003 Oleg Safiullin <form@pdp11.org.ru>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#ifndef __DEV_IC_MTD8XXREG_H__
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#define __DEV_IC_MTD8XXREG_H__
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#define MTD_PCI_LOIO 0x10 /* PCI I/O base address register */
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#define MTD_PCI_LOMEM 0x14 /* PCI memory base address register */
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#define MTD_TIMEOUT 1000 /* Software reset timeout */
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#define MII_OPCODE_RD 0x6000
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#define MII_OPCODE_WR 0x5002
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/*
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* MTD8xx command and status register.
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*/
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#define MTD_PAR0 0x00 /* Physical address register 0*/
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#define MTD_PAR4 0x04 /* Physical address register 4 */
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#define MTD_MAR0 0x08 /* Multicast address register 0 */
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#define MTD_MAR4 0x0C /* Multicast address register 4 */
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#define MTD_TCRRCR 0x18 /* Transmit/receive config */
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#define MTD_BCR 0x1C /* Bus configuration register */
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#define MTD_TXPDR 0x20 /* Transmit poll demand */
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#define MTD_RXPDR 0x24 /* Receive poll demand */
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#define MTD_RXCWP 0x28 /* Receive current word pointer */
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#define MTD_TXLBA 0x2C /* Transmit list base address */
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#define MTD_RXLBA 0x30 /* Receive list base address */
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#define MTD_ISR 0x34 /* Interrupt status register */
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#define MTD_IMR 0x38 /* Interrupt mask register */
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#define MTD_TSR 0x48 /* Tally counter register */
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#define MTD_MIIMGT 0x40 /* MII management register */
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#define MTD_PHYCSR 0x4C /* PHY control status register */
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/*
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* Receive configuration register.
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*/
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#define RCR_RXS 0x00008000U /* Receive process is running */
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#define RCR_EIEN 0x00004000U /* Early interrupt enabled */
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#define RCR_RFCEN 0x00002000U /* Receive flow control enabled */
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#define RCR_NDFA 0x00001000U /* Not defined flow control address */
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#define RCR_RBLEN 0x00000800U /* Receive burst length enable */
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#define RCR_RPBL1 0x00000000U /* 1 word */
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#define RCR_RPBL4 0x00000100U /* 4 words */
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#define RCR_RPBL8 0x00000200U /* 8 words */
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#define RCR_RPBL16 0x00000300U /* 16 words */
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#define RCR_RPBL32 0x00000400U /* 32 words */
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#define RCR_RPBL64 0x00000500U /* 64 words */
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#define RCR_RPBL128 0x00000600U /* 128 words */
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#define RCR_RPBL512 0x00000700U /* 512 words */
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#define RCR_PROM 0x00000080U /* Promiscuous mode */
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#define RCR_AB 0x00000040U /* Accept broadcast addresses */
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#define RCR_AM 0x00000020U /* Accept multicast addresses */
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#define RCR_ARP 0x00000008U /* Accept runt packets */
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#define RCR_ALP 0x00000004U /* Accept long packets */
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#define RCR_SEP 0x00000002U /* Accept packets w/ receive errors */
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#define RCR_RE 0x00000001U /* Receive enable */
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/*
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* Transmit configuration register.
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*/
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#define TCR_TXS 0x80000000U /* Tx process is running */
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#define TCR_BACKOPT 0x10000000U /* Optional back-off */
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#define TCR_FBACK 0x08000000U /* Fast back-off */
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#define TCR_ENHANCED 0x02000000U /* Enhanced transmit mode */
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#define TCR_TFCEN 0x01000000U /* Ttansmit flow control enable */
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#define TCR_TFT64 0x00000000U /* 64 bytes */
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#define TCR_TFT32 0x00200000U /* 32 bytes */
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#define TCR_TFT128 0x00400000U /* 128 bytes */
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#define TCR_TFT256 0x00600000U /* 256 bytes */
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#define TCR_TFT512 0x00800000U /* 512 bytes */
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#define TCR_TFT768 0x00A00000U /* 768 bytes */
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#define TCR_TFT1024 0x00C00000U /* 1024 bytes */
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#define TCR_TFTSF 0x00E00000U /* Transmit store and forward */
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#define TCR_FD 0x00100000U /* Full-duplex mode */
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#define TCR_PS 0x00080000U /* Port speed is 10Mbit/s */
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#define TCR_TE 0x00040000U /* Transmit enable */
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#define TCR_LB 0x00020000U /* MII loopback on */
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/*
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* Bus configuration register.
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*/
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#define BCR_PROG 0x00000200U /* Programming */
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#define BCR_RLE 0x00000100U /* Read line cmd enable */
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#define BCR_RME 0x00000080U /* Read multiple cmd enable */
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#define BCR_WIE 0x00000040U /* Write and invalidate cmd enable */
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/* Programmable burst length */
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#define BCR_PBL1 0x00000000U /* 1 dword */
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#define BCR_PBL4 0x00000008U /* 4 dwords */
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#define BCR_PBL8 0x00000010U /* 8 dwords */
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#define BCR_PBL16 0x00000018U /* 16 dwords */
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#define BCR_PBL32 0x00000020U /* 32 dwords */
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#define BCR_PBL64 0x00000028U /* 64 dwords */
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#define BCR_PBL128 0x00000030U /* 128 dwords */
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#define BCR_PBL512 0x00000038U /* 512 dwords */
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#define BCR_SWR 0x00000001U /* Software reset */
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/*
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* Interrupt status register.
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*/
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#define ISR_PDF 0x00040000U /* Parallel detection fault */
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#define ISR_RFCON 0x00020000U /* Receive flow control XON */
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#define ISR_RFCOFF 0x00010000U /* Receive flow control XOFF */
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#define ISR_LSC 0x00008000U /* Link status change */
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#define ISR_ANC 0x00004000U /* Auto-negotiation completed */
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#define ISR_FBE 0x00002000U /* Fatal bus error */
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#define ISR_ETMASK 0x00001800U /* Error type mask */
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#define ISR_ET(x) ((x) & ISR_ETMASK)
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#define ISR_ETPARITY 0x00000000U /* Parity error */
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#define ISR_ETMASTER 0x00000800U /* Master abort */
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#define ISR_ETTARGET 0x00001000U /* Target abort */
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#define ISR_TUNF 0x00000400U /* Transmit underflow */
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#define ISR_ROVF 0x00000200U /* Receive overflow */
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#define ISR_ETI 0x00000100U /* Early transfer interrupt */
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#define ISR_ERI 0x00000080U /* Early receive interrupt */
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#define ISR_CNTOVF 0x00000040U /* CRC or MPA tally ounter overflow */
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#define ISR_RBU 0x00000020U /* Receive buffer unavailable */
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#define ISR_TBU 0x00000010U /* Transmit buffer unavailable */
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#define ISR_TI 0x00000008U /* Transmit interrupt */
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#define ISR_RI 0x00000004U /* Receive interrupt */
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#define ISR_RXERI 0x00000002U /* Receive error interrupt */
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#define ISR_INTRS (ISR_RBU | ISR_TBU | ISR_TI | ISR_RI | ISR_ETI)
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/*
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* Interrupt mask register.
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*/
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#define IMR_MPDF 0x00040000U /* Parallel detection fault */
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#define IMR_MRFCON 0x00020000U /* Receive flow control XON */
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#define IMR_MRFCOFF 0x00010000U /* Receive flow control XOFF */
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#define IMR_MLSC 0x00008000U /* Link status change */
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#define IMR_MANC 0x00004000U /* Auto-negotiation completed */
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#define IMR_MFBE 0x00002000U /* Fatal bus error */
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#define IMR_MTUNF 0x00000400U /* Transmit underflow */
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#define IMR_MROVF 0x00000200U /* Receive overflow */
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#define IMR_METI 0x00000100U /* Early transfer interrupt */
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#define IMR_MERI 0x00000080U /* Early receive interrupt */
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#define IMR_MCNTOVF 0x00000040U /* CRC or MPA tally ounter overflow */
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#define IMR_MRBU 0x00000020U /* Receive buffer unavailable */
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#define IMR_MTBU 0x00000010U /* Transmit buffer unavailable */
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#define IMR_MTI 0x00000008U /* Transmit interrupt */
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#define IMR_MRI 0x00000004U /* Receive interrupt */
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#define IMR_MRXERI 0x00000002U /* Receive error interrupt */
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#define IMR_INTRS (IMR_MRBU | IMR_MTBU | IMR_MTI | IMR_MRI | IMR_METI)
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/*
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* Transmit status register.
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*/
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#define TSR_NCR_MASK 0x0000FFFFU
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#define TSR_NCR_SHIFT 0
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#define TSR_NCR_GET(x) (((x) & TSR_NCR_MASK) >> TSR_NCR_SHIFT)
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/* Retry collisions count */
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/*
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* MII management register.
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*/
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#define MIIMGT_READ 0x00000000U
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#define MIIMGT_WRITE 0x00000008U
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#define MIIMGT_MDO 0x00000004U
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#define MIIMGT_MDI 0x00000002U
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#define MIIMGT_MDC 0x00000001U
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#define MIIMGT_MASK 0x0000000FU
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/*
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* Command and status register space access macros.
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*/
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#define CSR_READ_1(reg) bus_space_read_1(sc->sc_bust, sc->sc_bush, reg)
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#define CSR_WRITE_1(reg, val) \
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bus_space_write_1(sc->sc_bust, sc->sc_bush, reg, val)
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#define CSR_READ_2(reg) bus_space_read_2(sc->sc_bust, sc->sc_bush, reg)
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#define CSR_WRITE_2(reg, vat) \
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bus_space_write_2(sc->sc_bust, sc->sc_bush, reg, val)
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#define CSR_READ_4(reg) bus_space_read_4(sc->sc_bust, sc->sc_bush, reg)
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#define CSR_WRITE_4(reg, val) \
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bus_space_write_4(sc->sc_bust, sc->sc_bush, reg, val)
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#define CSR_SETBIT(reg, val) CSR_WRITE_4(reg, CSR_READ_4(reg) | (val))
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#define CSR_CLRBIT(reg, val) CSR_WRITE_4(reg, CSR_READ_4(reg) & ~(val))
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#endif /* __DEV_IC_MTD8XXREG_H__ */
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