279 lines
11 KiB
C
279 lines
11 KiB
C
/* $OpenBSD: dwqereg.h,v 1.7 2024/04/25 11:37:39 stsp Exp $ */
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/*
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* Copyright (c) 2008, 2019 Mark Kettenis <kettenis@openbsd.org>
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* Copyright (c) 2017, 2022 Patrick Wildt <patrick@blueri.se>
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#define GMAC_MAC_CONF 0x0000
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#define GMAC_MAC_CONF_CST (1 << 21)
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#define GMAC_MAC_CONF_ACS (1 << 20)
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#define GMAC_MAC_CONF_BE (1 << 18)
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#define GMAC_MAC_CONF_JD (1 << 17)
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#define GMAC_MAC_CONF_JE (1 << 16)
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#define GMAC_MAC_CONF_PS (1 << 15)
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#define GMAC_MAC_CONF_FES (1 << 14)
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#define GMAC_MAC_CONF_DM (1 << 13)
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#define GMAC_MAC_CONF_DCRS (1 << 9)
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#define GMAC_MAC_CONF_TE (1 << 1)
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#define GMAC_MAC_CONF_RE (1 << 0)
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#define GMAC_MAC_PACKET_FILTER 0x0008
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#define GMAC_MAC_PACKET_FILTER_HPF (1 << 10)
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#define GMAC_MAC_PACKET_FILTER_PCF_MASK (3 << 6)
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#define GMAC_MAC_PACKET_FILTER_PCF_ALL (2 << 6)
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#define GMAC_MAC_PACKET_FILTER_DBF (1 << 5)
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#define GMAC_MAC_PACKET_FILTER_PM (1 << 4)
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#define GMAC_MAC_PACKET_FILTER_HMC (1 << 2)
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#define GMAC_MAC_PACKET_FILTER_HUC (1 << 1)
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#define GMAC_MAC_PACKET_FILTER_PR (1 << 0)
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#define GMAC_MAC_HASH_TAB_REG0 0x0010
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#define GMAC_MAC_HASH_TAB_REG1 0x0014
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#define GMAC_INT_MASK 0x003c
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#define GMAC_INT_MASK_LPIIM (1 << 10)
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#define GMAC_INT_MASK_PIM (1 << 3)
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#define GMAC_INT_MASK_RIM (1 << 0)
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#define GMAC_QX_TX_FLOW_CTRL(x) (0x0070 + (x) * 4)
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#define GMAC_QX_TX_FLOW_CTRL_PT_SHIFT 16
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#define GMAC_QX_TX_FLOW_CTRL_TFE (1 << 0)
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#define GMAC_RX_FLOW_CTRL 0x0090
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#define GMAC_RX_FLOW_CTRL_RFE (1 << 0)
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#define GMAC_RXQ_CTRL0 0x00a0
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#define GMAC_RXQ_CTRL0_QUEUE_CLR(x) (0x3 << ((x) * 2)
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#define GMAC_RXQ_CTRL0_AVB_QUEUE_EN(x) (1 << ((x) * 2))
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#define GMAC_RXQ_CTRL0_DCB_QUEUE_EN(x) (2 << ((x) * 2))
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#define GMAC_RXQ_CTRL1 0x00a4
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#define GMAC_RXQ_CTRL2 0x00a8
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#define GMAC_RXQ_CTRL3 0x00ac
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#define GMAC_INT_STATUS 0x00b0
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#define GMAC_INT_EN 0x00b4
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#define GMAC_MAC_1US_TIC_CTR 0x00dc
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#define GMAC_VERSION 0x0110
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#define GMAC_VERSION_SNPS_MASK 0xff
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#define GMAC_MAC_HW_FEATURE(x) (0x011c + (x) * 0x4)
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#define GMAC_MAC_HW_FEATURE1_TXFIFOSIZE(x) (((x) >> 6) & 0x1f)
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#define GMAC_MAC_HW_FEATURE1_RXFIFOSIZE(x) (((x) >> 0) & 0x1f)
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#define GMAC_MAC_MDIO_ADDR 0x0200
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#define GMAC_MAC_MDIO_ADDR_PA_SHIFT 21
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#define GMAC_MAC_MDIO_ADDR_RDA_SHIFT 16
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#define GMAC_MAC_MDIO_ADDR_CR_SHIFT 8
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#define GMAC_MAC_MDIO_ADDR_CR_60_100 0
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#define GMAC_MAC_MDIO_ADDR_CR_100_150 1
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#define GMAC_MAC_MDIO_ADDR_CR_20_35 2
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#define GMAC_MAC_MDIO_ADDR_CR_35_60 3
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#define GMAC_MAC_MDIO_ADDR_CR_150_250 4
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#define GMAC_MAC_MDIO_ADDR_CR_250_300 5
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#define GMAC_MAC_MDIO_ADDR_CR_300_500 6
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#define GMAC_MAC_MDIO_ADDR_CR_500_800 7
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#define GMAC_MAC_MDIO_ADDR_SKAP (1 << 4)
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#define GMAC_MAC_MDIO_ADDR_GOC_READ (3 << 2)
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#define GMAC_MAC_MDIO_ADDR_GOC_WRITE (1 << 2)
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#define GMAC_MAC_MDIO_ADDR_C45E (1 << 1)
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#define GMAC_MAC_MDIO_ADDR_GB (1 << 0)
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#define GMAC_MAC_MDIO_DATA 0x0204
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#define GMAC_MAC_ADDR0_HI 0x0300
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#define GMAC_MAC_ADDR0_LO 0x0304
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#define GMAC_MMC_RX_INT_MASK 0x070c
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#define GMAC_MMC_TX_INT_MASK 0x0710
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#define GMAC_MTL_OPERATION_MODE 0x0c00
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#define GMAC_MTL_FRPE (1 << 15)
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#define GMAC_MTL_OPERATION_SCHALG_MASK (0x3 << 5)
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#define GMAC_MTL_OPERATION_SCHALG_WRR (0x0 << 5)
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#define GMAC_MTL_OPERATION_SCHALG_WFQ (0x1 << 5)
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#define GMAC_MTL_OPERATION_SCHALG_DWRR (0x2 << 5)
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#define GMAC_MTL_OPERATION_SCHALG_SP (0x3 << 5)
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#define GMAC_MTL_OPERATION_RAA_MASK (0x1 << 2)
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#define GMAC_MTL_OPERATION_RAA_SP (0x0 << 2)
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#define GMAC_MTL_OPERATION_RAA_WSP (0x1 << 2)
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#define GMAC_MTL_CHAN_BASE_ADDR(x) (0x0d00 + (x) * 0x40)
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#define GMAC_MTL_CHAN_TX_OP_MODE(x) (GMAC_MTL_CHAN_BASE_ADDR(x) + 0x0)
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#define GMAC_MTL_CHAN_TX_OP_MODE_TQS_MASK (0x1ffU << 16)
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#define GMAC_MTL_CHAN_TX_OP_MODE_TQS_SHIFT 16
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#define GMAC_MTL_CHAN_TX_OP_MODE_TTC_MASK (0x7 << 4)
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#define GMAC_MTL_CHAN_TX_OP_MODE_TTC_SHIFT 4
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#define GMAC_MTL_CHAN_TX_OP_MODE_TTC_32 0
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#define GMAC_MTL_CHAN_TX_OP_MODE_TTC_64 (1 << 4)
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#define GMAC_MTL_CHAN_TX_OP_MODE_TTC_96 (2 << 4)
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#define GMAC_MTL_CHAN_TX_OP_MODE_TTC_128 (3 << 4)
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#define GMAC_MTL_CHAN_TX_OP_MODE_TTC_192 (4 << 4)
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#define GMAC_MTL_CHAN_TX_OP_MODE_TTC_256 (5 << 4)
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#define GMAC_MTL_CHAN_TX_OP_MODE_TTC_384 (6 << 4)
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#define GMAC_MTL_CHAN_TX_OP_MODE_TTC_512 (7 << 4)
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#define GMAC_MTL_CHAN_TX_OP_MODE_TXQEN_MASK (0x3 << 2)
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#define GMAC_MTL_CHAN_TX_OP_MODE_TXQEN_AV (1 << 2)
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#define GMAC_MTL_CHAN_TX_OP_MODE_TXQEN (2 << 2)
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#define GMAC_MTL_CHAN_TX_OP_MODE_TSF (1 << 1)
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#define GMAC_MTL_CHAN_TX_OP_MODE_FTQ (1 << 0)
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#define GMAC_MTL_CHAN_TX_DEBUG(x) (GMAC_MTL_CHAN_BASE_ADDR(x) + 0x8)
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#define GMAC_MTL_CHAN_INT_CTRL(x) (GMAC_MTL_CHAN_BASE_ADDR(x) + 0x2c)
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#define GMAC_MTL_CHAN_RX_OP_MODE(x) (GMAC_MTL_CHAN_BASE_ADDR(x) + 0x30)
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#define GMAC_MTL_CHAN_RX_OP_MODE_RQS_MASK (0x3ffU << 20)
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#define GMAC_MTL_CHAN_RX_OP_MODE_RQS_SHIFT 20
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#define GMAC_MTL_CHAN_RX_OP_MODE_RFD_MASK (0x3fU << 14)
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#define GMAC_MTL_CHAN_RX_OP_MODE_RFD_SHIFT 14
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#define GMAC_MTL_CHAN_RX_OP_MODE_RFA_MASK (0x3fU << 8)
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#define GMAC_MTL_CHAN_RX_OP_MODE_RFA_SHIFT 8
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#define GMAC_MTL_CHAN_RX_OP_MODE_EHFC (1 << 7)
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#define GMAC_MTL_CHAN_RX_OP_MODE_RSF (1 << 5)
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#define GMAC_MTL_CHAN_RX_OP_MODE_RTC_MASK (0x3 << 3)
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#define GMAC_MTL_CHAN_RX_OP_MODE_RTC_SHIFT 3
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#define GMAC_MTL_CHAN_RX_OP_MODE_RTC_32 (1 << 3)
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#define GMAC_MTL_CHAN_RX_OP_MODE_RTC_64 (0 << 3)
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#define GMAC_MTL_CHAN_RX_OP_MODE_RTC_96 (2 << 3)
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#define GMAC_MTL_CHAN_RX_OP_MODE_RTC_128 (3 << 3)
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#define GMAC_MTL_CHAN_RX_DEBUG(x) (GMAC_MTL_CHAN_BASE_ADDR(x) + 0x38)
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#define GMAC_BUS_MODE 0x1000
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#define GMAC_BUS_MODE_DCHE (1 << 19)
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#define GMAC_BUS_MODE_SWR (1 << 0)
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#define GMAC_SYS_BUS_MODE 0x1004
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#define GMAC_SYS_BUS_MODE_EN_LPI (1U << 31)
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#define GMAC_SYS_BUS_MODE_LPI_XIT_FRM (1 << 30)
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#define GMAC_SYS_BUS_MODE_WR_OSR_LMT_MASK (0xf << 24)
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#define GMAC_SYS_BUS_MODE_WR_OSR_LMT_SHIFT 24
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#define GMAC_SYS_BUS_MODE_RD_OSR_LMT_MASK (0xf << 16)
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#define GMAC_SYS_BUS_MODE_RD_OSR_LMT_SHIFT 16
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#define GMAC_SYS_BUS_MODE_MB (1 << 14)
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#define GMAC_SYS_BUS_MODE_AAL (1 << 12)
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#define GMAC_SYS_BUS_MODE_EAME (1 << 11)
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#define GMAC_SYS_BUS_MODE_BLEN_256 (1 << 7)
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#define GMAC_SYS_BUS_MODE_BLEN_128 (1 << 6)
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#define GMAC_SYS_BUS_MODE_BLEN_64 (1 << 5)
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#define GMAC_SYS_BUS_MODE_BLEN_32 (1 << 4)
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#define GMAC_SYS_BUS_MODE_BLEN_16 (1 << 3)
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#define GMAC_SYS_BUS_MODE_BLEN_8 (1 << 2)
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#define GMAC_SYS_BUS_MODE_BLEN_4 (1 << 1)
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#define GMAC_SYS_BUS_MODE_FB (1 << 0)
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#define GMAC_CHAN_BASE_ADDR(x) (0x1100 + (x) * 0x80)
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#define GMAC_CHAN_CONTROL(x) (GMAC_CHAN_BASE_ADDR(x) + 0x0)
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#define GMAC_CHAN_CONTROL_8XPBL (1 << 16)
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#define GMAC_CHAN_TX_CONTROL(x) (GMAC_CHAN_BASE_ADDR(x) + 0x4)
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#define GMAC_CHAN_TX_CONTROL_PBL_MASK (0x3f << 16)
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#define GMAC_CHAN_TX_CONTROL_PBL_SHIFT 16
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#define GMAC_CHAN_TX_CONTROL_OSP (1 << 4)
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#define GMAC_CHAN_TX_CONTROL_ST (1 << 0)
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#define GMAC_CHAN_RX_CONTROL(x) (GMAC_CHAN_BASE_ADDR(x) + 0x8)
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#define GMAC_CHAN_RX_CONTROL_RPBL_MASK (0x3f << 16)
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#define GMAC_CHAN_RX_CONTROL_RPBL_SHIFT 16
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#define GMAC_CHAN_RX_CONTROL_SR (1 << 0)
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#define GMAC_CHAN_TX_BASE_ADDR_HI(x) (GMAC_CHAN_BASE_ADDR(x) + 0x10)
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#define GMAC_CHAN_TX_BASE_ADDR(x) (GMAC_CHAN_BASE_ADDR(x) + 0x14)
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#define GMAC_CHAN_RX_BASE_ADDR_HI(x) (GMAC_CHAN_BASE_ADDR(x) + 0x18)
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#define GMAC_CHAN_RX_BASE_ADDR(x) (GMAC_CHAN_BASE_ADDR(x) + 0x1c)
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#define GMAC_CHAN_TX_END_ADDR(x) (GMAC_CHAN_BASE_ADDR(x) + 0x20)
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#define GMAC_CHAN_RX_END_ADDR(x) (GMAC_CHAN_BASE_ADDR(x) + 0x28)
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#define GMAC_CHAN_TX_RING_LEN(x) (GMAC_CHAN_BASE_ADDR(x) + 0x2c)
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#define GMAC_CHAN_RX_RING_LEN(x) (GMAC_CHAN_BASE_ADDR(x) + 0x30)
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#define GMAC_CHAN_INTR_ENA(x) (GMAC_CHAN_BASE_ADDR(x) + 0x34)
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#define GMAC_CHAN_INTR_ENA_NIE (1 << 15)
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#define GMAC_CHAN_INTR_ENA_AIE (1 << 14)
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#define GMAC_CHAN_INTR_ENA_CDE (1 << 13)
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#define GMAC_CHAN_INTR_ENA_FBE (1 << 12)
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#define GMAC_CHAN_INTR_ENA_ERE (1 << 11)
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#define GMAC_CHAN_INTR_ENA_ETE (1 << 10)
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#define GMAC_CHAN_INTR_ENA_RWE (1 << 9)
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#define GMAC_CHAN_INTR_ENA_RSE (1 << 8)
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#define GMAC_CHAN_INTR_ENA_RBUE (1 << 7)
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#define GMAC_CHAN_INTR_ENA_RIE (1 << 6)
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#define GMAC_CHAN_INTR_ENA_TBUE (1 << 2)
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#define GMAC_CHAN_INTR_ENA_TSE (1 << 1)
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#define GMAC_CHAN_INTR_ENA_TIE (1 << 0)
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#define GMAC_CHAN_RX_WATCHDOG(x) (GMAC_CHAN_CONTROL(x) + 0x38)
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#define GMAC_CHAN_SLOT_CTRL_STATUS(x) (GMAC_CHAN_CONTROL(x) + 0x3c)
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#define GMAC_CHAN_CUR_TX_DESC(x) (GMAC_CHAN_CONTROL(x) + 0x44)
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#define GMAC_CHAN_CUR_RX_DESC(x) (GMAC_CHAN_CONTROL(x) + 0x4c)
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#define GMAC_CHAN_CUR_TX_BUF_ADDR(x) (GMAC_CHAN_CONTROL(x) + 0x54)
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#define GMAC_CHAN_CUR_RX_BUF_ADDR(x) (GMAC_CHAN_CONTROL(x) + 0x5c)
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#define GMAC_CHAN_STATUS(x) (GMAC_CHAN_CONTROL(x) + 0x60)
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#define GMAC_CHAN_STATUS_REB_MASK 0x7
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#define GMAC_CHAN_STATUS_REB_SHIFT 19
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#define GMAC_CHAN_STATUS_TEB_MASK 0x7
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#define GMAC_CHAN_STATUS_TEB_SHIFT 16
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#define GMAC_CHAN_STATUS_NIS (1 << 15)
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#define GMAC_CHAN_STATUS_AIS (1 << 14)
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#define GMAC_CHAN_STATUS_CDE (1 << 13)
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#define GMAC_CHAN_STATUS_FBE (1 << 12)
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#define GMAC_CHAN_STATUS_ERI (1 << 11)
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#define GMAC_CHAN_STATUS_ETI (1 << 10)
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#define GMAC_CHAN_STATUS_RWT (1 << 9)
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#define GMAC_CHAN_STATUS_RPS (1 << 8)
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#define GMAC_CHAN_STATUS_RBU (1 << 7)
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#define GMAC_CHAN_STATUS_RI (1 << 6)
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#define GMAC_CHAN_STATUS_TBU (1 << 2)
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#define GMAC_CHAN_STATUS_TPS (1 << 1)
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#define GMAC_CHAN_STATUS_TI (1 << 0)
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/*
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* DWQE descriptors.
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*/
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struct dwqe_desc {
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uint32_t sd_tdes0;
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uint32_t sd_tdes1;
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uint32_t sd_tdes2;
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uint32_t sd_tdes3;
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};
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/* Tx bits */
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#define TDES2_IC (1U << 31)
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#define TDES3_ES (1 << 15)
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#define TDES3_DE (1 << 23)
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#define TDES3_LS (1 << 28)
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#define TDES3_FS (1 << 29)
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#define TDES3_OWN (1U << 31)
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/* Rx bits (read format; host to device) */
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#define RDES3_BUF1V (1 << 24)
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#define RDES3_BUF2V (1 << 25)
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#define RDES3_IC (1 << 30)
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#define RDES3_OWN (1U << 31)
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/* Rx bits (writeback format; device to host) */
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#define RDES1_IP_PAYLOAD_TYPE 0x7
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#define RDES1_IP_PAYLOAD_UNKNOWN 0x0
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#define RDES1_IP_PAYLOAD_UDP 0x1
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#define RDES1_IP_PAYLOAD_TCP 0x2
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#define RDES1_IP_PAYLOAD_ICMP 0x3
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#define RDES1_IP_HDR_ERROR (1 << 3)
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#define RDES1_IPV4_HDR (1 << 4)
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#define RDES1_IPV6_HDR (1 << 5)
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#define RDES1_IP_CSUM_BYPASS (1 << 6)
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#define RDES1_IP_PAYLOAD_ERROR (1 << 7)
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#define RDES3_LENGTH (0x7fff << 0)
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#define RDES3_ES (1 << 15)
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#define RDES3_LENTYPE 0x70000
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#define RDES3_LENTYPE_LENGTH (0x0 << 16)
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#define RDES3_LENTYPE_TYPE (0x1 << 16)
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/* 0x2 is reserved */
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#define RDES3_LENTYPE_ARP (0x3 << 16)
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#define RDES3_LENTYPE_VLAN (0x4 << 16)
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#define RDES3_LENTYPE_2VLAN (0x5 << 16)
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#define RDES3_LENTYPE_MACCTL (0x6 << 16)
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#define RDES3_LENTYPE_OAM (0x7 << 16)
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#define RDES3_DE (1 << 19)
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#define RDES3_RE (1 << 20)
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#define RDES3_OE (1 << 21)
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#define RDES3_RWT (1 << 22)
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#define RDES3_GP (1 << 23)
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#define RDES3_CE (1 << 24)
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#define RDES3_RDES0_VALID (1 << 25)
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#define RDES3_RDES1_VALID (1 << 26)
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#define RDES3_RDES2_VALID (1 << 27)
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#define RDES3_LD (1 << 28)
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#define RDES3_FD (1 << 29)
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#define RDES3_CTXT (1 << 30)
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/* Bit 31 is the OWN bit, as in "read" format. */
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