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HardenedBSD/sys/conf/options.riscv

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Welcome the RISC-V 64-bit kernel. This is the final step required allowing to compile and to run RISC-V kernel and userland from HEAD. RISC-V is a completely open ISA that is freely available to academia and industry. Thanks to all the people involved! Special thanks to Andrew Turner, David Chisnall, Ed Maste, Konstantin Belousov, John Baldwin and Arun Thomas for their help. Thanks to Robert Watson for organizing this project. This project sponsored by UK Higher Education Innovation Fund (HEIF5) and DARPA CTSRD project at the University of Cambridge Computer Laboratory. FreeBSD/RISC-V project home: https://wiki.freebsd.org/riscv Reviewed by: andrew, emaste, kib Relnotes: Yes Sponsored by: DARPA, AFRL Sponsored by: HEIF5 Differential Revision: https://reviews.freebsd.org/D4982
2016-01-29 16:12:31 +01:00
# $FreeBSD$
RISCV opt_global.h
Add full softfloat and hardfloat support for RISC-V. Hardfloat is now default (use riscv64sf as TARGET_ARCH for softfloat). Sponsored by: DARPA, AFRL Differential Revision: https://reviews.freebsd.org/D8529
2016-11-16 16:21:32 +01:00
FPE opt_global.h
o Add driver for PLIC (Platform-Level Interrupt Controller) device. o Convert interrupt machdep support to use INTRNG code. Sponsored by: DARPA, AFRL
2018-06-12 19:45:15 +02:00
INTRNG opt_global.h
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