HardenedBSD/sys/dts/arm/socfpga_cyclone5_sockit_sdmmc.dts

/*-
 * Copyright (c) 2017 Ruslan Bukin <br@bsdpad.com>
 * All rights reserved.
 *
 * This software was developed by SRI International and the University of
 * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
 * ("CTSRD"), as part of the DARPA CRASH research programme.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 */

/* /dts-v1/; */
#include "socfpga_cyclone5_sockit.dts"

/ {
	model = "Terasic SoCkit";
	compatible = "altr,socfpga-cyclone5", "altr,socfpga";

	/* Reserve first page for secondary CPU trampoline code */
	memreserve = < 0x00000000 0x1000 >;

	soc {
		/* Local timer */
		timer@fffec600 {
			clock-frequency = <200000000>;
		};

		/* Global timer */
		global_timer: timer@fffec200 {
			compatible = "arm,cortex-a9-global-timer";
			reg = <0xfffec200 0x20>;
			interrupts = <1 11 0xf04>;
			clock-frequency = <200000000>;
		};
	};

	chosen {
		stdin = "serial0";
		stdout = "serial0";
	};
};

&mmc0 {
	bus-frequency = <25000000>;
};

&uart0 {
	clock-frequency = <100000000>;
};

&uart1 {
	status = "disabled";
};