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https://git.hardenedbsd.org/hardenedbsd/HardenedBSD.git
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87 lines
1.9 KiB
Plaintext
87 lines
1.9 KiB
Plaintext
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.sc
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.nr pp 12
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.nr tp 12
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.nr sp 12
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.nr fi 0
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.st ug
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.ls 1
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.po 1i
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.pl 11i
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.EQ
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gsize 12
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delim $$
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define // 'over down 10'
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define sw 'phi sub'
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define aa 'A sub'
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define vv 'V sub'
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define mm 'M sub'
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define nn 'N sub'
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define cc 'C sub'
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define ll 'L sub'
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define rr 'R sub'
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define ss 'S sub'
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define gg 'g sub'
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define ff 'F sub'
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define qq 'Q sub'
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define qqq '{C prime} sub'
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define pp 'P sub'
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define tt 'T sub'
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define zz 'Z sub'
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define kk 'K sub'
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define ii 'I sub'
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define iis 'IC sub'
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define e2 '2 sup'
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define sunc '{ sin x } / x'
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define vddm1V 'vv DD - 1 ^ roman V'
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define vssp1V 'vv SS + 1 ^ roman V'
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.EN
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.pp
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The following slide shows the complete schematics of the
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fully-differential RIC. The operation includes a
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correlated-double-sampling phase that occurs once every 256
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clock periods, also called the
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.i "spreading ratio" .
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This reset phase is controlled by clocks $ DP sub 1 $ and $ DP
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sub 2 $ in which the integrator is initialized by totally
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removing the charge from $ cc F $ and storing the low-frequency
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noise of the op amp in $ cc C $. At the same time the comparison
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thresholds are set.
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.fl
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.po -0.2i
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.sp 2
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.lp
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.(b
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.EQ
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gsize -4
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.EN
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.GS
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roman 1
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italics 2
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bold 3
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special 4
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narrow 1
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medium 3
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thick 5
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width 5.5
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l mg
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file grnexmpl.g
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.GE
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.EQ
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gsize +4
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.EN
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.)b
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.fl
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.po +0.2i
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.pp
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The faster clocks are $ PN $, $ ITS $ and $ SP $. The sampling
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capacitor $ cc S $ performs the delayed subtraction of a sample
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of the input signal $ +- ^ vv SIG $ and a choice of $ - ^ vv REF
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$, $ AGND $ or $ + ^ vv REF $ according to the operations
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performed by the logic partially depicted operating on past
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results of the comparisons. The synchronous comparators are
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reset at this fast rates, thus performing one comparison for
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every fast clock cycle. The dynamic common-mode feedback
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arrangement operates synchronously with the reset time slot and
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its configuration is equivalent to that in the differential
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feedback path.
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