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HardenedBSD/sys/conf/Makefile.riscv

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Welcome the RISC-V 64-bit kernel. This is the final step required allowing to compile and to run RISC-V kernel and userland from HEAD. RISC-V is a completely open ISA that is freely available to academia and industry. Thanks to all the people involved! Special thanks to Andrew Turner, David Chisnall, Ed Maste, Konstantin Belousov, John Baldwin and Arun Thomas for their help. Thanks to Robert Watson for organizing this project. This project sponsored by UK Higher Education Innovation Fund (HEIF5) and DARPA CTSRD project at the University of Cambridge Computer Laboratory. FreeBSD/RISC-V project home: https://wiki.freebsd.org/riscv Reviewed by: andrew, emaste, kib Relnotes: Yes Sponsored by: DARPA, AFRL Sponsored by: HEIF5 Differential Revision: https://reviews.freebsd.org/D4982
2016-01-29 16:12:31 +01:00
# Makefile.riscv -- with config changes.
# Copyright 1990 W. Jolitz
# from: @(#)Makefile.i386 7.1 5/10/91
# from FreeBSD: src/sys/conf/Makefile.i386,v 1.255 2002/02/20 23:35:49
# $FreeBSD$
#
# Makefile for FreeBSD
#
# RISCVTODO: copy pasted from aarch64, needs to be
# constructed from a machine description:
# config machineid
# Most changes should be made in the machine description
# /sys/riscv/conf/``machineid''
# after which you should do
# config machineid
# Generic makefile changes should be made in
# /sys/conf/Makefile.riscv
# after which config should be rerun for all machines.
#
# Which version of config(8) is required.
%VERSREQ= 600012
.if !defined(S)
S= ../../..
.endif
.include "$S/conf/kern.pre.mk"
INCLUDES+= -I$S/contrib/libfdt
Support for v1.10 (latest) of RISC-V privilege specification. New version is not compatible on supervisor mode with v1.9.1 (previous version). Highlights: o BBL (Berkeley Boot Loader) provides no initial page tables anymore allowing us to choose VM, to build page tables manually and enable MMU in S-mode. o SBI interface changed. o GENERIC kernel. FDT is now chosen standard for RISC-V hardware description. DTB is now provided by Spike (golden model simulator). This allows us to introduce GENERIC kernel. However, description for console and timer devices is not provided in DTB, so move these devices temporary to nexus bus. o Supervisor can't access userspace by default. Solution is to set SUM (permit Supervisor User Memory access) bit in sstatus register. o Compressed extension is now turned on by default. o External GCC 7.1 compiler used. o _gp renamed to __global_pointer$ o Compiler -march= string is now in use allowing us to choose required extensions (compressed, FPU, atomic, etc). Sponsored by: DARPA, AFRL Differential Revision: https://reviews.freebsd.org/D11800
2017-08-10 16:18:09 +02:00
SYSTEM_LD= @${LD} -N -m ${LD_EMULATION} -Bdynamic -T ${LDSCRIPT} ${_LDFLAGS} \
--no-warn-mismatch --warn-common --export-dynamic \
--dynamic-linker /red/herring \
-o ${.TARGET} -X ${SYSTEM_OBJS} vers.o
Welcome the RISC-V 64-bit kernel. This is the final step required allowing to compile and to run RISC-V kernel and userland from HEAD. RISC-V is a completely open ISA that is freely available to academia and industry. Thanks to all the people involved! Special thanks to Andrew Turner, David Chisnall, Ed Maste, Konstantin Belousov, John Baldwin and Arun Thomas for their help. Thanks to Robert Watson for organizing this project. This project sponsored by UK Higher Education Innovation Fund (HEIF5) and DARPA CTSRD project at the University of Cambridge Computer Laboratory. FreeBSD/RISC-V project home: https://wiki.freebsd.org/riscv Reviewed by: andrew, emaste, kib Relnotes: Yes Sponsored by: DARPA, AFRL Sponsored by: HEIF5 Differential Revision: https://reviews.freebsd.org/D4982
2016-01-29 16:12:31 +01:00
.if !empty(DDB_ENABLED)
Add support for ddb(4). Sponsored by: DARPA, AFRL Sponsored by: HEIF5
2016-03-10 16:51:43 +01:00
CFLAGS += -fno-omit-frame-pointer -fno-optimize-sibling-calls
Welcome the RISC-V 64-bit kernel. This is the final step required allowing to compile and to run RISC-V kernel and userland from HEAD. RISC-V is a completely open ISA that is freely available to academia and industry. Thanks to all the people involved! Special thanks to Andrew Turner, David Chisnall, Ed Maste, Konstantin Belousov, John Baldwin and Arun Thomas for their help. Thanks to Robert Watson for organizing this project. This project sponsored by UK Higher Education Innovation Fund (HEIF5) and DARPA CTSRD project at the University of Cambridge Computer Laboratory. FreeBSD/RISC-V project home: https://wiki.freebsd.org/riscv Reviewed by: andrew, emaste, kib Relnotes: Yes Sponsored by: DARPA, AFRL Sponsored by: HEIF5 Differential Revision: https://reviews.freebsd.org/D4982
2016-01-29 16:12:31 +01:00
.endif
Set dependencies for genassym.c. This fixes non-parallel build.
2016-05-24 18:30:05 +02:00
# hack because genassym.c includes sys/bus.h which includes these.
genassym.o: bus_if.h device_if.h
Welcome the RISC-V 64-bit kernel. This is the final step required allowing to compile and to run RISC-V kernel and userland from HEAD. RISC-V is a completely open ISA that is freely available to academia and industry. Thanks to all the people involved! Special thanks to Andrew Turner, David Chisnall, Ed Maste, Konstantin Belousov, John Baldwin and Arun Thomas for their help. Thanks to Robert Watson for organizing this project. This project sponsored by UK Higher Education Innovation Fund (HEIF5) and DARPA CTSRD project at the University of Cambridge Computer Laboratory. FreeBSD/RISC-V project home: https://wiki.freebsd.org/riscv Reviewed by: andrew, emaste, kib Relnotes: Yes Sponsored by: DARPA, AFRL Sponsored by: HEIF5 Differential Revision: https://reviews.freebsd.org/D4982
2016-01-29 16:12:31 +01:00
%BEFORE_DEPEND
%OBJS
%FILES.c
%FILES.s
%FILES.m
%CLEAN
%RULES
.include "$S/conf/kern.post.mk"
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