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Only support INTRNG in the SMP code on arm. We already require INTRNG on
anything that could be multicore on arm.
This commit is contained in:
Andrew Turner
parent
e4c66ddabd
commit
15bff09749
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=336806
@ -26,7 +26,6 @@
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* SUCH DAMAGE.
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*/
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#include "opt_ddb.h"
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#include "opt_smp.h"
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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@ -75,9 +74,6 @@ volatile int mp_naps;
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/* Set to 1 once we're ready to let the APs out of the pen. */
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volatile int aps_ready = 0;
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#ifndef INTRNG
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static int ipi_handler(void *arg);
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#endif
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void set_stackptrs(int cpu);
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/* Temporary variables for init_secondary() */
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@ -153,9 +149,6 @@ init_secondary(int cpu)
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{
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struct pcpu *pc;
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uint32_t loop_counter;
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#ifndef INTRNG
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int start = 0, end = 0;
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#endif
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pmap_set_tex();
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cpuinfo_reinit_mmu(pmap_kern_ttb);
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@ -215,20 +208,6 @@ init_secondary(int cpu)
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mtx_unlock_spin(&ap_boot_mtx);
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#ifndef INTRNG
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/* Enable ipi */
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#ifdef IPI_IRQ_START
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start = IPI_IRQ_START;
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#ifdef IPI_IRQ_END
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end = IPI_IRQ_END;
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#else
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end = IPI_IRQ_START;
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#endif
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#endif
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for (int i = start; i <= end; i++)
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arm_unmask_irq(i);
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#endif /* INTRNG */
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enable_interrupts(PSR_I);
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loop_counter = 0;
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@ -250,7 +229,6 @@ init_secondary(int cpu)
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/* NOTREACHED */
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}
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#ifdef INTRNG
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static void
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ipi_rendezvous(void *dummy __unused)
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{
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@ -347,126 +325,20 @@ ipi_hardclock(void *arg)
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critical_exit();
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}
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#else
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static int
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ipi_handler(void *arg)
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{
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u_int cpu, ipi;
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cpu = PCPU_GET(cpuid);
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ipi = pic_ipi_read((int)arg);
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while ((ipi != 0x3ff)) {
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switch (ipi) {
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case IPI_RENDEZVOUS:
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CTR0(KTR_SMP, "IPI_RENDEZVOUS");
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smp_rendezvous_action();
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break;
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case IPI_AST:
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CTR0(KTR_SMP, "IPI_AST");
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break;
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case IPI_STOP:
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/*
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* IPI_STOP_HARD is mapped to IPI_STOP so it is not
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* necessary to add it in the switch.
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*/
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CTR0(KTR_SMP, "IPI_STOP or IPI_STOP_HARD");
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savectx(&stoppcbs[cpu]);
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/*
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* CPUs are stopped when entering the debugger and at
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* system shutdown, both events which can precede a
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* panic dump. For the dump to be correct, all caches
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* must be flushed and invalidated, but on ARM there's
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* no way to broadcast a wbinv_all to other cores.
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* Instead, we have each core do the local wbinv_all as
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* part of stopping the core. The core requesting the
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* stop will do the l2 cache flush after all other cores
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* have done their l1 flushes and stopped.
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*/
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dcache_wbinv_poc_all();
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/* Indicate we are stopped */
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CPU_SET_ATOMIC(cpu, &stopped_cpus);
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/* Wait for restart */
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while (!CPU_ISSET(cpu, &started_cpus))
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cpu_spinwait();
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CPU_CLR_ATOMIC(cpu, &started_cpus);
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CPU_CLR_ATOMIC(cpu, &stopped_cpus);
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#ifdef DDB
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dbg_resume_dbreg();
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#endif
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CTR0(KTR_SMP, "IPI_STOP (restart)");
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break;
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case IPI_PREEMPT:
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CTR1(KTR_SMP, "%s: IPI_PREEMPT", __func__);
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sched_preempt(curthread);
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break;
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case IPI_HARDCLOCK:
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CTR1(KTR_SMP, "%s: IPI_HARDCLOCK", __func__);
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hardclockintr();
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break;
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default:
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panic("Unknown IPI 0x%0x on cpu %d", ipi, curcpu);
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}
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pic_ipi_clear(ipi);
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ipi = pic_ipi_read(-1);
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}
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return (FILTER_HANDLED);
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}
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#endif
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static void
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release_aps(void *dummy __unused)
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{
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uint32_t loop_counter;
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#ifndef INTRNG
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int start = 0, end = 0;
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#endif
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if (mp_ncpus == 1)
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return;
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#ifdef INTRNG
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intr_pic_ipi_setup(IPI_RENDEZVOUS, "rendezvous", ipi_rendezvous, NULL);
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intr_pic_ipi_setup(IPI_AST, "ast", ipi_ast, NULL);
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intr_pic_ipi_setup(IPI_STOP, "stop", ipi_stop, NULL);
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intr_pic_ipi_setup(IPI_PREEMPT, "preempt", ipi_preempt, NULL);
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intr_pic_ipi_setup(IPI_HARDCLOCK, "hardclock", ipi_hardclock, NULL);
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#else
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#ifdef IPI_IRQ_START
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start = IPI_IRQ_START;
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#ifdef IPI_IRQ_END
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end = IPI_IRQ_END;
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#else
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end = IPI_IRQ_START;
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#endif
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#endif
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for (int i = start; i <= end; i++) {
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/*
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* IPI handler
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*/
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/*
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* Use 0xdeadbeef as the argument value for irq 0,
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* if we used 0, the intr code will give the trap frame
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* pointer instead.
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*/
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arm_setup_irqhandler("ipi", ipi_handler, NULL, (void *)i, i,
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INTR_TYPE_MISC | INTR_EXCL, NULL);
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/* Enable ipi */
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arm_unmask_irq(i);
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}
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#endif
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atomic_store_rel_int(&aps_ready, 1);
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/* Wake the other threads up */
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dsb();
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@ -507,11 +379,7 @@ ipi_all_but_self(u_int ipi)
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other_cpus = all_cpus;
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CPU_CLR(PCPU_GET(cpuid), &other_cpus);
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CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
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#ifdef INTRNG
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intr_ipi_send(other_cpus, ipi);
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#else
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pic_ipi_send(other_cpus, ipi);
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#endif
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}
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void
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@ -523,11 +391,7 @@ ipi_cpu(int cpu, u_int ipi)
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CPU_SET(cpu, &cpus);
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CTR3(KTR_SMP, "%s: cpu: %d, ipi: %x", __func__, cpu, ipi);
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#ifdef INTRNG
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intr_ipi_send(cpus, ipi);
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#else
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pic_ipi_send(cpus, ipi);
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#endif
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}
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void
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@ -535,9 +399,5 @@ ipi_selected(cpuset_t cpus, u_int ipi)
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{
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CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
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#ifdef INTRNG
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intr_ipi_send(cpus, ipi);
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#else
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pic_ipi_send(cpus, ipi);
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#endif
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}
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@ -6,7 +6,6 @@
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#include <sys/_cpuset.h>
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#include <machine/pcb.h>
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#ifdef INTRNG
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enum {
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IPI_AST,
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IPI_PREEMPT,
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@ -18,16 +17,6 @@ enum {
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IPI_CACHE, /* Not used now, but keep it reserved. */
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INTR_IPI_COUNT
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};
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#else
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#define IPI_AST 0
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#define IPI_PREEMPT 2
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#define IPI_RENDEZVOUS 3
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#define IPI_STOP 4
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#define IPI_STOP_HARD 4
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#define IPI_HARDCLOCK 6
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#define IPI_TLB 7 /* Not used now, but keep it reserved. */
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#define IPI_CACHE 8 /* Not used now, but keep it reserved. */
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#endif /* INTRNG */
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void init_secondary(int cpu);
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void mpentry(void);
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@ -36,13 +25,6 @@ void ipi_all_but_self(u_int ipi);
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void ipi_cpu(int cpu, u_int ipi);
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void ipi_selected(cpuset_t cpus, u_int ipi);
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/* PIC interface */
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#ifndef INTRNG
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void pic_ipi_send(cpuset_t cpus, u_int ipi);
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void pic_ipi_clear(int ipi);
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int pic_ipi_read(int arg);
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#endif
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/* Platform interface */
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void platform_mp_setmaxid(void);
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void platform_mp_start_ap(void);
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@ -23,8 +23,6 @@ EFI opt_platform.h
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FLASHADDR opt_global.h
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GIC_DEFAULT_ICFGR_INIT opt_global.h
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INTRNG opt_global.h
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IPI_IRQ_START opt_smp.h
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IPI_IRQ_END opt_smp.h
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FREEBSD_BOOT_LOADER opt_global.h
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KERNBASE opt_global.h
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KERNVIRTADDR opt_global.h
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