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Removed original distribution files that are no longer valid.
This commit is contained in:
Nate Williams
parent
bd063a9d88
commit
17139567a0
@ -1,11 +0,0 @@
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Original work is copyright (C) Andrew McRae 1994,1995
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Permission is granted to freely copy as long as
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all attribution remains and copyright notices are
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included, and source made available upon request.
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Parts of this distribution is derived from work
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by Barry Jaspan and Keith Moore.
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DISCLAIMER:
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There is no warranty for this software.
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All responsibility is your own.
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@ -1,12 +0,0 @@
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The files are:
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enabler Sample enabler for connecting drivers
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dumpcis Reads and dumps CIS of card.
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pccardmem Sets a memory area for use by the driver
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rdmap Dumps the current memory and I/O card contexts
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rdreg reads a PCIC register
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wrreg Writes a PCIC register
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wrattr Writes a byte into the card's attribute area.
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The cardd stuff has been updated for the new interfaces, but
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hasn't been tested to any real extent.
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@ -1,34 +0,0 @@
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INSTALLATION
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------------
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1. Copy the source files from the sys directory into your
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/sys (or where-ever) tree. There are a number of .diff files
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that can be used to modify the following files:
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sys/conf/files
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sys/i386/i386/autoconf.c
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sys/i386/i386/conf.c
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There is also a sys/pccard directory that should reside in
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/sys/pccard
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2. Make a symbolic link like:
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ln -s /sys/pccard /usr/include/pccard
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3. Add a line in the kernel config file:
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controller crd0
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and rebuild the kernel. Optionally, the PCIC slot driver can
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and also built into the kernel by adding the line:
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device pcic0
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4. Create a device for each slot e.g.
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foreach i (0 1)
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mknod /dev/card$i c 50 $i
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end
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5. You can use lkm to load the PCIC controller. It can
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be unloaded at will. Once loaded, you should assign
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some memory via pccardmem for use with read/write.
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Normally cardd does this, but I haven't quite finished yet.
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@ -1,32 +0,0 @@
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#
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# Makefile for PCMCIA card programs.
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#
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CFLAGS = -m486 -g # -DDEBUG
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PROGS = dumpcis rdmap rdreg wrreg pccardmem wrattr enabler
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all: $(PROGS)
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clean:
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rm -f *.core core *.o $(PROGS)
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dumpcis: dumpcis.o readcis.o printcis.o
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cc -o dumpcis -static dumpcis.o readcis.o printcis.o
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wrattr: wrattr.c
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cc $(CFLAGS) -o wrattr wrattr.c
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pccardmem: pccardmem.c
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cc $(CFLAGS) -o pccardmem pccardmem.c
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enabler: enabler.c
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cc $(CFLAGS) -o enabler enabler.c
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rdmap: rdmap.c
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cc $(CFLAGS) -o rdmap rdmap.c
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rdreg: rdreg.c
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cc $(CFLAGS) -o rdreg rdreg.c
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wrreg: wrreg.c
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cc $(CFLAGS) -o wrreg wrreg.c
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@ -1,62 +0,0 @@
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PCMCIA Support for FreeBSD 2.0
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------------------------------
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This package contains the following:
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- Driver for Intel 83265 PCIC PCMCIA controller
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- A PCMCIA daemon for managing card insertions/removals
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- Diffs to various source files for adding PCMCIA support
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- A sample config file
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- Some utility programs for reading card data tuples
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- Some documentation.
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What it doesn't include is:
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- Configuration for brand XYZ PCMCIA cards
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- Drivers for brand XYZ PCMCIA cards
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- Diffs to modify standard drivers to handle card events
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Essentially, this package contains everything required to
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add PCMCIA support to FreeBSD 2.0. It does this via a
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daemon that manages the PCMCIA slots via a PCIC driver. A configuration
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file provides the daemon with the information required to setup
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the specific cards, and to manage card insertion and removal.
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This package has been tested on a NEC Versa Laptop.
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The first version was developed on FreeBSD 1.1.5.1.
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The main idea behind the package is for pcmciad to detect
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inserted cards and match to a card ID in the config file,
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then set up the I/O ports and memory window to the card
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according to the data for the driver associated with the
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card, then attach the kernel driver to the device. Shell
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commands can be executed for both insertion and removal of cards,
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and different commands can be executed for different cards,
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drivers and devices.
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Different kernel drivers may have to have some mods
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done to recognise the card once installed; I have included
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some diffs to `ed' that allows recognition of a `generic'
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NS8390 card.
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Some minor changes were made to ifconfig(8) to allow a
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different ethernet address to be assigned to a network
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interface, since each card may have different locations
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the ethernet address is stored in.
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This is a snapshot of a release for FreeBSD 2.0. It is
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basically the 1.1.5.1 release ported for 2.0. I have only
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just received a developer's guide for PCMCIA, so I should
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have some more stable support soon.
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For instructions on installation, see INSTALL.
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There is a man entry on the daemon (pcmciad.8),
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and the config file (pcmcia.conf.5).
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Please send mail with any bugs or new card descriptions.
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Enjoy!
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Andrew McRae inet: andrew@mega.com.au
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MITS Real Time Ltd, uucp: ..!uunet!mega.com.au!andrew
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North Ryde 2113 Phone: +61 2 805 0899
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NSW AUSTRALIA Fax: +61 2 887 4847
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@ -1,113 +0,0 @@
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/*
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* Enabler for PCCARD. Used for testing drivers etc.
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* Options:
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* enabler slot driver [ -m card addr size ] [ -i iobase ] [ -q irq ]
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*/
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#include <stdio.h>
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#include <unistd.h>
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#include <stdlib.h>
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#include <string.h>
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#include <sys/ioctl.h>
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#include <pccard/card.h>
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#include <pccard/cis.h>
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void usage();
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main(argc, argv)
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int argc;
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char *argv[];
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{
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struct drv_desc drv;
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struct mem_desc mem;
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struct io_desc io;
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int fd, err, slot, i, card_addr;
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char name[32], cmd[256];
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char *p;
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if (argc == 2)
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slot = atoi(argv[1]);
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else
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slot = 0;
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if (slot < 0 || slot >= MAXSLOT)
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usage("Illegal slot number");
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sprintf(cmd, "util/wrattr %d 100 80", slot);
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printf("%s\n", cmd);
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system(cmd);
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usleep(200*1000);
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sprintf(cmd, "util/wrattr %d 100 0", slot);
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printf("%s\n", cmd);
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system(cmd);
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usleep(200*1000);
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sprintf(cmd, "util/wrattr %d 100 30", slot);
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printf("%s\n", cmd);
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system(cmd);
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usleep(200*1000);
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bzero(&drv, sizeof(drv));
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drv.unit = 0;
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strcpy(drv.name, "ed");
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drv.irqmask = 1 << 5;
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sprintf(name, "/dev/card%d", slot);
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fd = open(name, 2);
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if (fd < 0)
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{
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perror(name);
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exit(1);
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}
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/*
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* Map the memory and I/O contexts.
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*/
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drv.mem = 0xD4000;
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if (drv.mem)
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{
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mem.window = 0;
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mem.flags = MDF_ACTIVE;
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mem.start = (caddr_t)drv.mem;
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mem.size = 16*1024;
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mem.card = 0x4000;
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if (ioctl(fd, PIOCSMEM, &mem))
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{
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perror("Set memory context");
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exit(1);
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}
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}
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drv.iobase = 0x300;
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if (drv.iobase)
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{
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io.window = 0;
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io.flags = IODF_ACTIVE|IODF_CS16|IODF_WS;
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io.start = drv.iobase;
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io.size = 32; /* Blah... */
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if (ioctl(fd, PIOCSIO, &io))
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{
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perror("Set I/O context");
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exit(1);
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}
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#ifdef 0
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io.window = 1;
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io.flags = IODF_ACTIVE|IODF_16BIT;
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io.start = drv.iobase+16;
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io.size = 16; /* Blah... */
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if (ioctl(fd, PIOCSIO, &io))
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{
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perror("Set I/O context");
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exit(1);
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}
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#endif
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}
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if (ioctl(fd, PIOCSDRV, &drv))
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perror("set driver");
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close(fd);
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}
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/*
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* usage - print usage and exit
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*/
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void
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usage(msg)
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char *msg;
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{
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fprintf(stderr, "rpti: %s\n", msg);
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fprintf(stderr, "Usage: rpti slot driver\n");
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exit(1);
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}
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@ -1,37 +0,0 @@
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#include <stdio.h>
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#include <unistd.h>
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#include <stdlib.h>
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#include <string.h>
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#include <sys/ioctl.h>
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#include <pccard/card.h>
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#include <pccard/cis.h>
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main(argc, argv)
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int argc;
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char *argv[];
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{
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struct drv_desc drv;
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int fd, err;
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fd = open("/dev/card0", 0);
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if (fd < 0)
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{
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perror("/dev/card0");
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exit(1);
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}
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strcpy(drv.name, "skel");
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if (argc == 2)
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drv.unit = atoi(argv[1]);
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else
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drv.unit = 0;
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drv.iobase = 0x300;
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drv.mem = 0xD4000;
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drv.memsize = 16*1024;
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drv.irq = 0xFFFF;
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drv.flags = 0x1234;
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if (ioctl(fd, PIOCSDRV, &drv))
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perror("set driver");
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close(fd);
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}
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@ -1,63 +0,0 @@
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#
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# GENERIC -- Generic machine with WD/AHx/NCR/BTx family disks
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#
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# GENERIC,v 1.20 1994/11/18 19:10:25 jkh Exp
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#
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machine "i386"
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cpu "I386_CPU"
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cpu "I486_CPU"
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cpu "I586_CPU"
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ident LAPTOP
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maxusers 4
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options MATH_EMULATE #Support for x87 emulation
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options INET #InterNETworking
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options FFS #Berkeley Fast Filesystem
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options NFS #Network Filesystem
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options MSDOSFS #MSDOS Filesystem
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options PROCFS #Process filesystem
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options "COMPAT_43" #Compatible with BSD 4.3
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options UCONSOLE #X Console support
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options "FAT_CURSOR" #block cursor in syscons or pccons
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options "NCONS=4" #4 virtual consoles
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options ALLOW_CONFLICT_IOADDR
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options PSM_NO_RESET
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config kernel root on wd0 swap on wd0 and wd1 and sd0 and sd1 dumps on wd0
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controller crd0
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#device pcic0
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controller isa0
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controller fdc0 at isa? port "IO_FD1" bio irq 6 drq 2 vector fdintr
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disk fd0 at fdc0 drive 0
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controller wdc0 at isa? port "IO_WD1" bio irq 14 vector wdintr
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disk wd0 at wdc0 drive 0
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device sc0 at isa? port "IO_KBD" tty irq 1 vector scintr
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device npx0 at isa? port "IO_NPX" irq 13 vector npxintr
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device psm0 at isa? port "IO_KBD" tty irq 12 vector psmintr
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#device pcic0 at isa? port 0x3E0 tty irq 3 iomem 0xd0000
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device sio0 at isa? port "IO_COM1" tty irq 4 vector siointr
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device sio1 at isa? port "IO_COM2" tty irq 10 vector siointr
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#device sio1 at isa? port "IO_COM2" tty flags 0x80 irq 10 vector siointr
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device lpt0 at isa? port? tty irq 7 vector lptintr
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#device ed0 at isa? port 0x300 net flags 0x20 irq 5 iomem 0xd4000 vector edintr
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device apm0 at isa?
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pseudo-device loop
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pseudo-device ether
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pseudo-device log
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pseudo-device sl 2
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pseudo-device pty 16
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pseudo-device speaker
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pseudo-device gzip # Exec gzipped a.out's
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@ -1,25 +0,0 @@
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all: pcic.o ed.o
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CFLAGS = -O -DINET -DKERNEL -DLKM -I/sys
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pcic.o: pcic.c
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cc -c $(CFLAGS) pcic.c
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load: pcic.o
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modload -e lkm_pcic pcic.o
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pccardmem d0000
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unload:
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modunload -n pcic
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skel.o: skel.c
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cc -c $(CFLAGS) skel.c
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ldskel: skel.o
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modload -e lkm_skel skel.o
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ed.o: if_ed.o lkm_ed.o
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ld -r -o ed.o if_ed.o lkm_ed.o
|
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lded: ed.o
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modload -e lkm_ed ed.o
|
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@ -1,13 +0,0 @@
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This directory contains:
|
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|
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card.h Include file for driver interface
|
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cis.h CIS defines
|
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slot.h Kernel interface for card/slot driver/devices interface
|
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i82365.h Defines for PCIC device
|
||||
|
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pccard.c Mainline PC-Card support functions (card services).
|
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pcic.c PCIC or compatible slot driver (loadable).
|
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skel.c Skeleton loadable driver interfacing to card services.
|
||||
|
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The other files are working copies of drivers.
|
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@ -1 +0,0 @@
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#define NBPFILTER 0
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@ -1 +0,0 @@
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#define NED 2
|
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File diff suppressed because it is too large
Load Diff
@ -1,989 +0,0 @@
|
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/*
|
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* Copyright (C) 1993, David Greenman. This software may be used, modified,
|
||||
* copied, distributed, and sold, in both source and binary form provided
|
||||
* that the above copyright and these terms are retained. Under no
|
||||
* circumstances is the author responsible for the proper functioning
|
||||
* of this software, nor does the author assume any responsibility
|
||||
* for damages incurred with its use.
|
||||
*
|
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* $Id: if_edreg.h,v 1.17 1995/01/23 19:06:08 davidg Exp $
|
||||
*/
|
||||
/*
|
||||
* National Semiconductor DS8390 NIC register definitions
|
||||
*
|
||||
*
|
||||
* Modification history
|
||||
*
|
||||
* Revision 2.2 1993/11/29 16:33:39 davidg
|
||||
* From Thomas Sandford <t.d.g.sandford@comp.brad.ac.uk>
|
||||
* Add support for the 8013W board type
|
||||
*
|
||||
* Revision 2.1 1993/11/22 10:52:33 davidg
|
||||
* patch to add support for SMC8216 (Elite-Ultra) boards
|
||||
* from Glen H. Lowe
|
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*
|
||||
* Revision 2.0 93/09/29 00:37:15 davidg
|
||||
* changed double buffering flag to multi buffering
|
||||
* made changes/additions for 3c503 multi-buffering
|
||||
* ...companion to Rev. 2.0 of 'ed' driver.
|
||||
*
|
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* Revision 1.1 93/06/23 03:01:07 davidg
|
||||
* Initial revision
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
* Page 0 register offsets
|
||||
*/
|
||||
#define ED_P0_CR 0x00 /* Command Register */
|
||||
|
||||
#define ED_P0_CLDA0 0x01 /* Current Local DMA Addr low (read) */
|
||||
#define ED_P0_PSTART 0x01 /* Page Start register (write) */
|
||||
|
||||
#define ED_P0_CLDA1 0x02 /* Current Local DMA Addr high (read) */
|
||||
#define ED_P0_PSTOP 0x02 /* Page Stop register (write) */
|
||||
|
||||
#define ED_P0_BNRY 0x03 /* Boundary Pointer */
|
||||
|
||||
#define ED_P0_TSR 0x04 /* Transmit Status Register (read) */
|
||||
#define ED_P0_TPSR 0x04 /* Transmit Page Start (write) */
|
||||
|
||||
#define ED_P0_NCR 0x05 /* Number of Collisions Reg (read) */
|
||||
#define ED_P0_TBCR0 0x05 /* Transmit Byte count, low (write) */
|
||||
|
||||
#define ED_P0_FIFO 0x06 /* FIFO register (read) */
|
||||
#define ED_P0_TBCR1 0x06 /* Transmit Byte count, high (write) */
|
||||
|
||||
#define ED_P0_ISR 0x07 /* Interrupt Status Register */
|
||||
|
||||
#define ED_P0_CRDA0 0x08 /* Current Remote DMA Addr low (read) */
|
||||
#define ED_P0_RSAR0 0x08 /* Remote Start Address low (write) */
|
||||
|
||||
#define ED_P0_CRDA1 0x09 /* Current Remote DMA Addr high (read) */
|
||||
#define ED_P0_RSAR1 0x09 /* Remote Start Address high (write) */
|
||||
|
||||
#define ED_P0_RBCR0 0x0a /* Remote Byte Count low (write) */
|
||||
|
||||
#define ED_P0_RBCR1 0x0b /* Remote Byte Count high (write) */
|
||||
|
||||
#define ED_P0_RSR 0x0c /* Receive Status (read) */
|
||||
#define ED_P0_RCR 0x0c /* Receive Configuration Reg (write) */
|
||||
|
||||
#define ED_P0_CNTR0 0x0d /* frame alignment error counter (read) */
|
||||
#define ED_P0_TCR 0x0d /* Transmit Configuration Reg (write) */
|
||||
|
||||
#define ED_P0_CNTR1 0x0e /* CRC error counter (read) */
|
||||
#define ED_P0_DCR 0x0e /* Data Configuration Reg (write) */
|
||||
|
||||
#define ED_P0_CNTR2 0x0f /* missed packet counter (read) */
|
||||
#define ED_P0_IMR 0x0f /* Interrupt Mask Register (write) */
|
||||
|
||||
/*
|
||||
* Page 1 register offsets
|
||||
*/
|
||||
#define ED_P1_CR 0x00 /* Command Register */
|
||||
#define ED_P1_PAR0 0x01 /* Physical Address Register 0 */
|
||||
#define ED_P1_PAR1 0x02 /* Physical Address Register 1 */
|
||||
#define ED_P1_PAR2 0x03 /* Physical Address Register 2 */
|
||||
#define ED_P1_PAR3 0x04 /* Physical Address Register 3 */
|
||||
#define ED_P1_PAR4 0x05 /* Physical Address Register 4 */
|
||||
#define ED_P1_PAR5 0x06 /* Physical Address Register 5 */
|
||||
#define ED_P1_CURR 0x07 /* Current RX ring-buffer page */
|
||||
#define ED_P1_MAR0 0x08 /* Multicast Address Register 0 */
|
||||
#define ED_P1_MAR1 0x09 /* Multicast Address Register 1 */
|
||||
#define ED_P1_MAR2 0x0a /* Multicast Address Register 2 */
|
||||
#define ED_P1_MAR3 0x0b /* Multicast Address Register 3 */
|
||||
#define ED_P1_MAR4 0x0c /* Multicast Address Register 4 */
|
||||
#define ED_P1_MAR5 0x0d /* Multicast Address Register 5 */
|
||||
#define ED_P1_MAR6 0x0e /* Multicast Address Register 6 */
|
||||
#define ED_P1_MAR7 0x0f /* Multicast Address Register 7 */
|
||||
|
||||
/*
|
||||
* Page 2 register offsets
|
||||
*/
|
||||
#define ED_P2_CR 0x00 /* Command Register */
|
||||
#define ED_P2_PSTART 0x01 /* Page Start (read) */
|
||||
#define ED_P2_CLDA0 0x01 /* Current Local DMA Addr 0 (write) */
|
||||
#define ED_P2_PSTOP 0x02 /* Page Stop (read) */
|
||||
#define ED_P2_CLDA1 0x02 /* Current Local DMA Addr 1 (write) */
|
||||
#define ED_P2_RNPP 0x03 /* Remote Next Packet Pointer */
|
||||
#define ED_P2_TPSR 0x04 /* Transmit Page Start (read) */
|
||||
#define ED_P2_LNPP 0x05 /* Local Next Packet Pointer */
|
||||
#define ED_P2_ACU 0x06 /* Address Counter Upper */
|
||||
#define ED_P2_ACL 0x07 /* Address Counter Lower */
|
||||
#define ED_P2_RCR 0x0c /* Receive Configuration Register (read) */
|
||||
#define ED_P2_TCR 0x0d /* Transmit Configuration Register (read) */
|
||||
#define ED_P2_DCR 0x0e /* Data Configuration Register (read) */
|
||||
#define ED_P2_IMR 0x0f /* Interrupt Mask Register (read) */
|
||||
|
||||
/*
|
||||
* Command Register (CR) definitions
|
||||
*/
|
||||
|
||||
/*
|
||||
* STP: SToP. Software reset command. Takes the controller offline. No
|
||||
* packets will be received or transmitted. Any reception or
|
||||
* transmission in progress will continue to completion before
|
||||
* entering reset state. To exit this state, the STP bit must
|
||||
* reset and the STA bit must be set. The software reset has
|
||||
* executed only when indicated by the RST bit in the ISR being
|
||||
* set.
|
||||
*/
|
||||
#define ED_CR_STP 0x01
|
||||
|
||||
/*
|
||||
* STA: STArt. This bit is used to activate the NIC after either power-up,
|
||||
* or when the NIC has been put in reset mode by software command
|
||||
* or error.
|
||||
*/
|
||||
#define ED_CR_STA 0x02
|
||||
|
||||
/*
|
||||
* TXP: Transmit Packet. This bit must be set to indicate transmission of
|
||||
* a packet. TXP is internally reset either after the transmission is
|
||||
* completed or aborted. This bit should be set only after the Transmit
|
||||
* Byte Count and Transmit Page Start register have been programmed.
|
||||
*/
|
||||
#define ED_CR_TXP 0x04
|
||||
|
||||
/*
|
||||
* RD0, RD1, RD2: Remote DMA Command. These three bits control the operation
|
||||
* of the remote DMA channel. RD2 can be set to abort any remote DMA
|
||||
* command in progress. The Remote Byte Count registers should be cleared
|
||||
* when a remote DMA has been aborted. The Remote Start Addresses are not
|
||||
* restored to the starting address if the remote DMA is aborted.
|
||||
*
|
||||
* RD2 RD1 RD0 function
|
||||
* 0 0 0 not allowed
|
||||
* 0 0 1 remote read
|
||||
* 0 1 0 remote write
|
||||
* 0 1 1 send packet
|
||||
* 1 X X abort
|
||||
*/
|
||||
#define ED_CR_RD0 0x08
|
||||
#define ED_CR_RD1 0x10
|
||||
#define ED_CR_RD2 0x20
|
||||
|
||||
/*
|
||||
* PS0, PS1: Page Select. The two bits select which register set or 'page' to
|
||||
* access.
|
||||
*
|
||||
* PS1 PS0 page
|
||||
* 0 0 0
|
||||
* 0 1 1
|
||||
* 1 0 2
|
||||
* 1 1 reserved
|
||||
*/
|
||||
#define ED_CR_PS0 0x40
|
||||
#define ED_CR_PS1 0x80
|
||||
/* bit encoded aliases */
|
||||
#define ED_CR_PAGE_0 0x00 /* (for consistency) */
|
||||
#define ED_CR_PAGE_1 0x40
|
||||
#define ED_CR_PAGE_2 0x80
|
||||
|
||||
/*
|
||||
* Interrupt Status Register (ISR) definitions
|
||||
*/
|
||||
|
||||
/*
|
||||
* PRX: Packet Received. Indicates packet received with no errors.
|
||||
*/
|
||||
#define ED_ISR_PRX 0x01
|
||||
|
||||
/*
|
||||
* PTX: Packet Transmitted. Indicates packet transmitted with no errors.
|
||||
*/
|
||||
#define ED_ISR_PTX 0x02
|
||||
|
||||
/*
|
||||
* RXE: Receive Error. Indicates that a packet was received with one or more
|
||||
* the following errors: CRC error, frame alignment error, FIFO overrun,
|
||||
* missed packet.
|
||||
*/
|
||||
#define ED_ISR_RXE 0x04
|
||||
|
||||
/*
|
||||
* TXE: Transmission Error. Indicates that an attempt to transmit a packet
|
||||
* resulted in one or more of the following errors: excessive
|
||||
* collisions, FIFO underrun.
|
||||
*/
|
||||
#define ED_ISR_TXE 0x08
|
||||
|
||||
/*
|
||||
* OVW: OverWrite. Indicates a receive ring-buffer overrun. Incoming network
|
||||
* would exceed (has exceeded?) the boundry pointer, resulting in data
|
||||
* that was previously received and not yet read from the buffer to be
|
||||
* overwritten.
|
||||
*/
|
||||
#define ED_ISR_OVW 0x10
|
||||
|
||||
/*
|
||||
* CNT: Counter Overflow. Set when the MSB of one or more of the Network Talley
|
||||
* Counters has been set.
|
||||
*/
|
||||
#define ED_ISR_CNT 0x20
|
||||
|
||||
/*
|
||||
* RDC: Remote Data Complete. Indicates that a Remote DMA operation has completed.
|
||||
*/
|
||||
#define ED_ISR_RDC 0x40
|
||||
|
||||
/*
|
||||
* RST: Reset status. Set when the NIC enters the reset state and cleared when a
|
||||
* Start Command is issued to the CR. This bit is also set when a receive
|
||||
* ring-buffer overrun (OverWrite) occurs and is cleared when one or more
|
||||
* packets have been removed from the ring. This is a read-only bit.
|
||||
*/
|
||||
#define ED_ISR_RST 0x80
|
||||
|
||||
/*
|
||||
* Interrupt Mask Register (IMR) definitions
|
||||
*/
|
||||
|
||||
/*
|
||||
* PRXE: Packet Received interrupt Enable. If set, a received packet will cause
|
||||
* an interrupt.
|
||||
*/
|
||||
#define ED_IMR_PRXE 0x01
|
||||
|
||||
/*
|
||||
* PTXE: Packet Transmit interrupt Enable. If set, an interrupt is generated when
|
||||
* a packet transmission completes.
|
||||
*/
|
||||
#define ED_IMR_PTXE 0x02
|
||||
|
||||
/*
|
||||
* RXEE: Receive Error interrupt Enable. If set, an interrupt will occur whenever a
|
||||
* packet is received with an error.
|
||||
*/
|
||||
#define ED_IMR_RXEE 0x04
|
||||
|
||||
/*
|
||||
* TXEE: Transmit Error interrupt Enable. If set, an interrupt will occur whenever
|
||||
* a transmission results in an error.
|
||||
*/
|
||||
#define ED_IMR_TXEE 0x08
|
||||
|
||||
/*
|
||||
* OVWE: OverWrite error interrupt Enable. If set, an interrupt is generated whenever
|
||||
* the receive ring-buffer is overrun. i.e. when the boundry pointer is exceeded.
|
||||
*/
|
||||
#define ED_IMR_OVWE 0x10
|
||||
|
||||
/*
|
||||
* CNTE: Counter overflow interrupt Enable. If set, an interrupt is generated whenever
|
||||
* the MSB of one or more of the Network Statistics counters has been set.
|
||||
*/
|
||||
#define ED_IMR_CNTE 0x20
|
||||
|
||||
/*
|
||||
* RDCE: Remote DMA Complete interrupt Enable. If set, an interrupt is generated
|
||||
* when a remote DMA transfer has completed.
|
||||
*/
|
||||
#define ED_IMR_RDCE 0x40
|
||||
|
||||
/*
|
||||
* bit 7 is unused/reserved
|
||||
*/
|
||||
|
||||
/*
|
||||
* Data Configuration Register (DCR) definitions
|
||||
*/
|
||||
|
||||
/*
|
||||
* WTS: Word Transfer Select. WTS establishes byte or word transfers for
|
||||
* both remote and local DMA transfers
|
||||
*/
|
||||
#define ED_DCR_WTS 0x01
|
||||
|
||||
/*
|
||||
* BOS: Byte Order Select. BOS sets the byte order for the host.
|
||||
* Should be 0 for 80x86, and 1 for 68000 series processors
|
||||
*/
|
||||
#define ED_DCR_BOS 0x02
|
||||
|
||||
/*
|
||||
* LAS: Long Address Select. When LAS is 1, the contents of the remote
|
||||
* DMA registers RSAR0 and RSAR1 are used to provide A16-A31
|
||||
*/
|
||||
#define ED_DCR_LAS 0x04
|
||||
|
||||
/*
|
||||
* LS: Loopback Select. When 0, loopback mode is selected. Bits D1 and D2
|
||||
* of the TCR must also be programmed for loopback operation.
|
||||
* When 1, normal operation is selected.
|
||||
*/
|
||||
#define ED_DCR_LS 0x08
|
||||
|
||||
/*
|
||||
* AR: Auto-initialize Remote. When 0, data must be removed from ring-buffer
|
||||
* under program control. When 1, remote DMA is automatically initiated
|
||||
* and the boundry pointer is automatically updated
|
||||
*/
|
||||
#define ED_DCR_AR 0x10
|
||||
|
||||
/*
|
||||
* FT0, FT1: Fifo Threshold select.
|
||||
* FT1 FT0 Word-width Byte-width
|
||||
* 0 0 1 word 2 bytes
|
||||
* 0 1 2 words 4 bytes
|
||||
* 1 0 4 words 8 bytes
|
||||
* 1 1 8 words 12 bytes
|
||||
*
|
||||
* During transmission, the FIFO threshold indicates the number of bytes
|
||||
* or words that the FIFO has filled from the local DMA before BREQ is
|
||||
* asserted. The transmission threshold is 16 bytes minus the receiver
|
||||
* threshold.
|
||||
*/
|
||||
#define ED_DCR_FT0 0x20
|
||||
#define ED_DCR_FT1 0x40
|
||||
|
||||
/*
|
||||
* bit 7 (0x80) is unused/reserved
|
||||
*/
|
||||
|
||||
/*
|
||||
* Transmit Configuration Register (TCR) definitions
|
||||
*/
|
||||
|
||||
/*
|
||||
* CRC: Inhibit CRC. If 0, CRC will be appended by the transmitter, if 0, CRC
|
||||
* is not appended by the transmitter.
|
||||
*/
|
||||
#define ED_TCR_CRC 0x01
|
||||
|
||||
/*
|
||||
* LB0, LB1: Loopback control. These two bits set the type of loopback that is
|
||||
* to be performed.
|
||||
*
|
||||
* LB1 LB0 mode
|
||||
* 0 0 0 - normal operation (DCR_LS = 0)
|
||||
* 0 1 1 - internal loopback (DCR_LS = 0)
|
||||
* 1 0 2 - external loopback (DCR_LS = 1)
|
||||
* 1 1 3 - external loopback (DCR_LS = 0)
|
||||
*/
|
||||
#define ED_TCR_LB0 0x02
|
||||
#define ED_TCR_LB1 0x04
|
||||
|
||||
/*
|
||||
* ATD: Auto Transmit Disable. Clear for normal operation. When set, allows
|
||||
* another station to disable the NIC's transmitter by transmitting to
|
||||
* a multicast address hashing to bit 62. Reception of a multicast address
|
||||
* hashing to bit 63 enables the transmitter.
|
||||
*/
|
||||
#define ED_TCR_ATD 0x08
|
||||
|
||||
/*
|
||||
* OFST: Collision Offset enable. This bit when set modifies the backoff
|
||||
* algorithm to allow prioritization of nodes.
|
||||
*/
|
||||
#define ED_TCR_OFST 0x10
|
||||
|
||||
/*
|
||||
* bits 5, 6, and 7 are unused/reserved
|
||||
*/
|
||||
|
||||
/*
|
||||
* Transmit Status Register (TSR) definitions
|
||||
*/
|
||||
|
||||
/*
|
||||
* PTX: Packet Transmitted. Indicates successful transmission of packet.
|
||||
*/
|
||||
#define ED_TSR_PTX 0x01
|
||||
|
||||
/*
|
||||
* bit 1 (0x02) is unused/reserved
|
||||
*/
|
||||
|
||||
/*
|
||||
* COL: Transmit Collided. Indicates that the transmission collided at least
|
||||
* once with another station on the network.
|
||||
*/
|
||||
#define ED_TSR_COL 0x04
|
||||
|
||||
/*
|
||||
* ABT: Transmit aborted. Indicates that the transmission was aborted due to
|
||||
* excessive collisions.
|
||||
*/
|
||||
#define ED_TSR_ABT 0x08
|
||||
|
||||
/*
|
||||
* CRS: Carrier Sense Lost. Indicates that carrier was lost during the
|
||||
* transmission of the packet. (Transmission is not aborted because
|
||||
* of a loss of carrier)
|
||||
*/
|
||||
#define ED_TSR_CRS 0x10
|
||||
|
||||
/*
|
||||
* FU: FIFO Underrun. Indicates that the NIC wasn't able to access bus/
|
||||
* transmission memory before the FIFO emptied. Transmission of the
|
||||
* packet was aborted.
|
||||
*/
|
||||
#define ED_TSR_FU 0x20
|
||||
|
||||
/*
|
||||
* CDH: CD Heartbeat. Indicates that the collision detection circuitry
|
||||
* isn't working correctly during a collision heartbeat test.
|
||||
*/
|
||||
#define ED_TSR_CDH 0x40
|
||||
|
||||
/*
|
||||
* OWC: Out of Window Collision: Indicates that a collision occurred after
|
||||
* a slot time (51.2us). The transmission is rescheduled just as in
|
||||
* normal collisions.
|
||||
*/
|
||||
#define ED_TSR_OWC 0x80
|
||||
|
||||
/*
|
||||
* Receiver Configuration Register (RCR) definitions
|
||||
*/
|
||||
|
||||
/*
|
||||
* SEP: Save Errored Packets. If 0, error packets are discarded. If set to 1,
|
||||
* packets with CRC and frame errors are not discarded.
|
||||
*/
|
||||
#define ED_RCR_SEP 0x01
|
||||
|
||||
/*
|
||||
* AR: Accept Runt packet. If 0, packet with less than 64 byte are discarded.
|
||||
* If set to 1, packets with less than 64 byte are not discarded.
|
||||
*/
|
||||
#define ED_RCR_AR 0x02
|
||||
|
||||
/*
|
||||
* AB: Accept Broadcast. If set, packets sent to the broadcast address will be
|
||||
* accepted.
|
||||
*/
|
||||
#define ED_RCR_AB 0x04
|
||||
|
||||
/*
|
||||
* AM: Accept Multicast. If set, packets sent to a multicast address are checked
|
||||
* for a match in the hashing array. If clear, multicast packets are ignored.
|
||||
*/
|
||||
#define ED_RCR_AM 0x08
|
||||
|
||||
/*
|
||||
* PRO: Promiscuous Physical. If set, all packets with a physical addresses are
|
||||
* accepted. If clear, a physical destination address must match this
|
||||
* station's address. Note: for full promiscuous mode, RCR_AB and RCR_AM
|
||||
* must also be set. In addition, the multicast hashing array must be set
|
||||
* to all 1's so that all multicast addresses are accepted.
|
||||
*/
|
||||
#define ED_RCR_PRO 0x10
|
||||
|
||||
/*
|
||||
* MON: Monitor Mode. If set, packets will be checked for good CRC and framing,
|
||||
* but are not stored in the ring-buffer. If clear, packets are stored (normal
|
||||
* operation).
|
||||
*/
|
||||
#define ED_RCR_MON 0x20
|
||||
|
||||
/*
|
||||
* bits 6 and 7 are unused/reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Receiver Status Register (RSR) definitions
|
||||
*/
|
||||
|
||||
/*
|
||||
* PRX: Packet Received without error.
|
||||
*/
|
||||
#define ED_RSR_PRX 0x01
|
||||
|
||||
/*
|
||||
* CRC: CRC error. Indicates that a packet has a CRC error. Also set for frame
|
||||
* alignment errors.
|
||||
*/
|
||||
#define ED_RSR_CRC 0x02
|
||||
|
||||
/*
|
||||
* FAE: Frame Alignment Error. Indicates that the incoming packet did not end on
|
||||
* a byte boundry and the CRC did not match at the last byte boundry.
|
||||
*/
|
||||
#define ED_RSR_FAE 0x04
|
||||
|
||||
/*
|
||||
* FO: FIFO Overrun. Indicates that the FIFO was not serviced (during local DMA)
|
||||
* causing it to overrun. Reception of the packet is aborted.
|
||||
*/
|
||||
#define ED_RSR_FO 0x08
|
||||
|
||||
/*
|
||||
* MPA: Missed Packet. Indicates that the received packet couldn't be stored in
|
||||
* the ring-buffer because of insufficient buffer space (exceeding the
|
||||
* boundry pointer), or because the transfer to the ring-buffer was inhibited
|
||||
* by RCR_MON - monitor mode.
|
||||
*/
|
||||
#define ED_RSR_MPA 0x10
|
||||
|
||||
/*
|
||||
* PHY: Physical address. If 0, the packet received was sent to a physical address.
|
||||
* If 1, the packet was accepted because of a multicast/broadcast address
|
||||
* match.
|
||||
*/
|
||||
#define ED_RSR_PHY 0x20
|
||||
|
||||
/*
|
||||
* DIS: Receiver Disabled. Set to indicate that the receiver has enetered monitor
|
||||
* mode. Cleared when the receiver exits monitor mode.
|
||||
*/
|
||||
#define ED_RSR_DIS 0x40
|
||||
|
||||
/*
|
||||
* DFR: Deferring. Set to indicate a 'jabber' condition. The CRS and COL inputs
|
||||
* are active, and the transceiver has set the CD line as a result of the
|
||||
* jabber.
|
||||
*/
|
||||
#define ED_RSR_DFR 0x80
|
||||
|
||||
/*
|
||||
* receive ring discriptor
|
||||
*
|
||||
* The National Semiconductor DS8390 Network interface controller uses
|
||||
* the following receive ring headers. The way this works is that the
|
||||
* memory on the interface card is chopped up into 256 bytes blocks.
|
||||
* A contiguous portion of those blocks are marked for receive packets
|
||||
* by setting start and end block #'s in the NIC. For each packet that
|
||||
* is put into the receive ring, one of these headers (4 bytes each) is
|
||||
* tacked onto the front. The first byte is a copy of the receiver status
|
||||
* register at the time the packet was received.
|
||||
*/
|
||||
struct ed_ring {
|
||||
u_char rsr; /* receiver status */
|
||||
u_char next_packet; /* pointer to next packet */
|
||||
u_short count; /* bytes in packet (length + 4) */
|
||||
};
|
||||
|
||||
/*
|
||||
* Common constants
|
||||
*/
|
||||
#define ED_PAGE_SIZE 256 /* Size of RAM pages in bytes */
|
||||
#define ED_TXBUF_SIZE 6 /* Size of TX buffer in pages */
|
||||
|
||||
/*
|
||||
* Vendor types
|
||||
*/
|
||||
#define ED_VENDOR_WD_SMC 0x00 /* Western Digital/SMC */
|
||||
#define ED_VENDOR_3COM 0x01 /* 3Com */
|
||||
#define ED_VENDOR_NOVELL 0x02 /* Novell */
|
||||
#define ED_VENDOR_PCMCIA 0x03 /* Generic pcmcia */
|
||||
|
||||
/*
|
||||
* Compile-time config flags
|
||||
*/
|
||||
/*
|
||||
* this sets the default for enabling/disablng the tranceiver
|
||||
*/
|
||||
#define ED_FLAGS_DISABLE_TRANCEIVER 0x0001
|
||||
|
||||
/*
|
||||
* This forces the board to be used in 8/16bit mode even if it
|
||||
* autoconfigs differently
|
||||
*/
|
||||
#define ED_FLAGS_FORCE_8BIT_MODE 0x0002
|
||||
#define ED_FLAGS_FORCE_16BIT_MODE 0x0004
|
||||
|
||||
/*
|
||||
* This disables the use of double transmit buffers.
|
||||
*/
|
||||
#define ED_FLAGS_NO_MULTI_BUFFERING 0x0008
|
||||
|
||||
/*
|
||||
* This forces all operations with the NIC memory to use Programmed
|
||||
* I/O (i.e. not via shared memory)
|
||||
*/
|
||||
#define ED_FLAGS_FORCE_PIO 0x0010
|
||||
|
||||
/*
|
||||
* Definitions for Western digital/SMC WD80x3 series ASIC
|
||||
*/
|
||||
/*
|
||||
* Memory Select Register (MSR)
|
||||
*/
|
||||
#define ED_WD_MSR 0
|
||||
|
||||
/* next three definitions for Toshiba */
|
||||
#define ED_WD_MSR_POW 0x02 /* 0 = power save, 1 = normal (R/W) */
|
||||
#define ED_WD_MSR_BSY 0x04 /* gate array busy (R) */
|
||||
#define ED_WD_MSR_LEN 0x20 /* data bus width, 0 = 16 bits,
|
||||
1 = 8 bits (R/W) */
|
||||
#define ED_WD_MSR_ADDR 0x3f /* Memory decode bits 18-13 */
|
||||
#define ED_WD_MSR_MENB 0x40 /* Memory enable */
|
||||
#define ED_WD_MSR_RST 0x80 /* Reset board */
|
||||
|
||||
/*
|
||||
* Interface Configuration Register (ICR)
|
||||
*/
|
||||
#define ED_WD_ICR 1
|
||||
|
||||
#define ED_WD_ICR_16BIT 0x01 /* 16-bit interface */
|
||||
#define ED_WD_ICR_OAR 0x02 /* select register. 0=BIO 1=EAR */
|
||||
#define ED_WD_ICR_IR2 0x04 /* high order bit of encoded IRQ */
|
||||
#define ED_WD_ICR_MSZ 0x08 /* memory size (0=8k 1=32k) */
|
||||
#define ED_WD_ICR_RLA 0x10 /* recall LAN address */
|
||||
#define ED_WD_ICR_RX7 0x20 /* recall all but i/o and LAN address */
|
||||
#define ED_WD_ICR_RIO 0x40 /* recall i/o address */
|
||||
#define ED_WD_ICR_STO 0x80 /* store to non-volatile memory */
|
||||
#ifdef TOSH_ETHER
|
||||
#define ED_WD_ICR_MEM 0xe0 /* shared mem address A15-A13 (R/W) */
|
||||
#define ED_WD_ICR_MSZ1 0x0f /* memory size, 0x08 = 64K, 0x04 = 32K,
|
||||
0x02 = 16K, 0x01 = 8K */
|
||||
/* 64K can only be used if mem address
|
||||
above 1Mb */
|
||||
/* IAR holds address A23-A16 (R/W) */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* IO Address Register (IAR)
|
||||
*/
|
||||
#define ED_WD_IAR 2
|
||||
|
||||
/*
|
||||
* EEROM Address Register
|
||||
*/
|
||||
#define ED_WD_EAR 3
|
||||
|
||||
/*
|
||||
* Interrupt Request Register (IRR)
|
||||
*/
|
||||
#define ED_WD_IRR 4
|
||||
|
||||
#define ED_WD_IRR_0WS 0x01 /* use 0 wait-states on 8 bit bus */
|
||||
#define ED_WD_IRR_OUT1 0x02 /* WD83C584 pin 1 output */
|
||||
#define ED_WD_IRR_OUT2 0x04 /* WD83C584 pin 2 output */
|
||||
#define ED_WD_IRR_OUT3 0x08 /* WD83C584 pin 3 output */
|
||||
#define ED_WD_IRR_FLASH 0x10 /* Flash RAM is in the ROM socket */
|
||||
|
||||
/*
|
||||
* The three bits of the encoded IRQ are decoded as follows:
|
||||
*
|
||||
* IR2 IR1 IR0 IRQ
|
||||
* 0 0 0 2/9
|
||||
* 0 0 1 3
|
||||
* 0 1 0 5
|
||||
* 0 1 1 7
|
||||
* 1 0 0 10
|
||||
* 1 0 1 11
|
||||
* 1 1 0 15
|
||||
* 1 1 1 4
|
||||
*/
|
||||
#define ED_WD_IRR_IR0 0x20 /* bit 0 of encoded IRQ */
|
||||
#define ED_WD_IRR_IR1 0x40 /* bit 1 of encoded IRQ */
|
||||
#define ED_WD_IRR_IEN 0x80 /* Interrupt enable */
|
||||
|
||||
/*
|
||||
* LA Address Register (LAAR)
|
||||
*/
|
||||
#define ED_WD_LAAR 5
|
||||
|
||||
#define ED_WD_LAAR_ADDRHI 0x1f /* bits 23-19 of RAM address */
|
||||
#define ED_WD_LAAR_0WS16 0x20 /* enable 0 wait-states on 16 bit bus */
|
||||
#define ED_WD_LAAR_L16EN 0x40 /* enable 16-bit operation */
|
||||
#define ED_WD_LAAR_M16EN 0x80 /* enable 16-bit memory access */
|
||||
|
||||
/* i/o base offset to station address/card-ID PROM */
|
||||
#define ED_WD_PROM 8
|
||||
|
||||
/*
|
||||
* 83C790 specific registers
|
||||
*/
|
||||
/*
|
||||
* Hardware Support Register (HWR) ('790)
|
||||
*/
|
||||
#define ED_WD790_HWR 4
|
||||
|
||||
#define WD_WD790_HWR_NUKE 0x10 /* hardware reset */
|
||||
#define ED_WD790_HWR_LPRM 0x40 /* LAN PROM select */
|
||||
#define ED_WD790_HWR_SWH 0x80 /* switch register set */
|
||||
|
||||
/*
|
||||
* ICR790 Interrupt Control Register for the 83C790
|
||||
*/
|
||||
#define ED_WD790_ICR 6
|
||||
|
||||
#define ED_WD790_ICR_EIL 0x01 /* enable interrupts */
|
||||
|
||||
/*
|
||||
* REV/IOPA Revision / I/O Pipe register for the 83C79X
|
||||
*/
|
||||
#define ED_WD790_REV 7
|
||||
|
||||
#define ED_WD790 0x20
|
||||
#define ED_WD795 0x40
|
||||
|
||||
/*
|
||||
* 79X RAM Address Register (RAR)
|
||||
* Enabled with SWH bit=1 in HWR register
|
||||
*/
|
||||
#define ED_WD790_RAR 0x0b
|
||||
|
||||
#define ED_WD790_RAR_SZ8 0x00 /* 8k memory buffer */
|
||||
#define ED_WD790_RAR_SZ16 0x10 /* 16k memory buffer */
|
||||
#define ED_WD790_RAR_SZ32 0x20 /* 32k memory buffer */
|
||||
#define ED_WD790_RAR_SZ64 0x30 /* 64k memory buffer */
|
||||
|
||||
/*
|
||||
* General Control Register (GCR)
|
||||
* Enabled with SWH bit=1 in HWR register
|
||||
*/
|
||||
#define ED_WD790_GCR 0x0d
|
||||
|
||||
#define ED_WD790_GCR_IR0 0x04 /* bit 0 of encoded IRQ */
|
||||
#define ED_WD790_GCR_IR1 0x08 /* bit 1 of encoded IRQ */
|
||||
#define ED_WD790_GCR_ZWSEN 0x20 /* zero wait state enable */
|
||||
#define ED_WD790_GCR_IR2 0x40 /* bit 2 of encoded IRQ */
|
||||
#define ED_WD790_GCR_LIT 0x01 /* Link Integrity Test Enable */
|
||||
/*
|
||||
* The three bits of the encoded IRQ are decoded as follows:
|
||||
*
|
||||
* IR2 IR1 IR0 IRQ
|
||||
* 0 0 0 none
|
||||
* 0 0 1 9
|
||||
* 0 1 0 3
|
||||
* 0 1 1 5
|
||||
* 1 0 0 7
|
||||
* 1 0 1 10
|
||||
* 1 1 0 11
|
||||
* 1 1 1 15
|
||||
*/
|
||||
|
||||
/* i/o base offset to CARD ID */
|
||||
#define ED_WD_CARD_ID ED_WD_PROM+6
|
||||
|
||||
/* Board type codes in card ID */
|
||||
#define ED_TYPE_WD8003S 0x02
|
||||
#define ED_TYPE_WD8003E 0x03
|
||||
#define ED_TYPE_WD8013EBT 0x05
|
||||
#define ED_TYPE_TOSHIBA1 0x11 /* named PCETA1 */
|
||||
#define ED_TYPE_TOSHIBA2 0x12 /* named PCETA2 */
|
||||
#define ED_TYPE_TOSHIBA3 0x13 /* named PCETB */
|
||||
#define ED_TYPE_TOSHIBA4 0x14 /* named PCETC */
|
||||
#define ED_TYPE_WD8003W 0x24
|
||||
#define ED_TYPE_WD8003EB 0x25
|
||||
#define ED_TYPE_WD8013W 0x26
|
||||
#define ED_TYPE_WD8013EP 0x27
|
||||
#define ED_TYPE_WD8013WC 0x28
|
||||
#define ED_TYPE_WD8013EPC 0x29
|
||||
#define ED_TYPE_SMC8216T 0x2a
|
||||
#define ED_TYPE_SMC8216C 0x2b
|
||||
#define ED_TYPE_WD8013EBP 0x2c
|
||||
|
||||
/* Bit definitions in card ID */
|
||||
#define ED_WD_REV_MASK 0x1f /* Revision mask */
|
||||
#define ED_WD_SOFTCONFIG 0x20 /* Soft config */
|
||||
#define ED_WD_LARGERAM 0x40 /* Large RAM */
|
||||
#define ED_MICROCHANEL 0x80 /* Microchannel bus (vs. isa) */
|
||||
|
||||
/*
|
||||
* Checksum total. All 8 bytes in station address PROM will add up to this
|
||||
*/
|
||||
#ifdef TOSH_ETHER
|
||||
#define ED_WD_ROM_CHECKSUM_TOTAL 0xA5
|
||||
#else
|
||||
#define ED_WD_ROM_CHECKSUM_TOTAL 0xFF
|
||||
#endif
|
||||
|
||||
#define ED_WD_NIC_OFFSET 0x10 /* I/O base offset to NIC */
|
||||
#define ED_WD_ASIC_OFFSET 0 /* I/O base offset to ASIC */
|
||||
#define ED_WD_IO_PORTS 32 /* # of i/o addresses used */
|
||||
|
||||
#define ED_WD_PAGE_OFFSET 0 /* page offset for NIC access to mem */
|
||||
|
||||
/*
|
||||
* Definitions for 3Com 3c503
|
||||
*/
|
||||
#define ED_3COM_NIC_OFFSET 0
|
||||
#define ED_3COM_ASIC_OFFSET 0x400 /* offset to nic i/o regs */
|
||||
|
||||
/*
|
||||
* XXX - The I/O address range is fragmented in the 3c503; this is the
|
||||
* number of regs at iobase.
|
||||
*/
|
||||
#define ED_3COM_IO_PORTS 16 /* # of i/o addresses used */
|
||||
|
||||
/* tx memory starts in second bank on 8bit cards */
|
||||
#define ED_3COM_TX_PAGE_OFFSET_8BIT 0x20
|
||||
|
||||
/* tx memory starts in first bank on 16bit cards */
|
||||
#define ED_3COM_TX_PAGE_OFFSET_16BIT 0x0
|
||||
|
||||
/* ...and rx memory starts in second bank */
|
||||
#define ED_3COM_RX_PAGE_OFFSET_16BIT 0x20
|
||||
|
||||
|
||||
/*
|
||||
* Page Start Register. Must match PSTART in NIC
|
||||
*/
|
||||
#define ED_3COM_PSTR 0
|
||||
|
||||
/*
|
||||
* Page Stop Register. Must match PSTOP in NIC
|
||||
*/
|
||||
#define ED_3COM_PSPR 1
|
||||
|
||||
/*
|
||||
* Drq Timer Register. Determines number of bytes to be transfered during
|
||||
* a DMA burst.
|
||||
*/
|
||||
#define ED_3COM_DQTR 2
|
||||
|
||||
/*
|
||||
* Base Configuration Register. Read-only register which contains the
|
||||
* board-configured I/O base address of the adapter. Bit encoded.
|
||||
*/
|
||||
#define ED_3COM_BCFR 3
|
||||
|
||||
#define ED_3COM_BCFR_2E0 0x01
|
||||
#define ED_3COM_BCFR_2A0 0x02
|
||||
#define ED_3COM_BCFR_280 0x04
|
||||
#define ED_3COM_BCFR_250 0x08
|
||||
#define ED_3COM_BCFR_350 0x10
|
||||
#define ED_3COM_BCFR_330 0x20
|
||||
#define ED_3COM_BCFR_310 0x40
|
||||
#define ED_3COM_BCFR_300 0x80
|
||||
|
||||
/*
|
||||
* EPROM Configuration Register. Read-only register which contains the
|
||||
* board-configured memory base address. Bit encoded.
|
||||
*/
|
||||
#define ED_3COM_PCFR 4
|
||||
|
||||
#define ED_3COM_PCFR_C8000 0x10
|
||||
#define ED_3COM_PCFR_CC000 0x20
|
||||
#define ED_3COM_PCFR_D8000 0x40
|
||||
#define ED_3COM_PCFR_DC000 0x80
|
||||
|
||||
/*
|
||||
* GA Configuration Register. Gate-Array Configuration Register.
|
||||
*/
|
||||
#define ED_3COM_GACFR 5
|
||||
|
||||
/*
|
||||
* mbs2 mbs1 mbs0 start address
|
||||
* 0 0 0 0x0000
|
||||
* 0 0 1 0x2000
|
||||
* 0 1 0 0x4000
|
||||
* 0 1 1 0x6000
|
||||
*
|
||||
* Note that with adapters with only 8K, the setting for 0x2000 must
|
||||
* always be used.
|
||||
*/
|
||||
#define ED_3COM_GACFR_MBS0 0x01
|
||||
#define ED_3COM_GACFR_MBS1 0x02
|
||||
#define ED_3COM_GACFR_MBS2 0x04
|
||||
|
||||
#define ED_3COM_GACFR_RSEL 0x08 /* enable shared memory */
|
||||
#define ED_3COM_GACFR_TEST 0x10 /* for GA testing */
|
||||
#define ED_3COM_GACFR_OWS 0x20 /* select 0WS access to GA */
|
||||
#define ED_3COM_GACFR_TCM 0x40 /* Mask DMA interrupts */
|
||||
#define ED_3COM_GACFR_NIM 0x80 /* Mask NIC interrupts */
|
||||
|
||||
/*
|
||||
* Control Register. Miscellaneous control functions.
|
||||
*/
|
||||
#define ED_3COM_CR 6
|
||||
|
||||
#define ED_3COM_CR_RST 0x01 /* Reset GA and NIC */
|
||||
#define ED_3COM_CR_XSEL 0x02 /* Transceiver select. BNC=1(def) AUI=0 */
|
||||
#define ED_3COM_CR_EALO 0x04 /* window EA PROM 0-15 to I/O base */
|
||||
#define ED_3COM_CR_EAHI 0x08 /* window EA PROM 16-31 to I/O base */
|
||||
#define ED_3COM_CR_SHARE 0x10 /* select interrupt sharing option */
|
||||
#define ED_3COM_CR_DBSEL 0x20 /* Double buffer select */
|
||||
#define ED_3COM_CR_DDIR 0x40 /* DMA direction select */
|
||||
#define ED_3COM_CR_START 0x80 /* Start DMA controller */
|
||||
|
||||
/*
|
||||
* Status Register. Miscellaneous status information.
|
||||
*/
|
||||
#define ED_3COM_STREG 7
|
||||
|
||||
#define ED_3COM_STREG_REV 0x07 /* GA revision */
|
||||
#define ED_3COM_STREG_DIP 0x08 /* DMA in progress */
|
||||
#define ED_3COM_STREG_DTC 0x10 /* DMA terminal count */
|
||||
#define ED_3COM_STREG_OFLW 0x20 /* Overflow */
|
||||
#define ED_3COM_STREG_UFLW 0x40 /* Underflow */
|
||||
#define ED_3COM_STREG_DPRDY 0x80 /* Data port ready */
|
||||
|
||||
/*
|
||||
* Interrupt/DMA Configuration Register
|
||||
*/
|
||||
#define ED_3COM_IDCFR 8
|
||||
|
||||
#define ED_3COM_IDCFR_DRQ0 0x01 /* DMA request 1 select */
|
||||
#define ED_3COM_IDCFR_DRQ1 0x02 /* DMA request 2 select */
|
||||
#define ED_3COM_IDCFR_DRQ2 0x04 /* DMA request 3 select */
|
||||
#define ED_3COM_IDCFR_UNUSED 0x08 /* not used */
|
||||
#define ED_3COM_IDCFR_IRQ2 0x10 /* Interrupt request 2 select */
|
||||
#define ED_3COM_IDCFR_IRQ3 0x20 /* Interrupt request 3 select */
|
||||
#define ED_3COM_IDCFR_IRQ4 0x40 /* Interrupt request 4 select */
|
||||
#define ED_3COM_IDCFR_IRQ5 0x80 /* Interrupt request 5 select */
|
||||
|
||||
/*
|
||||
* DMA Address Register MSB
|
||||
*/
|
||||
#define ED_3COM_DAMSB 9
|
||||
|
||||
/*
|
||||
* DMA Address Register LSB
|
||||
*/
|
||||
#define ED_3COM_DALSB 0x0a
|
||||
|
||||
/*
|
||||
* Vector Pointer Register 2
|
||||
*/
|
||||
#define ED_3COM_VPTR2 0x0b
|
||||
|
||||
/*
|
||||
* Vector Pointer Register 1
|
||||
*/
|
||||
#define ED_3COM_VPTR1 0x0c
|
||||
|
||||
/*
|
||||
* Vector Pointer Register 0
|
||||
*/
|
||||
#define ED_3COM_VPTR0 0x0d
|
||||
|
||||
/*
|
||||
* Register File Access MSB
|
||||
*/
|
||||
#define ED_3COM_RFMSB 0x0e
|
||||
|
||||
/*
|
||||
* Register File Access LSB
|
||||
*/
|
||||
#define ED_3COM_RFLSB 0x0f
|
||||
|
||||
/*
|
||||
* Definitions for Novell NE1000/2000 boards
|
||||
*/
|
||||
|
||||
/*
|
||||
* Board type codes
|
||||
*/
|
||||
#define ED_TYPE_NE1000 0x01
|
||||
#define ED_TYPE_NE2000 0x02
|
||||
|
||||
/*
|
||||
* Register offsets/total
|
||||
*/
|
||||
#define ED_NOVELL_NIC_OFFSET 0x00
|
||||
#define ED_NOVELL_ASIC_OFFSET 0x10
|
||||
#define ED_NOVELL_IO_PORTS 32
|
||||
|
||||
/*
|
||||
* Remote DMA data register; for reading or writing to the NIC mem
|
||||
* via programmed I/O (offset from ASIC base)
|
||||
*/
|
||||
#define ED_NOVELL_DATA 0x00
|
||||
|
||||
/*
|
||||
* Reset register; reading from this register causes a board reset
|
||||
*/
|
||||
#define ED_NOVELL_RESET 0x0f
|
||||
|
||||
#define ED_TYPE_PCMCIA 0x01
|
||||
#define ED_PCMCIA_PAGE_OFFSET 0x40 /* True for all cards I have seen */
|
||||
#define ED_PCMCIA_IO_PORTS 32
|
||||
#define ED_PCMCIA_RESET 0xF /* Reset port */
|
||||
@ -1,143 +0,0 @@
|
||||
/*
|
||||
* Loadable kernel module if_ed driver
|
||||
* 11 July 1995 Andrew McRae
|
||||
*
|
||||
*-------------------------------------------------------------------------
|
||||
*
|
||||
* Copyright (c) 1995 Andrew McRae. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#include <sys/param.h>
|
||||
#include <sys/ioctl.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/proc.h>
|
||||
#include <sys/conf.h>
|
||||
#include <sys/mount.h>
|
||||
#include <sys/sysent.h>
|
||||
#include <sys/exec.h>
|
||||
#include <sys/lkm.h>
|
||||
#include <sys/errno.h>
|
||||
|
||||
#include <i386/isa/isa.h>
|
||||
#include <i386/isa/isa_device.h>
|
||||
|
||||
#include <pccard/card.h>
|
||||
#include <pccard/slot.h>
|
||||
|
||||
/*
|
||||
* This defines the lkm_misc module use by modload
|
||||
* to define the module name.
|
||||
*/
|
||||
MOD_MISC( "ed")
|
||||
|
||||
|
||||
int edintr(struct pccard_dev *); /* Interrupt handler */
|
||||
void edunload(struct pccard_dev *); /* Disable driver */
|
||||
void edsuspend(struct pccard_dev *); /* Suspend driver */
|
||||
int edinit(struct pccard_dev *, int); /* init device */
|
||||
|
||||
static struct pccard_drv ed_info =
|
||||
{
|
||||
"ed",
|
||||
edintr,
|
||||
edunload,
|
||||
edsuspend,
|
||||
edinit,
|
||||
0,
|
||||
&net_imask
|
||||
};
|
||||
static int opened; /* Rather minimal device state... */
|
||||
|
||||
/*
|
||||
* Module handler that processes loads and unloads.
|
||||
* Once the module is loaded, the add driver routine is called
|
||||
* to register the driver.
|
||||
* If an unload is requested the remove driver routine is
|
||||
* called to deregister the driver before unloading.
|
||||
*/
|
||||
static int
|
||||
ed_handle( lkmtp, cmd)
|
||||
struct lkm_table *lkmtp;
|
||||
int cmd;
|
||||
{
|
||||
int i;
|
||||
struct lkm_misc *args = lkmtp->private.lkm_misc;
|
||||
int err = 0; /* default = success*/
|
||||
|
||||
switch( cmd) {
|
||||
case LKM_E_LOAD:
|
||||
|
||||
/*
|
||||
* Don't load twice! (lkmexists() is exported by kern_lkm.c)
|
||||
*/
|
||||
if( lkmexists( lkmtp))
|
||||
return( EEXIST);
|
||||
/*
|
||||
* Now register the driver
|
||||
*/
|
||||
pccard_add_driver(&ed_info);
|
||||
break; /* Success*/
|
||||
/*
|
||||
* Attempt to deregister the driver.
|
||||
*/
|
||||
case LKM_E_UNLOAD:
|
||||
pccard_remove_driver(&ed_info);
|
||||
break; /* Success*/
|
||||
|
||||
default: /* we only understand load/unload*/
|
||||
err = EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
return( err);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* External entry point; should generally match name of .o file. The
|
||||
* arguments are always the same for all loaded modules. The "load",
|
||||
* "unload", and "stat" functions in "DISPATCH" will be called under
|
||||
* their respective circumstances unless their value is "nosys". If
|
||||
* called, they are called with the same arguments (cmd is included to
|
||||
* allow the use of a single function, ver is included for version
|
||||
* matching between modules and the kernel loader for the modules).
|
||||
*
|
||||
* Since we expect to link in the kernel and add external symbols to
|
||||
* the kernel symbol name space in a future version, generally all
|
||||
* functions used in the implementation of a particular module should
|
||||
* be static unless they are expected to be seen in other modules or
|
||||
* to resolve unresolved symbols alread existing in the kernel (the
|
||||
* second case is not likely to ever occur).
|
||||
*
|
||||
* The entry point should return 0 unless it is refusing load (in which
|
||||
* case it should return an errno from errno.h).
|
||||
*/
|
||||
int
|
||||
lkm_ed(lkmtp, cmd, ver)
|
||||
struct lkm_table *lkmtp;
|
||||
int cmd;
|
||||
int ver;
|
||||
{
|
||||
DISPATCH(lkmtp,cmd,ver,ed_handle,ed_handle,nosys)
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user