diff --git a/sys/riscv/include/elf.h b/sys/riscv/include/elf.h
index ff0f36d2efe6..a14d6859902b 100644
--- a/sys/riscv/include/elf.h
+++ b/sys/riscv/include/elf.h
@@ -82,5 +82,6 @@ __ElfType(Auxinfo);
 #define	HWCAP_ISA_C		HWCAP_ISA_BIT('c')
 #define	HWCAP_ISA_G		\
     (HWCAP_ISA_I | HWCAP_ISA_M | HWCAP_ISA_A | HWCAP_ISA_F | HWCAP_ISA_D)
+#define	HWCAP_ISA_B		HWCAP_ISA_BIT('b')
 
 #endif /* !_MACHINE_ELF_H_ */
diff --git a/sys/riscv/riscv/identcpu.c b/sys/riscv/riscv/identcpu.c
index c681edfff47b..203edb3689bc 100644
--- a/sys/riscv/riscv/identcpu.c
+++ b/sys/riscv/riscv/identcpu.c
@@ -245,6 +245,7 @@ parse_riscv_isa(struct cpu_desc *desc, char *isa, int len)
 	while (i < len) {
 		switch(isa[i]) {
 		case 'a':
+		case 'b':
 		case 'c':
 		case 'd':
 		case 'f':