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synced 2024-11-25 10:01:02 +01:00
dwc: Move interrupt related code to core and dma file
No functional changes intended.
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@ -419,3 +419,22 @@ dwc1000_harvest_stats(struct dwc_softc *sc)
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dwc1000_clear_stats(sc);
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}
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void
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dwc1000_intr(struct dwc_softc *sc)
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{
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uint32_t reg;
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DWC_ASSERT_LOCKED(sc);
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reg = READ4(sc, INTERRUPT_STATUS);
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if (reg)
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READ4(sc, SGMII_RGMII_SMII_CTRL_STATUS);
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}
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void
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dwc1000_intr_disable(struct dwc_softc *sc)
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{
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WRITE4(sc, INTERRUPT_ENABLE, 0);
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}
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@ -39,5 +39,7 @@ void dwc1000_enable_csum_offload(struct dwc_softc *sc);
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void dwc1000_setup_rxfilter(struct dwc_softc *sc);
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void dwc1000_get_hwaddr(struct dwc_softc *sc, uint8_t *hwaddr);
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void dwc1000_harvest_stats(struct dwc_softc *sc);
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void dwc1000_intr(struct dwc_softc *softc);
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void dwc1000_intr_disable(struct dwc_softc *sc);
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#endif /* __DWC1000_CORE_H__ */
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@ -810,3 +810,38 @@ dma1000_free(struct dwc_softc *sc)
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if (sc->txdesc_tag != NULL)
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bus_dma_tag_destroy(sc->txdesc_tag);
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}
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/*
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* Interrupt function
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*/
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int
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dma1000_intr(struct dwc_softc *sc)
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{
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uint32_t reg;
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int rv;
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DWC_ASSERT_LOCKED(sc);
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rv = 0;
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reg = READ4(sc, DMA_STATUS);
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if (reg & DMA_STATUS_NIS) {
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if (reg & DMA_STATUS_RI)
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dma1000_rxfinish_locked(sc);
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if (reg & DMA_STATUS_TI) {
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dma1000_txfinish_locked(sc);
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dma1000_txstart(sc);
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}
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}
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if (reg & DMA_STATUS_AIS) {
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if (reg & DMA_STATUS_FBI) {
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/* Fatal bus error */
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rv = EIO;
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}
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}
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WRITE4(sc, DMA_STATUS, reg & DMA_STATUS_INTR_MASK);
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return (rv);
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}
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@ -50,5 +50,6 @@ int dma1000_setup_txbuf(struct dwc_softc *sc, int idx, struct mbuf **mp);
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void dma1000_txfinish_locked(struct dwc_softc *sc);
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void dma1000_rxfinish_locked(struct dwc_softc *sc);
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void dma1000_txstart(struct dwc_softc *sc);
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int dma1000_intr(struct dwc_softc *sc);
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#endif /* __DWC1000_DMA_H__ */
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@ -300,38 +300,18 @@ static void
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dwc_intr(void *arg)
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{
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struct dwc_softc *sc;
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uint32_t reg;
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int rv;
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sc = arg;
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DWC_LOCK(sc);
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reg = READ4(sc, INTERRUPT_STATUS);
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if (reg)
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READ4(sc, SGMII_RGMII_SMII_CTRL_STATUS);
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reg = READ4(sc, DMA_STATUS);
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if (reg & DMA_STATUS_NIS) {
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if (reg & DMA_STATUS_RI)
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dma1000_rxfinish_locked(sc);
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if (reg & DMA_STATUS_TI) {
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dma1000_txfinish_locked(sc);
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dwc_txstart_locked(sc);
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}
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dwc1000_intr(sc);
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rv = dma1000_intr(sc);
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if (rv == EIO) {
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device_printf(sc->dev,
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"Ethernet DMA error, restarting controller.\n");
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dwc_stop_locked(sc);
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dwc_init_locked(sc);
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}
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if (reg & DMA_STATUS_AIS) {
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if (reg & DMA_STATUS_FBI) {
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/* Fatal bus error */
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device_printf(sc->dev,
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"Ethernet DMA error, restarting controller.\n");
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dwc_stop_locked(sc);
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dwc_init_locked(sc);
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}
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}
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WRITE4(sc, DMA_STATUS, reg & DMA_STATUS_INTR_MASK);
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DWC_UNLOCK(sc);
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}
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@ -706,7 +686,7 @@ dwc_detach(device_t dev)
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* Disable and tear down interrupts before anything else, so we don't
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* race with the handler.
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*/
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WRITE4(sc, INTERRUPT_ENABLE, 0);
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dwc1000_intr_disable(sc);
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if (sc->intr_cookie != NULL) {
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bus_teardown_intr(dev, sc->res[1], sc->intr_cookie);
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}
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