dwc: Move interrupt related code to core and dma file

No functional changes intended.
This commit is contained in:
Emmanuel Vadot 2023-10-03 18:04:03 +02:00
parent fe82f82dcc
commit 29776aa436
5 changed files with 66 additions and 29 deletions

View File

@ -419,3 +419,22 @@ dwc1000_harvest_stats(struct dwc_softc *sc)
dwc1000_clear_stats(sc);
}
void
dwc1000_intr(struct dwc_softc *sc)
{
uint32_t reg;
DWC_ASSERT_LOCKED(sc);
reg = READ4(sc, INTERRUPT_STATUS);
if (reg)
READ4(sc, SGMII_RGMII_SMII_CTRL_STATUS);
}
void
dwc1000_intr_disable(struct dwc_softc *sc)
{
WRITE4(sc, INTERRUPT_ENABLE, 0);
}

View File

@ -39,5 +39,7 @@ void dwc1000_enable_csum_offload(struct dwc_softc *sc);
void dwc1000_setup_rxfilter(struct dwc_softc *sc);
void dwc1000_get_hwaddr(struct dwc_softc *sc, uint8_t *hwaddr);
void dwc1000_harvest_stats(struct dwc_softc *sc);
void dwc1000_intr(struct dwc_softc *softc);
void dwc1000_intr_disable(struct dwc_softc *sc);
#endif /* __DWC1000_CORE_H__ */

View File

@ -810,3 +810,38 @@ dma1000_free(struct dwc_softc *sc)
if (sc->txdesc_tag != NULL)
bus_dma_tag_destroy(sc->txdesc_tag);
}
/*
* Interrupt function
*/
int
dma1000_intr(struct dwc_softc *sc)
{
uint32_t reg;
int rv;
DWC_ASSERT_LOCKED(sc);
rv = 0;
reg = READ4(sc, DMA_STATUS);
if (reg & DMA_STATUS_NIS) {
if (reg & DMA_STATUS_RI)
dma1000_rxfinish_locked(sc);
if (reg & DMA_STATUS_TI) {
dma1000_txfinish_locked(sc);
dma1000_txstart(sc);
}
}
if (reg & DMA_STATUS_AIS) {
if (reg & DMA_STATUS_FBI) {
/* Fatal bus error */
rv = EIO;
}
}
WRITE4(sc, DMA_STATUS, reg & DMA_STATUS_INTR_MASK);
return (rv);
}

View File

@ -50,5 +50,6 @@ int dma1000_setup_txbuf(struct dwc_softc *sc, int idx, struct mbuf **mp);
void dma1000_txfinish_locked(struct dwc_softc *sc);
void dma1000_rxfinish_locked(struct dwc_softc *sc);
void dma1000_txstart(struct dwc_softc *sc);
int dma1000_intr(struct dwc_softc *sc);
#endif /* __DWC1000_DMA_H__ */

View File

@ -300,38 +300,18 @@ static void
dwc_intr(void *arg)
{
struct dwc_softc *sc;
uint32_t reg;
int rv;
sc = arg;
DWC_LOCK(sc);
reg = READ4(sc, INTERRUPT_STATUS);
if (reg)
READ4(sc, SGMII_RGMII_SMII_CTRL_STATUS);
reg = READ4(sc, DMA_STATUS);
if (reg & DMA_STATUS_NIS) {
if (reg & DMA_STATUS_RI)
dma1000_rxfinish_locked(sc);
if (reg & DMA_STATUS_TI) {
dma1000_txfinish_locked(sc);
dwc_txstart_locked(sc);
}
dwc1000_intr(sc);
rv = dma1000_intr(sc);
if (rv == EIO) {
device_printf(sc->dev,
"Ethernet DMA error, restarting controller.\n");
dwc_stop_locked(sc);
dwc_init_locked(sc);
}
if (reg & DMA_STATUS_AIS) {
if (reg & DMA_STATUS_FBI) {
/* Fatal bus error */
device_printf(sc->dev,
"Ethernet DMA error, restarting controller.\n");
dwc_stop_locked(sc);
dwc_init_locked(sc);
}
}
WRITE4(sc, DMA_STATUS, reg & DMA_STATUS_INTR_MASK);
DWC_UNLOCK(sc);
}
@ -706,7 +686,7 @@ dwc_detach(device_t dev)
* Disable and tear down interrupts before anything else, so we don't
* race with the handler.
*/
WRITE4(sc, INTERRUPT_ENABLE, 0);
dwc1000_intr_disable(sc);
if (sc->intr_cookie != NULL) {
bus_teardown_intr(dev, sc->res[1], sc->intr_cookie);
}