From 4cc6fe1e5b73ce540882753d918bc8208849e9e9 Mon Sep 17 00:00:00 2001 From: Konstantin Belousov Date: Mon, 2 Aug 2021 22:53:08 +0300 Subject: [PATCH] coretemp: use x86_msr_op for thermal MSR access Reviewed by: markj Discussed with: mav Sponsored by: The FreeBSD Foundation MFC after: 1 week Differential revision: https://reviews.freebsd.org/D31386 --- sys/dev/coretemp/coretemp.c | 57 +++++++++++-------------------------- 1 file changed, 16 insertions(+), 41 deletions(-) diff --git a/sys/dev/coretemp/coretemp.c b/sys/dev/coretemp/coretemp.c index 53a2434254f6..bdc71b284ac7 100644 --- a/sys/dev/coretemp/coretemp.c +++ b/sys/dev/coretemp/coretemp.c @@ -315,56 +315,31 @@ struct coretemp_args { uint64_t val; }; -static void -coretemp_rdmsr(void *arg) -{ - struct coretemp_args *args = arg; - - args->val = rdmsr(args->msr); -} - -static void -coretemp_wrmsr(void *arg) -{ - struct coretemp_args *args = arg; - - wrmsr(args->msr, args->val); -} - +/* + * The digital temperature reading is located at bit 16 + * of MSR_THERM_STATUS. + * + * There is a bit on that MSR that indicates whether the + * temperature is valid or not. + * + * The temperature is computed by subtracting the temperature + * reading by Tj(max). + */ static uint64_t coretemp_get_thermal_msr(int cpu) { - struct coretemp_args args; - cpuset_t cpus; + uint64_t res; - /* - * The digital temperature reading is located at bit 16 - * of MSR_THERM_STATUS. - * - * There is a bit on that MSR that indicates whether the - * temperature is valid or not. - * - * The temperature is computed by subtracting the temperature - * reading by Tj(max). - */ - args.msr = MSR_THERM_STATUS; - CPU_SETOF(cpu, &cpus); - smp_rendezvous_cpus(cpus, smp_no_rendezvous_barrier, coretemp_rdmsr, - smp_no_rendezvous_barrier, &args); - return (args.val); + x86_msr_op(MSR_THERM_STATUS, MSR_OP_RENDEZVOUS_ONE | MSR_OP_READ | + MSR_OP_CPUID(cpu), 0, &res); + return (res); } static void coretemp_clear_thermal_msr(int cpu) { - struct coretemp_args args; - cpuset_t cpus; - - args.msr = MSR_THERM_STATUS; - args.val = 0; - CPU_SETOF(cpu, &cpus); - smp_rendezvous_cpus(cpus, smp_no_rendezvous_barrier, coretemp_wrmsr, - smp_no_rendezvous_barrier, &args); + x86_msr_op(MSR_THERM_STATUS, MSR_OP_RENDEZVOUS_ONE | MSR_OP_WRITE | + MSR_OP_CPUID(cpu), 0, NULL); } static int