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allwinner: NKMP clock: add update bit
The PLL_DDR clock have an update bit which need to be set after changing the value, add the possibility to define one for NKMP clocks. This allow us to add the missing clocks. We now have the full list of clocks created under the clock domain.
This commit is contained in:
Emmanuel Vadot
parent
7a5603c04a
commit
511d4e58f3
@ -64,6 +64,7 @@ struct aw_clk_init {
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#define AW_CLK_REPARENT 0x0008
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#define AW_CLK_SCALE_CHANGE 0x0010
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#define AW_CLK_HAS_FRAC 0x0020
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#define AW_CLK_HAS_UPDATE 0x0040
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#define AW_CLK_FACTOR_POWER_OF_TWO 0x0001
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#define AW_CLK_FACTOR_ZERO_BASED 0x0002
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@ -218,6 +219,48 @@ aw_clk_factor_get_value(struct aw_clk_factor *factor, uint32_t raw)
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.flags = _flags, \
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}
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#define NKMP_CLK_WITH_UPDATE(_clkname, \
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_id, _name, _pnames, \
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_offset, \
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_n_shift, _n_width, _n_value, _n_flags, \
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_k_shift, _k_width, _k_value, _k_flags, \
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_m_shift, _m_width, _m_value, _m_flags, \
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_p_shift, _p_width, _p_value, _p_flags, \
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_gate, \
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_lock, _lock_retries, \
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_update, \
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_flags) \
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static struct aw_clk_nkmp_def _clkname = { \
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.clkdef = { \
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.id = _id, \
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.name = _name, \
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.parent_names = _pnames, \
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.parent_cnt = nitems(_pnames), \
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}, \
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.offset = _offset, \
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.n.shift = _n_shift, \
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.n.width = _n_width, \
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.n.value = _n_value, \
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.n.flags = _n_flags, \
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.k.shift = _k_shift, \
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.k.width = _k_width, \
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.k.value = _k_value, \
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.k.flags = _k_flags, \
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.m.shift = _m_shift, \
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.m.width = _m_width, \
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.m.value = _m_value, \
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.m.flags = _m_flags, \
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.p.shift = _p_shift, \
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.p.width = _p_width, \
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.p.value = _p_value, \
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.p.flags = _p_flags, \
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.gate_shift = _gate, \
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.lock_shift = _lock, \
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.lock_retries = _lock_retries, \
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.update_shift = _update, \
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.flags = _flags | AW_CLK_HAS_UPDATE, \
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}
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#define NM_CLK(_clkname, _id, _name, _pnames, \
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_offset, \
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_nshift, _nwidth, _nvalue, _nflags, \
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@ -58,6 +58,7 @@ struct aw_clk_nkmp_sc {
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uint32_t gate_shift;
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uint32_t lock_shift;
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uint32_t lock_retries;
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uint32_t update_shift;
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uint32_t flags;
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};
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@ -263,6 +264,14 @@ aw_clk_nkmp_set_freq(struct clknode *clk, uint64_t fparent, uint64_t *fout,
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WRITE4(clk, sc->offset, val);
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DELAY(2000);
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if ((sc->flags & AW_CLK_HAS_UPDATE) != 0) {
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DEVICE_LOCK(clk);
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READ4(clk, sc->offset, &val);
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val |= 1 << sc->update_shift;
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WRITE4(clk, sc->offset, val);
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DELAY(2000);
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}
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if ((sc->flags & AW_CLK_HAS_LOCK) != 0) {
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for (retry = 0; retry < sc->lock_retries; retry++) {
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READ4(clk, sc->offset, &val);
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@ -354,6 +363,7 @@ aw_clk_nkmp_register(struct clkdom *clkdom, struct aw_clk_nkmp_def *clkdef)
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sc->gate_shift = clkdef->gate_shift;
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sc->lock_shift = clkdef->lock_shift;
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sc->lock_retries = clkdef->lock_retries;
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sc->update_shift = clkdef->update_shift;
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sc->flags = clkdef->flags;
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clknode_register(clkdom, clk);
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@ -44,6 +44,7 @@ struct aw_clk_nkmp_def {
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uint32_t gate_shift;
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uint32_t lock_shift;
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uint32_t lock_retries;
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uint32_t update_shift;
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uint32_t flags;
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};
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@ -177,15 +177,17 @@ static struct aw_ccung_gate h3_ccu_gates[] = {
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CCU_GATE(H3_CLK_I2S1, "i2s1", "i2s1mux", 0xB4, 31)
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CCU_GATE(H3_CLK_I2S2, "i2s2", "i2s2mux", 0xB8, 31)
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/* CCU_GATE(H3_CLK_DRAM_VE, "dram-ve", "dram", 0x100, 0) */
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/* CCU_GATE(H3_CLK_DRAM_VE, "dram-csi", "dram", 0x100, 1) */
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/* CCU_GATE(H3_CLK_DRAM_VE, "dram-deinterlace", "dram", 0x100, 2) */
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/* CCU_GATE(H3_CLK_DRAM_VE, "dram-ts", "dram", 0x100, 3) */
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CCU_GATE(H3_CLK_DRAM_VE, "dram-ve", "dram", 0x100, 0)
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CCU_GATE(H3_CLK_DRAM_CSI, "dram-csi", "dram", 0x100, 1)
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CCU_GATE(H3_CLK_DRAM_DEINTERLACE, "dram-deinterlace", "dram", 0x100, 2)
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CCU_GATE(H3_CLK_DRAM_TS, "dram-ts", "dram", 0x100, 3)
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CCU_GATE(H3_CLK_AC_DIG, "ac-dig", "pll_audio", 0x140, 31)
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CCU_GATE(H3_CLK_AVS, "avs", "osc24M", 0x144, 31)
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CCU_GATE(H3_CLK_CSI_MISC, "csi-misc", "osc24M", 0x130, 31)
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CCU_GATE(H3_CLK_HDMI_DDC, "hdmi-ddc", "osc24M", 0x154, 31)
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};
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@ -265,10 +267,19 @@ NM_CLK_WITH_FRAC(pll_ve_clk,
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270000000, 297000000, /* freq0, freq1 */
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24, 25); /* mode sel, freq sel */
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/*
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* Needs a update bit on nkmp or special clk
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static const char *pll_ddr_parents[] = {"osc24M"};
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*/
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NKMP_CLK_WITH_UPDATE(pll_ddr_clk,
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H3_CLK_PLL_DDR, /* id */
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"pll_ddr", pll_ddr_parents, /* name, parents */
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0x20, /* offset */
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8, 5, 0, 0, /* n factor */
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4, 2, 0, 0, /* k factor */
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0, 2, 0, 0, /* m factor */
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0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */
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31, /* gate */
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28, 1000, /* lock */
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20, /* update */
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AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */
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static const char *pll_periph0_parents[] = {"osc24M"};
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static const char *pll_periph0_2x_parents[] = {"pll_periph0"};
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@ -283,6 +294,14 @@ NKMP_CLK(pll_periph0_clk,
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31, /* gate */
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28, 1000, /* lock */
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AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */
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FIXED_CLK(pll_periph0_2x_clk,
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H3_CLK_PLL_PERIPH0_2X, /* id */
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"pll_periph0-2x", /* name */
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pll_periph0_2x_parents, /* parent */
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0, /* freq */
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2, /* mult */
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1, /* div */
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0); /* flags */
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static const char *pll_gpu_parents[] = {"osc24M"};
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NM_CLK_WITH_FRAC(pll_gpu_clk,
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@ -496,32 +515,122 @@ NM_CLK(spdif_clk,
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31, /* gate */
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AW_CLK_HAS_GATE); /* flags */
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FIXED_CLK(pll_periph0_2x_clk,
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H3_CLK_PLL_PERIPH0_2X, /* id */
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"pll_periph0-2x", /* name */
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pll_periph0_2x_parents, /* parent */
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0, /* freq */
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2, /* mult */
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1, /* div */
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0); /* flags */
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static const char *dram_parents[] = {"pll_ddr", "pll_periph0-2x"};
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NM_CLK(dram_clk,
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H3_CLK_DRAM, "dram", dram_parents, /* id, name, parents */
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0xF4, /* offset */
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0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
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0, 4, 0, 0, /* m factor */
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20, 2, /* mux */
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0, /* gate */
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AW_CLK_HAS_MUX); /* flags */
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/* DRAM clock 0xF4 */
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/* DE gating 0x104 */
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/* TCON0 0x118 */
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/* TVE 0x120 */
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/* Deinterlace 0x124 */
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/* CSI_MISC 0x130 */
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/* CSI 0x134 */
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/* VE 0x13C */
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/* HDMI 0x150 */
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/* MBUS 0x15C */
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/* GPU 0x1A0 */
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static const char *de_parents[] = {"pll_periph0-2x", "pll_de"};
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NM_CLK(de_clk,
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H3_CLK_DE, "de", de_parents, /* id, name, parents */
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0x104, /* offset */
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0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
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0, 4, 0, 0, /* m factor */
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24, 2, /* mux */
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31, /* gate */
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AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */
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static const char *tcon0_parents[] = {"pll_video"};
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NM_CLK(tcon0_clk,
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H3_CLK_TCON0, "tcon0", tcon0_parents, /* id, name, parents */
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0x118, /* offset */
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0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
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0, 4, 0, 0, /* m factor */
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24, 2, /* mux */
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31, /* gate */
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AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */
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static const char *tve_parents[] = {"pll_de", "pll_periph1"};
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NM_CLK(tve_clk,
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H3_CLK_TVE, "tve", tve_parents, /* id, name, parents */
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0x120, /* offset */
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0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
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0, 4, 0, 0, /* m factor */
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24, 2, /* mux */
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31, /* gate */
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AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */
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static const char *deinterlace_parents[] = {"pll_periph0", "pll_periph1"};
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NM_CLK(deinterlace_clk,
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H3_CLK_DEINTERLACE, "deinterlace", deinterlace_parents, /* id, name, parents */
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0x124, /* offset */
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0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
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0, 4, 0, 0, /* m factor */
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24, 2, /* mux */
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31, /* gate */
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AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */
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static const char *csi_sclk_parents[] = {"pll_periph0", "pll_periph1"};
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NM_CLK(csi_sclk_clk,
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H3_CLK_CSI_SCLK, "csi-sclk", csi_sclk_parents, /* id, name, parents */
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0x134, /* offset */
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0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
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16, 4, 0, 0, /* m factor */
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24, 2, /* mux */
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31, /* gate */
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AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */
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static const char *csi_mclk_parents[] = {"osc24M", "pll_video", "pll_periph1"};
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NM_CLK(csi_mclk_clk,
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H3_CLK_CSI_MCLK, "csi-mclk", csi_mclk_parents, /* id, name, parents */
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0x134, /* offset */
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0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
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0, 4, 0, 0, /* m factor */
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8, 2, /* mux */
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15, /* gate */
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AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */
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static const char *ve_parents[] = {"pll_ve"};
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NM_CLK(ve_clk,
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H3_CLK_VE, "ve", ve_parents, /* id, name, parents */
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0x13C, /* offset */
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16, 3, 0, 0, /* n factor */
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0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake) */
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0, 0, /* mux */
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31, /* gate */
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AW_CLK_HAS_GATE); /* flags */
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static const char *hdmi_parents[] = {"pll_video"};
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NM_CLK(hdmi_clk,
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H3_CLK_HDMI, "hdmi", hdmi_parents, /* id, name, parents */
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0x150, /* offset */
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0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
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0, 4, 0, 0, /* m factor */
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24, 2, /* mux */
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31, /* gate */
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AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */
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static const char *mbus_parents[] = {"osc24M", "pll_periph0-2x", "pll_ddr"};
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NM_CLK(mbus_clk,
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H3_CLK_MBUS, "mbus", mbus_parents, /* id, name, parents */
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0x15C, /* offset */
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0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
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0, 3, 0, 0, /* m factor */
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24, 2, /* mux */
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31, /* gate */
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AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */
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static const char *gpu_parents[] = {"pll_gpu"};
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NM_CLK(gpu_clk,
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H3_CLK_GPU, "gpu", gpu_parents, /* id, name, parents */
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0x1A0, /* offset */
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0, 2, 0, 0, /* n factor */
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0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake) */
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0, 0, /* mux */
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31, /* gate */
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AW_CLK_HAS_GATE); /* flags */
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static struct aw_clk_nkmp_def *nkmp_clks[] = {
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&pll_cpux_clk,
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&pll_audio_clk,
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&pll_periph0_clk,
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&pll_periph1_clk,
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&pll_ddr_clk,
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};
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static struct aw_clk_nm_def *nm_clks[] = {
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@ -539,6 +648,17 @@ static struct aw_clk_nm_def *nm_clks[] = {
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&spi0_clk,
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&spi1_clk,
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&spdif_clk,
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&dram_clk,
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&de_clk,
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&tcon0_clk,
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&tve_clk,
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&deinterlace_clk,
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&csi_sclk_clk,
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&csi_mclk_clk,
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&ve_clk,
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&hdmi_clk,
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&mbus_clk,
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&gpu_clk,
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};
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static struct aw_clk_prediv_mux_def *prediv_mux_clks[] = {
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@ -569,6 +689,7 @@ static struct clk_fixed_def *fixed_factor_clks[] = {
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static struct aw_clk_init init_clks[] = {
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{"ahb1", "pll_periph0", 0, false},
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{"ahb2", "pll_periph0", 0, false},
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{"dram", "pll_ddr", 0, false},
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};
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void
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@ -98,14 +98,12 @@
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#define H3_CLK_PLL_GPU 11
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#define H3_CLK_PLL_PERIPH1 12
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#define H3_CLK_PLL_DE 13
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#define H3_CLK_CPUX 14
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#define H3_CLK_AXI 15
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#define H3_CLK_AHB1 16
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#define H3_CLK_APB1 17
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#define H3_CLK_APB2 18
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#define H3_CLK_AHB2 19
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#define H3_CLK_BUS_CE 20
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#define H3_CLK_BUS_DMA 21
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#define H3_CLK_BUS_MMC0 22
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@ -155,7 +153,6 @@
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#define H3_CLK_BUS_SCR 66
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#define H3_CLK_BUS_EPHY 67
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#define H3_CLK_BUS_DBG 68
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#define H3_CLK_THS 69
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#define H3_CLK_NAND 70
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#define H3_CLK_MMC0 71
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@ -183,7 +180,7 @@
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#define H3_CLK_USBOHCI1 93
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#define H3_CLK_USBOHCI2 94
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#define H3_CLK_USBOHCI3 95
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#define H3_CLK_DRAM 96
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#define H3_CLK_DRAM_VE 97
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#define H3_CLK_DRAM_CSI 98
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#define H3_CLK_DRAM_DEINTERLACE 99
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@ -200,7 +197,7 @@
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#define H3_CLK_AVS 110
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#define H3_CLK_HDMI 111
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#define H3_CLK_HDMI_DDC 112
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#define H3_CLK_MBUS 113
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#define H3_CLK_GPU 114
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void ccu_h3_register_clocks(struct aw_ccung_softc *sc);
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