mirror of
https://git.hardenedbsd.org/hardenedbsd/HardenedBSD.git
synced 2024-12-29 15:10:57 +01:00
Eliminate irq_dispatch.S. Move the data items it contained into arm/intr.c
and the functionality it provided into arm/exception.S. Rename the main irq handling routine from arm_handler_execute() to arm_irq_handler() to make it more congruent with how other exception handlers are named, and also update its signature to reflect what has long been reality: it is passed just a trapframe pointer, no interrupt number argument.
This commit is contained in:
parent
2efbc4a68d
commit
5e4e1d4995
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=262979
@ -7,7 +7,6 @@ arm/arm/cpufunc_asm_armv5.S standard
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arm/arm/cpufunc_asm_arm10.S standard
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arm/arm/cpufunc_asm_arm11.S standard
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arm/arm/cpufunc_asm_armv7.S standard
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arm/arm/irq_dispatch.S standard
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arm/arm/gic.c standard
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arm/allwinner/a20/a20_cpu_cfg.c standard
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@ -7,7 +7,6 @@ arm/arm/cpufunc_asm_armv5.S standard
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arm/arm/cpufunc_asm_arm10.S standard
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arm/arm/cpufunc_asm_arm11.S standard
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arm/arm/cpufunc_asm_armv7.S standard
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arm/arm/irq_dispatch.S standard
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arm/allwinner/a10_clk.c standard
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arm/allwinner/a10_common.c standard
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@ -192,6 +192,16 @@ ASENTRY_NP(exception_exit)
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PULLFRAMEFROMSVCANDEXIT
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END(exception_exit)
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ASENTRY_NP(irq_entry)
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sub lr, lr, #0x00000004 /* Adjust the lr */
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PUSHFRAMEINSVC /* Push an interrupt frame */
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mov r0, sp /* arg for dispatcher */
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adr lr, exception_exit
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mov r1, #0
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b _C_LABEL(arm_irq_handler)
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END(irq_entry)
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/*
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* undefined_entry:
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*
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@ -56,12 +56,18 @@ typedef void (*mask_fn)(void *);
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static struct intr_event *intr_events[NIRQ];
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void arm_handler_execute(struct trapframe *, int);
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void arm_irq_handler(struct trapframe *);
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void (*arm_post_filter)(void *) = NULL;
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int (*arm_config_irq)(int irq, enum intr_trigger trig,
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enum intr_polarity pol) = NULL;
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/* Data for statistics reporting. */
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u_long intrcnt[NIRQ];
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char intrnames[NIRQ * INTRNAME_LEN];
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size_t sintrcnt = sizeof(intrcnt);
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size_t sintrnames = sizeof(intrnames);
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/*
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* Pre-format intrnames into an array of fixed-size strings containing spaces.
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* This allows us to avoid the need for an intermediate table of indices into
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@ -127,7 +133,7 @@ dosoftints(void)
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}
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void
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arm_handler_execute(struct trapframe *frame, int irqnb)
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arm_irq_handler(struct trapframe *frame)
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{
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struct intr_event *event;
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int i;
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@ -1,120 +0,0 @@
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/* $NetBSD: irq_dispatch.S,v 1.5 2003/10/30 08:57:24 scw Exp $ */
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/*-
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* Copyright (c) 2002 Fujitsu Component Limited
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* Copyright (c) 2002 Genetec Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of The Fujitsu Component Limited nor the name of
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* Genetec corporation may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC
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* CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC
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* CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/*-
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* Copyright (c) 2002, 2003 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "assym.s"
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#include <machine/asm.h>
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#include <machine/asmacros.h>
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#include <machine/armreg.h>
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__FBSDID("$FreeBSD$");
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/*
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* irq_entry:
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* Main entry point for the IRQ vector. This is a generic version
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* which can be used by different platforms.
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*/
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.text
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.align 0
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.Lcurrent_intr_depth:
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.word _C_LABEL(current_intr_depth)
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AST_LOCALS
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ASENTRY_NP(irq_entry)
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sub lr, lr, #0x00000004 /* Adjust the lr */
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PUSHFRAMEINSVC /* Push an interrupt frame */
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UNWINDSVCFRAME
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mov r0, sp /* arg for dispatcher */
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mov r1, #0
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bl _C_LABEL(arm_handler_execute)
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DO_AST
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PULLFRAMEFROMSVCANDEXIT
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movs pc, lr /* Exit */
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END(irq_entry)
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.data
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.align 0
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.global _C_LABEL(intrnames), _C_LABEL(sintrnames)
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.global _C_LABEL(intrcnt), _C_LABEL(sintrcnt)
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_C_LABEL(intrnames):
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.space NIRQ * (MAXCOMLEN + 1)
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_C_LABEL(intrcnt):
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.space NIRQ * 4
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_C_LABEL(sintrnames):
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.int NIRQ * (MAXCOMLEN + 1)
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_C_LABEL(sintrcnt):
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.int NIRQ * 4
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.global _C_LABEL(current_intr_depth)
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_C_LABEL(current_intr_depth):
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.word 0
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@ -1,6 +1,5 @@
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# $FreeBSD$
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arm/arm/cpufunc_asm_arm9.S standard
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arm/arm/irq_dispatch.S standard
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arm/at91/at91_machdep.c standard
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arm/at91/at91_aic.c standard
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arm/at91/at91.c standard
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@ -22,7 +22,6 @@ arm/arm/cpufunc_asm_arm11.S standard
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arm/arm/cpufunc_asm_arm11x6.S standard
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arm/arm/cpufunc_asm_armv5.S standard
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arm/arm/cpufunc_asm_armv6.S standard
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arm/arm/irq_dispatch.S standard
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kern/kern_clocksource.c standard
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@ -6,7 +6,6 @@ arm/econa/timer.c standard
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arm/econa/uart_bus_ec.c optional uart
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arm/econa/uart_cpu_ec.c optional uart
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dev/uart/uart_dev_ns8250.c optional uart
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arm/arm/irq_dispatch.S standard
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arm/arm/bus_space_generic.c standard
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arm/econa/ehci_ebus.c optional ehci
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arm/econa/ohci_ec.c optional ohci
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@ -4,7 +4,6 @@ arm/arm/bus_space_generic.c standard
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arm/arm/cpufunc_asm_armv5.S standard
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arm/arm/cpufunc_asm_arm11.S standard
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arm/arm/cpufunc_asm_armv7.S standard
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arm/arm/irq_dispatch.S standard
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kern/kern_clocksource.c standard
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# Init
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@ -4,7 +4,6 @@ arm/arm/bus_space_generic.c standard
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arm/arm/cpufunc_asm_armv5.S standard
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arm/arm/cpufunc_asm_arm11.S standard
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arm/arm/cpufunc_asm_armv7.S standard
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arm/arm/irq_dispatch.S standard
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kern/kern_clocksource.c standard
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# Init
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@ -8,7 +8,6 @@ arm/arm/bus_space_generic.c standard
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arm/arm/cpufunc_asm_arm11.S standard
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arm/arm/cpufunc_asm_armv5.S standard
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arm/arm/cpufunc_asm_armv7.S standard
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arm/arm/irq_dispatch.S standard
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kern/kern_clocksource.c standard
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#
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@ -8,7 +8,6 @@ arm/arm/cpufunc_asm_armv5.S standard
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arm/arm/cpufunc_asm_arm10.S standard
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arm/arm/cpufunc_asm_arm11.S standard
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arm/arm/cpufunc_asm_armv7.S standard
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arm/arm/irq_dispatch.S standard
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arm/arm/bus_space-v6.c standard
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arm/arm/gic.c standard
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@ -1,6 +1,5 @@
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# $FreeBSD$
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arm/arm/bus_space_generic.c standard
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arm/arm/irq_dispatch.S standard
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arm/arm/cpufunc_asm_arm9.S standard
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arm/arm/cpufunc_asm_armv5.S standard
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arm/lpc/lpc_machdep.c standard
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@ -20,7 +20,6 @@ arm/arm/cpufunc_asm_armv5_ec.S standard
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arm/arm/cpufunc_asm_armv7.S standard
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arm/arm/cpufunc_asm_sheeva.S standard
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arm/arm/cpufunc_asm_pj4b.S standard
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arm/arm/irq_dispatch.S standard
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arm/mv/bus_space.c standard
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arm/mv/gpio.c standard
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@ -7,7 +7,6 @@ arm/arm/cpufunc_asm_armv5.S standard
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arm/arm/cpufunc_asm_arm10.S standard
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arm/arm/cpufunc_asm_arm11.S standard
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arm/arm/cpufunc_asm_armv7.S standard
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arm/arm/irq_dispatch.S standard
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arm/arm/gic.c standard
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arm/arm/mpcore_timer.c standard
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@ -2,7 +2,6 @@
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arm/arm/bus_space_asm_generic.S standard
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arm/arm/bus_space_generic.c standard
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arm/arm/cpufunc_asm_arm9.S standard
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arm/arm/irq_dispatch.S standard
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arm/s3c2xx0/board_ln2410sbc.c optional board_ln2410sbc
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arm/s3c2xx0/s3c24x0_rtc.c standard
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arm/s3c2xx0/s3c24x0_machdep.c standard
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@ -8,7 +8,6 @@ arm/arm/cpufunc_asm_armv5.S standard
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arm/arm/cpufunc_asm_arm10.S standard
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arm/arm/cpufunc_asm_arm11.S standard
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arm/arm/cpufunc_asm_armv7.S standard
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arm/arm/irq_dispatch.S standard
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arm/arm/bus_space-v6.c standard
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arm/arm/gic.c standard
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@ -6,7 +6,6 @@ arm/arm/bus_space-v6.c standard
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arm/arm/cpufunc_asm_armv5.S standard
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arm/arm/cpufunc_asm_arm11.S standard
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arm/arm/cpufunc_asm_armv7.S standard
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arm/arm/irq_dispatch.S standard
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arm/arm/gic.c standard
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arm/arm/mpcore_timer.c standard
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@ -9,7 +9,6 @@ arm/arm/cpufunc_asm_armv5.S standard
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arm/arm/cpufunc_asm_arm10.S standard
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arm/arm/cpufunc_asm_arm11.S standard
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arm/arm/cpufunc_asm_armv7.S standard
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arm/arm/irq_dispatch.S standard
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arm/ti/ti_common.c standard
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arm/ti/ti_cpuid.c standard
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@ -6,7 +6,6 @@ arm/arm/cpufunc_asm_arm11.S standard
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arm/arm/cpufunc_asm_arm11x6.S standard
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arm/arm/cpufunc_asm_armv5.S standard
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arm/arm/cpufunc_asm_armv6.S standard
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arm/arm/irq_dispatch.S standard
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arm/versatile/bus_space.c standard
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arm/versatile/pl050.c optional sc
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@ -11,7 +11,6 @@ arm/arm/cpufunc_asm_armv5.S standard
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arm/arm/cpufunc_asm_arm10.S standard
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arm/arm/cpufunc_asm_arm11.S standard
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arm/arm/cpufunc_asm_armv7.S standard
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arm/arm/irq_dispatch.S standard
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arm/arm/gic.c standard
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arm/arm/mpcore_timer.c standard
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@ -4,7 +4,6 @@
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#
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arm/arm/bus_space_generic.c standard
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arm/arm/cpufunc_asm_xscale.S standard
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arm/arm/irq_dispatch.S standard
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arm/xscale/i80321/i80321.c standard
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arm/xscale/i80321/i80321_dma.c optional dma
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arm/xscale/i80321/i80321_mcu.c standard
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@ -1,7 +1,6 @@
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#$FreeBSD$
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arm/arm/bus_space_generic.c standard
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arm/arm/cpufunc_asm_xscale.S standard
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arm/arm/irq_dispatch.S standard
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arm/xscale/i80321/i80321.c standard
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arm/xscale/i80321/i80321_aau.c optional aau
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arm/xscale/i80321/i80321_dma.c optional dma
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@ -2,7 +2,6 @@
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arm/arm/bus_space_generic.c standard
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arm/arm/cpufunc_asm_xscale.S standard
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arm/arm/cpufunc_asm_xscale_c3.S standard
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arm/arm/irq_dispatch.S standard
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arm/xscale/i80321/i80321_timer.c standard
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arm/xscale/i80321/i80321_wdog.c optional iopwdog
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arm/xscale/i8134x/i81342.c standard
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@ -1,7 +1,6 @@
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#$FreeBSD$
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arm/arm/bus_space_generic.c standard
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arm/arm/cpufunc_asm_xscale.S standard
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arm/arm/irq_dispatch.S standard
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arm/xscale/ixp425/ixp425.c standard
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arm/xscale/ixp425/ixp425_mem.c standard
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arm/xscale/ixp425/ixp425_space.c standard
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@ -2,7 +2,6 @@
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arm/arm/bus_space_generic.c standard
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arm/arm/cpufunc_asm_xscale.S standard
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arm/arm/irq_dispatch.S standard
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arm/xscale/pxa/pxa_gpio.c standard
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arm/xscale/pxa/pxa_icu.c standard
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