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https://git.hardenedbsd.org/hardenedbsd/HardenedBSD.git
synced 2024-12-24 10:52:36 +01:00
Added support for newer cards that have the DP83840A PHY chip.
Fixed a bug in fxp_mdi_write - a hex number was missing a preceding 0x and this was causing the routine to not wait for a PHY write to complete. Added support for link0, link1, and link2 flags to toggle auto- negotiation, 10/100, and half/full duplex: link0 disable auto-negotiation When set, these flags then have meaning: -link1 10Mbps link1 100Mbps -link2 half duplex link2 full duplex ...needs a manual page.
This commit is contained in:
David Greenman
parent
8cd3868fee
commit
6ebc315326
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=24079
@ -24,7 +24,7 @@
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: if_fxp.c,v 1.29 1997/02/22 09:44:05 peter Exp $
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* $Id: if_fxp.c,v 1.30 1997/03/17 11:08:14 davidg Exp $
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*/
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/*
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@ -962,12 +962,39 @@ fxp_init(xsc)
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/*
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* Toggle a few bits in the DP83840 PHY.
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*/
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if (sc->phy_primary_device == FXP_PHY_DP83840) {
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if (sc->phy_primary_device == FXP_PHY_DP83840 ||
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sc->phy_primary_device == FXP_PHY_DP83840A) {
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fxp_mdi_write(sc->csr, sc->phy_primary_addr, FXP_DP83840_PCR,
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fxp_mdi_read(sc->csr, sc->phy_primary_addr, FXP_DP83840_PCR) |
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FXP_DP83840_PCR_LED4_MODE | /* LED4 always indicates duplex */
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FXP_DP83840_PCR_F_CONNECT | /* force link disconnect bypass */
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FXP_DP83840_PCR_BIT10); /* XXX I have no idea */
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/*
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* If link0 is set, disable auto-negotiation and then:
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* If link1 is unset = 10Mbps
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* If link1 is set = 100Mbps
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* If link2 is unset = half duplex
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* If link2 is set = full duplex
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*/
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if (ifp->if_flags & IFF_LINK0) {
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int flags;
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flags = (ifp->if_flags & IFF_LINK1) ?
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FXP_DP83840_BMCR_SPEED_100M : 0;
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flags |= (ifp->if_flags & IFF_LINK2) ?
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FXP_DP83840_BMCR_FULLDUPLEX : 0;
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fxp_mdi_write(sc->csr, sc->phy_primary_addr, FXP_DP83840_BMCR,
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(fxp_mdi_read(sc->csr, sc->phy_primary_addr, FXP_DP83840_BMCR) &
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~(FXP_DP83840_BMCR_AUTOEN | FXP_DP83840_BMCR_SPEED_100M |
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FXP_DP83840_BMCR_FULLDUPLEX)) | flags);
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} else {
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fxp_mdi_write(sc->csr, sc->phy_primary_addr, FXP_DP83840_BMCR,
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(fxp_mdi_read(sc->csr, sc->phy_primary_addr, FXP_DP83840_BMCR) |
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FXP_DP83840_BMCR_AUTOEN));
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}
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} else {
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printf("fxp%d: warning: unsupported PHY, type = %d, addr = %d\n",
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ifp->if_unit, sc->phy_primary_device, sc->phy_primary_addr);
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}
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ifp->if_flags |= IFF_RUNNING;
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@ -1042,23 +1069,24 @@ fxp_add_rfabuf(sc, oldm)
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return (m == oldm);
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}
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static int
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static volatile int
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fxp_mdi_read(csr, phy, reg)
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struct fxp_csr *csr;
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int phy;
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int reg;
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{
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int count = 10000;
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int value;
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csr->mdi_control = (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21);
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while ((csr->mdi_control & 0x10000000) == 0 && count--)
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DELAY(1);
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while (((value = csr->mdi_control) & 0x10000000) == 0 && count--)
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DELAY(10);
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if (count <= 0)
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printf("fxp_mdi_read: timed out\n");
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return (csr->mdi_control & 0xffff);
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return (value & 0xffff);
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}
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static void
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@ -1073,8 +1101,8 @@ fxp_mdi_write(csr, phy, reg, value)
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csr->mdi_control = (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21)
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| (value & 0xffff);
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while ((csr->mdi_control & 10000000) == 0 && count--)
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DELAY(1);
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while ((csr->mdi_control & 0x10000000) == 0 && count--)
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DELAY(10);
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if (count <= 0)
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printf("fxp_mdi_write: timed out\n");
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@ -24,7 +24,7 @@
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: if_fxpreg.h,v 1.6 1997/02/22 09:44:06 peter Exp $
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* $Id: if_fxpreg.h,v 1.7 1997/03/17 11:08:16 davidg Exp $
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*/
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#define FXP_VENDORID_INTEL 0x8086
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@ -292,6 +292,15 @@ struct fxp_stats {
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#define FXP_PHY_DP83840 4
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#define FXP_PHY_80C240 5
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#define FXP_PHY_80C24 6
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#define FXP_PHY_DP83840A 10
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/*
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* DP84830 PHY, BMCR Basic Mode Control Register
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*/
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#define FXP_DP83840_BMCR 0x0
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#define FXP_DP83840_BMCR_FULLDUPLEX 0x0100
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#define FXP_DP83840_BMCR_AUTOEN 0x1000
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#define FXP_DP83840_BMCR_SPEED_100M 0x2000
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/*
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* DP84830 PHY, PCS Configuration Register
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@ -24,7 +24,7 @@
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: if_fxp.c,v 1.29 1997/02/22 09:44:05 peter Exp $
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* $Id: if_fxp.c,v 1.30 1997/03/17 11:08:14 davidg Exp $
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*/
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/*
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@ -962,12 +962,39 @@ fxp_init(xsc)
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/*
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* Toggle a few bits in the DP83840 PHY.
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*/
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if (sc->phy_primary_device == FXP_PHY_DP83840) {
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if (sc->phy_primary_device == FXP_PHY_DP83840 ||
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sc->phy_primary_device == FXP_PHY_DP83840A) {
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fxp_mdi_write(sc->csr, sc->phy_primary_addr, FXP_DP83840_PCR,
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fxp_mdi_read(sc->csr, sc->phy_primary_addr, FXP_DP83840_PCR) |
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FXP_DP83840_PCR_LED4_MODE | /* LED4 always indicates duplex */
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FXP_DP83840_PCR_F_CONNECT | /* force link disconnect bypass */
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FXP_DP83840_PCR_BIT10); /* XXX I have no idea */
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/*
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* If link0 is set, disable auto-negotiation and then:
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* If link1 is unset = 10Mbps
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* If link1 is set = 100Mbps
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* If link2 is unset = half duplex
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* If link2 is set = full duplex
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*/
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if (ifp->if_flags & IFF_LINK0) {
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int flags;
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flags = (ifp->if_flags & IFF_LINK1) ?
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FXP_DP83840_BMCR_SPEED_100M : 0;
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flags |= (ifp->if_flags & IFF_LINK2) ?
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FXP_DP83840_BMCR_FULLDUPLEX : 0;
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fxp_mdi_write(sc->csr, sc->phy_primary_addr, FXP_DP83840_BMCR,
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(fxp_mdi_read(sc->csr, sc->phy_primary_addr, FXP_DP83840_BMCR) &
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~(FXP_DP83840_BMCR_AUTOEN | FXP_DP83840_BMCR_SPEED_100M |
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FXP_DP83840_BMCR_FULLDUPLEX)) | flags);
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} else {
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fxp_mdi_write(sc->csr, sc->phy_primary_addr, FXP_DP83840_BMCR,
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(fxp_mdi_read(sc->csr, sc->phy_primary_addr, FXP_DP83840_BMCR) |
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FXP_DP83840_BMCR_AUTOEN));
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}
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} else {
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printf("fxp%d: warning: unsupported PHY, type = %d, addr = %d\n",
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ifp->if_unit, sc->phy_primary_device, sc->phy_primary_addr);
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}
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ifp->if_flags |= IFF_RUNNING;
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@ -1042,23 +1069,24 @@ fxp_add_rfabuf(sc, oldm)
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return (m == oldm);
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}
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static int
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static volatile int
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fxp_mdi_read(csr, phy, reg)
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struct fxp_csr *csr;
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int phy;
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int reg;
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{
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int count = 10000;
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int value;
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csr->mdi_control = (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21);
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while ((csr->mdi_control & 0x10000000) == 0 && count--)
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DELAY(1);
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while (((value = csr->mdi_control) & 0x10000000) == 0 && count--)
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DELAY(10);
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if (count <= 0)
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printf("fxp_mdi_read: timed out\n");
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return (csr->mdi_control & 0xffff);
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return (value & 0xffff);
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}
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static void
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@ -1073,8 +1101,8 @@ fxp_mdi_write(csr, phy, reg, value)
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csr->mdi_control = (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21)
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| (value & 0xffff);
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while ((csr->mdi_control & 10000000) == 0 && count--)
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DELAY(1);
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while ((csr->mdi_control & 0x10000000) == 0 && count--)
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DELAY(10);
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if (count <= 0)
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printf("fxp_mdi_write: timed out\n");
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@ -24,7 +24,7 @@
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: if_fxpreg.h,v 1.6 1997/02/22 09:44:06 peter Exp $
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* $Id: if_fxpreg.h,v 1.7 1997/03/17 11:08:16 davidg Exp $
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*/
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#define FXP_VENDORID_INTEL 0x8086
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@ -292,6 +292,15 @@ struct fxp_stats {
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#define FXP_PHY_DP83840 4
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#define FXP_PHY_80C240 5
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#define FXP_PHY_80C24 6
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#define FXP_PHY_DP83840A 10
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/*
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* DP84830 PHY, BMCR Basic Mode Control Register
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*/
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#define FXP_DP83840_BMCR 0x0
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#define FXP_DP83840_BMCR_FULLDUPLEX 0x0100
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#define FXP_DP83840_BMCR_AUTOEN 0x1000
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#define FXP_DP83840_BMCR_SPEED_100M 0x2000
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/*
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* DP84830 PHY, PCS Configuration Register
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