Add kdb_cpu_sync_icache(), intended to synchronize instruction

caches with data caches after writing to memory. This typically
is required to make breakpoints work on ia64 and powerpc. For
those architectures the function is implemented.

sys/amd64/include/kdb.h

@@ -46,6 +46,11 @@ kdb_cpu_set_singlestep(void)
 	kdb_frame->tf_rflags |= PSL_T;
 }
 
+static __inline void
+kdb_cpu_sync_icache(unsigned char *addr, size_t size)
+{
+}
+
 static __inline void
 kdb_cpu_trap(int type, int code)
 {

sys/arm/include/kdb.h

@@ -43,6 +43,11 @@ kdb_cpu_set_singlestep(void)
 {
 }
 
+static __inline void
+kdb_cpu_sync_icache(unsigned char *addr, size_t size)
+{
+}
+
 static __inline void
 kdb_cpu_trap(int type, int code)
 {

sys/gdb/gdb_packet.c

@@ -33,6 +33,7 @@ __FBSDID("$FreeBSD$");
 #include <sys/kdb.h>
 
 #include <machine/gdb_machdep.h>
+#include <machine/kdb.h>
 
 #include <gdb/gdb.h>
 #include <gdb/gdb_int.h>
@@ -129,8 +130,10 @@ gdb_rx_equal(const char *str)
 int
 gdb_rx_mem(unsigned char *addr, size_t size)
 {
+	unsigned char *p;
 	void *prev;
 	jmp_buf jb;
+	size_t cnt;
 	int ret;
 	unsigned char c;
 
@@ -140,13 +143,16 @@ gdb_rx_mem(unsigned char *addr, size_t size)
 	prev = kdb_jmpbuf(jb);
 	ret = setjmp(jb);
 	if (ret == 0) {
-		while (size-- > 0) {
+		p = addr;
+		cnt = size;
+		while (cnt-- > 0) {
 			c = (C2N(gdb_rxp[0]) << 4) & 0xf0;
 			c |= C2N(gdb_rxp[1]) & 0x0f;
-			*addr++ = c;
+			*p++ = c;
 			gdb_rxsz -= 2;
 			gdb_rxp += 2;
 		}
+		kdb_cpu_sync_icache(addr, size);
 	}
 	(void)kdb_jmpbuf(prev);
 	return ((ret == 0) ? 1 : 0);

sys/i386/include/kdb.h

@@ -46,6 +46,11 @@ kdb_cpu_set_singlestep(void)
 	kdb_frame->tf_eflags |= PSL_T;
 }
 
+static __inline void
+kdb_cpu_sync_icache(unsigned char *addr, size_t size)
+{
+}
+
 static __inline void
 kdb_cpu_trap(int type, int code)
 {

sys/ia64/include/kdb.h

@@ -47,6 +47,21 @@ kdb_cpu_set_singlestep(void)
 	kdb_frame->tf_special.psr |= IA64_PSR_SS;
 }
 
+static __inline void
+kdb_cpu_sync_icache(unsigned char *addr, size_t size)
+{
+	vm_offset_t cacheline;
+
+	cacheline = (uintptr_t)addr & ~31;
+	size += (uintptr_t)addr - cacheline;
+	size = (size + 31) & ~31;
+	while (size > 0) {
+		__asm __volatile("fc %0;; sync.i;; srlz.i;;" :: "r"(cacheline));
+		cacheline += 32;
+		size -= 32;
+	}
+}
+
 static __inline void
 kdb_cpu_trap(int vector, int _)
 {

sys/powerpc/aim/uio_machdep.c

@@ -49,7 +49,7 @@ __FBSDID("$FreeBSD$");
 #include <vm/vm.h>
 #include <vm/vm_page.h>
 
-#include <machine/cpu.h>
+#include <machine/md_var.h>
 #include <machine/vmparam.h>
 
 /*

sys/powerpc/include/cpu.h

@@ -45,12 +45,6 @@
 #define	cpu_swapout(p)
 #define	cpu_number()		0
 
-#if defined(_KERNEL) || defined(_STANDALONE)
-#define	CACHELINESIZE	32
-#endif
-
-extern void __syncicache(void *, int);
-
 /*
  * CTL_MACHDEP definitions.
  */

sys/powerpc/include/kdb.h

@@ -31,6 +31,7 @@
 
 #include <machine/cpufunc.h>
 #include <machine/frame.h>
+#include <machine/md_var.h>
 #include <machine/psl.h>
 
 static __inline void
@@ -45,6 +46,12 @@ kdb_cpu_set_singlestep(void)
 	kdb_frame->srr1 |= PSL_SE;
 }
 
+static __inline void
+kdb_cpu_sync_icache(unsigned char *addr, size_t size)
+{
+	__syncicache(addr, size);
+}
+
 static __inline void
 kdb_cpu_trap(int vector, int _)
 {

sys/powerpc/include/md_var.h

@@ -50,6 +50,12 @@ struct reg;
 struct cam_sim;
 struct pcicfg;
 
+#if defined(_KERNEL) || defined(_STANDALONE)
+#define	CACHELINESIZE	32
+#endif
+
+void	__syncicache(void *, int);
+
 void	busdma_swi(void);
 int	is_physical_memory(vm_offset_t addr);
 int	mem_valid(vm_offset_t addr, int len);

sys/powerpc/powerpc/db_interface.c

@@ -13,7 +13,7 @@
 #include <sys/proc.h>
 #include <sys/smp.h>
 
-#include <machine/cpu.h>
+#include <machine/kdb.h>
 #include <machine/md_var.h>
 
 #include <vm/vm.h>
@@ -58,23 +58,19 @@ db_write_bytes(vm_offset_t addr, size_t size, char *data)
 	jmp_buf jb;
 	void *prev_jb;
 	char *dst;
+	size_t cnt;
 	int ret;
 
 	prev_jb = kdb_jmpbuf(jb);
 	ret = setjmp(jb);
 	if (ret == 0) {
 		dst = (char *)addr;
+		cnt = size;
 
-		if (size == 4)
-			*((int *)dst) = *((int *)data);
-		else if (size == 2)
-			*((short *)dst) = *((short *)data);
-		else
-			while (size-- > 0)
-				*dst++ = *data++;
+		while (cnt-- > 0)
+			*dst++ = *data++;
+		kdb_cpu_sync_icache((void *)addr, size);
 	}
-	__syncicache((void *)addr, size);
-
 	(void)kdb_jmpbuf(prev_jb);
 	return (ret);
 }

sys/powerpc/powerpc/syncicache.c

@@ -42,7 +42,7 @@ __FBSDID("$FreeBSD$");
 #endif
 #include <sys/sysctl.h>
 
-#include <machine/cpu.h>
+#include <machine/md_var.h>
 
 #if	defined(_KERNEL) || defined(_STANDALONE)
 #ifndef	CACHELINESIZE

sys/powerpc/powerpc/uio_machdep.c

@@ -49,7 +49,7 @@ __FBSDID("$FreeBSD$");
 #include <vm/vm.h>
 #include <vm/vm_page.h>
 
-#include <machine/cpu.h>
+#include <machine/md_var.h>
 #include <machine/vmparam.h>
 
 /*

sys/sparc64/include/kdb.h

@@ -43,6 +43,11 @@ kdb_cpu_set_singlestep(void)
 {
 }
 
+static __inline void
+kdb_cpu_sync_icache(unsigned char *addr, size_t size)
+{
+}
+
 static __inline void
 kdb_cpu_trap(int vector, int _)
 {

sys/sun4v/include/kdb.h

@@ -41,6 +41,11 @@ kdb_cpu_set_singlestep(void)
 {
 }
 
+static __inline void
+kdb_cpu_sync_icache(unsigned char *addr, size_t size)
+{
+}
+
 static __inline void
 kdb_cpu_trap(int vector, int _)
 {