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Clean up and update comments for CPUTYPE.
Requested by: rdivacky
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=243315
@ -25,22 +25,27 @@
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# The CPUTYPE variable controls which processor should be targeted for
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# generated code. This controls processor-specific optimizations in
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# certain code (currently only OpenSSL) as well as modifying the value
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# of CFLAGS to contain the appropriate optimization directive to gcc.
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# of CFLAGS to contain the appropriate optimization directive to cc.
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# The automatic setting of CFLAGS may be overridden using the
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# NO_CPU_CFLAGS variable below.
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# Currently the following CPU types are recognized:
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# Currently the following CPU types are recognized by gcc:
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# Intel x86 architecture:
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# (AMD CPUs) opteron-sse3 opteron athlon64-sse3 athlon64 athlon-mp
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# athlon-xp athlon-4 athlon-tbird athlon k8-sse3 k8
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# geode k6-3 k6-2 k6 k5
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# (Intel CPUs) core2 core nocona pentium4m pentium4 prescott
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# pentium3m pentium3 pentium-m pentium2
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# pentiumpro pentium-mmx pentium i486 i386
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# (Via CPUs) c3 c3-2
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# AMD64 architecture: opteron, athlon64, nocona, prescott, core2
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# Intel ia64 architecture: itanium2, itanium
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# (AMD CPUs) opteron-sse3, athlon64-sse3, k8-sse3, opteron,
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# athlon64, k8, athlon-mp, athlon-xp, athlon-4,
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# athlon-tbird, athlon, k7, geode, k6-3, k6-2, k6, k5
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# (Intel CPUs) core2, core, nocona, pentium4m, pentium4, prescott,
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# pentium3m, pentium3, pentium-m, pentium2,
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# pentiumpro, pentium-mmx, pentium, i486, i386
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# (VIA CPUs) c7, c3-2, c3
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# AMD64 architecture: opteron-sse3, athlon64-sse3, k8-sse3, opteron,
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# athlon64, k8, core2, nocona, prescott
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# Intel ia64 architecture: itanium2, itanium
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# SPARC-V9 architecture: v9 (generic 64-bit V9), ultrasparc (default
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# if omitted), ultrasparc3
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# Additionally the following CPU types are recognized by clang:
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# Intel x86 architecture (for both amd64 and i386):
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# (AMD CPUs) bdver2, bdver1, btver1, amdfam10
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# (Intel CPUs) core-avx-i, corei7-avx, corei7
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#
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# (?= allows to buildworld for a different CPUTYPE.)
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#
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