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Further fixes for multiple-IO-APIC systems from Tor Egge:
Further experimentation showed that some Dell 2450 machines with the prevention kludge installed still got T_RESERVED traps. CPU interrupt vector 0x7A was observed to be triggered. This might have been the bitwise OR of two different vectors sent from each of the IOAPICs at the same time. IOAPIC #0: 0x68 --> irq 8: RTC timer interrupt IOAPIC #1: 0x32 --> irq 18: scsi host adapter or network interface ---- 0x7a --> T_RESERVED Both IOAPICs had ID 0. Appendix B.3 in the MP spec indicates that the operating system is responsible for assigning unique IDs to the IOAPICs. The enclosed patch programs the IOAPIC IDs according to the IOAPIC entries in the MP table. Submitted by: tegge
This commit is contained in:
parent
92e24ad483
commit
c3c50c4e3a
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=61136
@ -572,6 +572,7 @@ mp_enable(u_int boot_addr)
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for (apic = 0; apic < mp_napics; ++apic) {
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ux = io_apic_read(apic, IOAPIC_VER);
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io_apic_versions[apic] = ux;
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io_apic_set_id(apic, IO_TO_ID(apic));
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}
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/* program each IO APIC in the system */
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@ -1661,13 +1662,7 @@ default_mp_table(int type)
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#else
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if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
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#endif /* REALLY_ANAL_IOAPICID_VALUE */
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ux = io_apic_read(0, IOAPIC_ID); /* get current contents */
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ux &= ~APIC_ID_MASK; /* clear the ID field */
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ux |= 0x02000000; /* set it to '2' */
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io_apic_write(0, IOAPIC_ID, ux); /* write new value */
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ux = io_apic_read(0, IOAPIC_ID); /* re-read && test */
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if ((ux & APIC_ID_MASK) != 0x02000000)
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panic("can't control IO APIC ID, reg: 0x%08x", ux);
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io_apic_set_id(0, 2);
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io_apic_id = 2;
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}
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IO_TO_ID(0) = io_apic_id;
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@ -572,6 +572,7 @@ mp_enable(u_int boot_addr)
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for (apic = 0; apic < mp_napics; ++apic) {
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ux = io_apic_read(apic, IOAPIC_VER);
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io_apic_versions[apic] = ux;
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io_apic_set_id(apic, IO_TO_ID(apic));
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}
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/* program each IO APIC in the system */
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@ -1661,13 +1662,7 @@ default_mp_table(int type)
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#else
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if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
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#endif /* REALLY_ANAL_IOAPICID_VALUE */
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ux = io_apic_read(0, IOAPIC_ID); /* get current contents */
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ux &= ~APIC_ID_MASK; /* clear the ID field */
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ux |= 0x02000000; /* set it to '2' */
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io_apic_write(0, IOAPIC_ID, ux); /* write new value */
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ux = io_apic_read(0, IOAPIC_ID); /* re-read && test */
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if ((ux & APIC_ID_MASK) != 0x02000000)
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panic("can't control IO APIC ID, reg: 0x%08x", ux);
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io_apic_set_id(0, 2);
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io_apic_id = 2;
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}
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IO_TO_ID(0) = io_apic_id;
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@ -572,6 +572,7 @@ mp_enable(u_int boot_addr)
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for (apic = 0; apic < mp_napics; ++apic) {
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ux = io_apic_read(apic, IOAPIC_VER);
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io_apic_versions[apic] = ux;
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io_apic_set_id(apic, IO_TO_ID(apic));
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}
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/* program each IO APIC in the system */
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@ -1661,13 +1662,7 @@ default_mp_table(int type)
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#else
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if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
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#endif /* REALLY_ANAL_IOAPICID_VALUE */
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ux = io_apic_read(0, IOAPIC_ID); /* get current contents */
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ux &= ~APIC_ID_MASK; /* clear the ID field */
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ux |= 0x02000000; /* set it to '2' */
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io_apic_write(0, IOAPIC_ID, ux); /* write new value */
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ux = io_apic_read(0, IOAPIC_ID); /* re-read && test */
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if ((ux & APIC_ID_MASK) != 0x02000000)
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panic("can't control IO APIC ID, reg: 0x%08x", ux);
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io_apic_set_id(0, 2);
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io_apic_id = 2;
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}
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IO_TO_ID(0) = io_apic_id;
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@ -165,6 +165,7 @@ void imen_dump __P((void));
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int apic_ipi __P((int, int, int));
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int selected_apic_ipi __P((u_int, int, int));
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int io_apic_setup __P((int));
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void io_apic_set_id __P((int, int));
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int ext_int_setup __P((int, int));
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#if defined(READY)
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@ -572,6 +572,7 @@ mp_enable(u_int boot_addr)
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for (apic = 0; apic < mp_napics; ++apic) {
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ux = io_apic_read(apic, IOAPIC_VER);
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io_apic_versions[apic] = ux;
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io_apic_set_id(apic, IO_TO_ID(apic));
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}
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/* program each IO APIC in the system */
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@ -1661,13 +1662,7 @@ default_mp_table(int type)
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#else
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if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
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#endif /* REALLY_ANAL_IOAPICID_VALUE */
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ux = io_apic_read(0, IOAPIC_ID); /* get current contents */
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ux &= ~APIC_ID_MASK; /* clear the ID field */
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ux |= 0x02000000; /* set it to '2' */
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io_apic_write(0, IOAPIC_ID, ux); /* write new value */
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ux = io_apic_read(0, IOAPIC_ID); /* re-read && test */
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if ((ux & APIC_ID_MASK) != 0x02000000)
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panic("can't control IO APIC ID, reg: 0x%08x", ux);
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io_apic_set_id(0, 2);
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io_apic_id = 2;
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}
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IO_TO_ID(0) = io_apic_id;
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@ -143,6 +143,24 @@ static void polarity __P((int apic, int pin, u_int32_t * flags, int level));
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IOART_DESTPHY | \
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IOART_DELLOPRI))
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void
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io_apic_set_id(int apic, int id)
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{
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u_int32_t ux;
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ux = io_apic_read(apic, IOAPIC_ID); /* get current contents */
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if (((ux & APIC_ID_MASK) >> 24) != id) {
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ux &= ~APIC_ID_MASK; /* clear the ID field */
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ux |= (id << 24);
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io_apic_write(apic, IOAPIC_ID, ux); /* write new value */
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ux = io_apic_read(apic, IOAPIC_ID); /* re-read && test */
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if (((ux & APIC_ID_MASK) >> 24) != id)
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panic("can't control IO APIC #%d ID, reg: 0x%08x",
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apic, ux);
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}
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}
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/*
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* Setup the IO APIC.
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*/
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@ -572,6 +572,7 @@ mp_enable(u_int boot_addr)
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for (apic = 0; apic < mp_napics; ++apic) {
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ux = io_apic_read(apic, IOAPIC_VER);
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io_apic_versions[apic] = ux;
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io_apic_set_id(apic, IO_TO_ID(apic));
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}
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/* program each IO APIC in the system */
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@ -1661,13 +1662,7 @@ default_mp_table(int type)
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#else
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if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
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#endif /* REALLY_ANAL_IOAPICID_VALUE */
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ux = io_apic_read(0, IOAPIC_ID); /* get current contents */
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ux &= ~APIC_ID_MASK; /* clear the ID field */
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ux |= 0x02000000; /* set it to '2' */
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io_apic_write(0, IOAPIC_ID, ux); /* write new value */
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ux = io_apic_read(0, IOAPIC_ID); /* re-read && test */
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if ((ux & APIC_ID_MASK) != 0x02000000)
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panic("can't control IO APIC ID, reg: 0x%08x", ux);
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io_apic_set_id(0, 2);
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io_apic_id = 2;
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}
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IO_TO_ID(0) = io_apic_id;
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@ -572,6 +572,7 @@ mp_enable(u_int boot_addr)
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for (apic = 0; apic < mp_napics; ++apic) {
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ux = io_apic_read(apic, IOAPIC_VER);
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io_apic_versions[apic] = ux;
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io_apic_set_id(apic, IO_TO_ID(apic));
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}
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/* program each IO APIC in the system */
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@ -1661,13 +1662,7 @@ default_mp_table(int type)
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#else
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if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
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#endif /* REALLY_ANAL_IOAPICID_VALUE */
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ux = io_apic_read(0, IOAPIC_ID); /* get current contents */
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ux &= ~APIC_ID_MASK; /* clear the ID field */
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ux |= 0x02000000; /* set it to '2' */
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io_apic_write(0, IOAPIC_ID, ux); /* write new value */
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ux = io_apic_read(0, IOAPIC_ID); /* re-read && test */
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if ((ux & APIC_ID_MASK) != 0x02000000)
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panic("can't control IO APIC ID, reg: 0x%08x", ux);
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io_apic_set_id(0, 2);
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io_apic_id = 2;
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}
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IO_TO_ID(0) = io_apic_id;
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@ -165,6 +165,7 @@ void imen_dump __P((void));
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int apic_ipi __P((int, int, int));
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int selected_apic_ipi __P((u_int, int, int));
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int io_apic_setup __P((int));
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void io_apic_set_id __P((int, int));
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int ext_int_setup __P((int, int));
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#if defined(READY)
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@ -572,6 +572,7 @@ mp_enable(u_int boot_addr)
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for (apic = 0; apic < mp_napics; ++apic) {
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ux = io_apic_read(apic, IOAPIC_VER);
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io_apic_versions[apic] = ux;
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io_apic_set_id(apic, IO_TO_ID(apic));
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}
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/* program each IO APIC in the system */
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@ -1661,13 +1662,7 @@ default_mp_table(int type)
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#else
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if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
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#endif /* REALLY_ANAL_IOAPICID_VALUE */
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ux = io_apic_read(0, IOAPIC_ID); /* get current contents */
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ux &= ~APIC_ID_MASK; /* clear the ID field */
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ux |= 0x02000000; /* set it to '2' */
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io_apic_write(0, IOAPIC_ID, ux); /* write new value */
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ux = io_apic_read(0, IOAPIC_ID); /* re-read && test */
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if ((ux & APIC_ID_MASK) != 0x02000000)
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panic("can't control IO APIC ID, reg: 0x%08x", ux);
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io_apic_set_id(0, 2);
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io_apic_id = 2;
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}
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IO_TO_ID(0) = io_apic_id;
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@ -165,6 +165,7 @@ void imen_dump __P((void));
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int apic_ipi __P((int, int, int));
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int selected_apic_ipi __P((u_int, int, int));
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int io_apic_setup __P((int));
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void io_apic_set_id __P((int, int));
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int ext_int_setup __P((int, int));
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#if defined(READY)
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