diff --git a/sys/x86/include/specialreg.h b/sys/x86/include/specialreg.h
index b4b95670e367..3115056ce14c 100644
--- a/sys/x86/include/specialreg.h
+++ b/sys/x86/include/specialreg.h
@@ -397,21 +397,31 @@
 #define	AMDFEID_CLZERO		0x00000001
 #define	AMDFEID_IRPERF		0x00000002
 #define	AMDFEID_XSAVEERPTR	0x00000004
+#define	AMDFEID_INVLPGB		0x00000008
 #define	AMDFEID_RDPRU		0x00000010
+#define	AMDFEID_BE		0x00000040
 #define	AMDFEID_MCOMMIT		0x00000100
 #define	AMDFEID_WBNOINVD	0x00000200
 #define	AMDFEID_IBPB		0x00001000
+#define	AMDFEID_INT_WBINVD	0x00002000
 #define	AMDFEID_IBRS		0x00004000
 #define	AMDFEID_STIBP		0x00008000
 /* The below are only defined if the corresponding base feature above exists. */
 #define	AMDFEID_IBRS_ALWAYSON	0x00010000
 #define	AMDFEID_STIBP_ALWAYSON	0x00020000
 #define	AMDFEID_PREFER_IBRS	0x00040000
+#define	AMDFEID_SAMEMODE_IBRS	0x00080000
+#define	AMDFEID_NO_LMSLE	0x00100000
+#define	AMDFEID_INVLPGB_NEST	0x00200000
 #define	AMDFEID_PPIN		0x00800000
 #define	AMDFEID_SSBD		0x01000000
 /* SSBD via MSRC001_011F instead of MSR 0x48: */
 #define	AMDFEID_VIRT_SSBD	0x02000000
 #define	AMDFEID_SSB_NO		0x04000000
+#define	AMDFEID_CPPC		0x08000000
+#define	AMDFEID_PSFD		0x10000000
+#define	AMDFEID_BTC_NO		0x20000000
+#define	AMDFEID_IBPB_RET	0x40000000
 
 /*
  * AMD extended function 8000_0008h ecx info
@@ -420,6 +430,13 @@
 #define	AMDID_COREID_SIZE	0x0000f000
 #define	AMDID_COREID_SIZE_SHIFT	12
 
+/*
+ * AMD extended function 8000_0008h edx info
+ */
+#define	AMDID_INVLPGB_MAXCNT	0x0000ffff
+#define	AMDID_RDPRU_SHIFT	16
+#define	AMDID_RDPRU_ID		0xffff0000
+
 /*
  * CPUID instruction 7 Structured Extended Features, leaf 0 ebx info
  */
diff --git a/sys/x86/include/x86_var.h b/sys/x86/include/x86_var.h
index f3677d84570b..f19c557e270b 100644
--- a/sys/x86/include/x86_var.h
+++ b/sys/x86/include/x86_var.h
@@ -57,6 +57,7 @@ extern	u_int	cpu_max_ext_state_size;
 extern	u_int	cpu_mxcsr_mask;
 extern	u_int	cpu_procinfo;
 extern	u_int	cpu_procinfo2;
+extern	u_int	cpu_procinfo3;
 extern	char	cpu_vendor[];
 extern	char	cpu_model[];
 extern	u_int	cpu_vendor_id;
diff --git a/sys/x86/x86/identcpu.c b/sys/x86/x86/identcpu.c
index 953736d6b25c..4da250c535a0 100644
--- a/sys/x86/x86/identcpu.c
+++ b/sys/x86/x86/identcpu.c
@@ -106,6 +106,7 @@ u_int	cpu_exthigh;		/* Highest arg to extended CPUID */
 u_int	cpu_id;			/* Stepping ID */
 u_int	cpu_procinfo;		/* HyperThreading Info / Brand Index / CLFUSH */
 u_int	cpu_procinfo2;		/* Multicore info */
+u_int	cpu_procinfo3;
 char	cpu_vendor[20];		/* CPU Origin code */
 u_int	cpu_vendor_id;		/* CPU vendor ID */
 u_int	cpu_mxcsr_mask;		/* Valid bits in mxcsr */
@@ -1089,19 +1090,29 @@ printcpuinfo(void)
 				    "\001CLZERO"
 				    "\002IRPerf"
 				    "\003XSaveErPtr"
+				    "\004INVLPGB"
 				    "\005RDPRU"
+				    "\007BE"
 				    "\011MCOMMIT"
 				    "\012WBNOINVD"
 				    "\015IBPB"
+				    "\016INT_WBINVD"
 				    "\017IBRS"
 				    "\020STIBP"
 				    "\021IBRS_ALWAYSON"
 				    "\022STIBP_ALWAYSON"
 				    "\023PREFER_IBRS"
+				    "\024SAMEMODE_IBRS"
+				    "\025NOLMSLE"
+				    "\026INVLPGBNEST"
 				    "\030PPIN"
 				    "\031SSBD"
 				    "\032VIRT_SSBD"
 				    "\033SSB_NO"
+				    "\034CPPC"
+				    "\035PSFD"
+				    "\036BTC_NO"
+				    "\037IBPB_RET"
 				    );
 			}
 
@@ -1664,6 +1675,7 @@ finishidentcpu(void)
 		cpu_maxphyaddr = regs[0] & 0xff;
 		amd_extended_feature_extensions = regs[1];
 		cpu_procinfo2 = regs[2];
+		cpu_procinfo3 = regs[3];
 	} else {
 		cpu_maxphyaddr = (cpu_feature & CPUID_PAE) != 0 ? 36 : 32;
 	}