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Add function for mapping SRAM-D area to USB0 (OTG) controller. Use a lower

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pass number to ensure that this driver is loaded before EMAC or OTG,
regardless of the order of nodes in the DT.
This commit is contained in:
Jared McNeill 2016-04-08 10:54:59 +00:00
parent b715d9af68
commit ce45969226
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=297703
2 changed files with 21 additions and 1 deletions
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21
sys/arm/allwinner/a10_sramc.c
View File

@ -52,6 +52,7 @@ __FBSDID("$FreeBSD$");
#include "a10_sramc.h"
#define SRAM_CTL1_CFG 0x04
#define CTL1_CFG_SRAMD_MAP_USB0 (1 << 0)
struct a10_sramc_softc {
struct resource *res;
@ -113,7 +114,8 @@ static driver_t a10_sramc_driver = {
static devclass_t a10_sramc_devclass;
DRIVER_MODULE(a10_sramc, simplebus, a10_sramc_driver, a10_sramc_devclass, 0, 0);
EARLY_DRIVER_MODULE(a10_sramc, simplebus, a10_sramc_driver, a10_sramc_devclass,
0, 0, BUS_PASS_RESOURCE + BUS_PASS_ORDER_EARLY);
int
a10_map_to_emac(void)
@ -131,3 +133,20 @@ a10_map_to_emac(void)
return (0);
}
int
a10_map_to_otg(void)
{
struct a10_sramc_softc *sc = a10_sramc_sc;
uint32_t reg_value;
if (sc == NULL)
return (ENXIO);
/* Map SRAM to OTG */
reg_value = sramc_read_4(sc, SRAM_CTL1_CFG);
reg_value |= CTL1_CFG_SRAMD_MAP_USB0;
sramc_write_4(sc, SRAM_CTL1_CFG, reg_value);
return (0);
}

1
sys/arm/allwinner/a10_sramc.h
View File

@ -30,5 +30,6 @@
#define _A10_SRAMC_H_
int a10_map_to_emac(void);
int a10_map_to_otg(void);
#endif