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https://git.hardenedbsd.org/hardenedbsd/HardenedBSD.git
synced 2025-01-11 17:04:19 +01:00
Renamed TRUE (which has value 2) to M_TR to avoid a clash with the
the boolean TRUE.
This commit is contained in:
Bruce Evans
parent
3b8511179e
commit
d74abd4029
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=12641
@ -1,6 +1,6 @@
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/**************************************************************************
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**
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** $Id: pcisupport.c,v 1.21 1995/09/14 13:13:33 se Exp $
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** $Id: pcisupport.c,v 1.22 1995/09/14 17:26:24 se Exp $
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**
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** Device driver for DEC/INTEL PCI chipsets.
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**
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@ -128,20 +128,20 @@ chipset_probe (pcici_t tag, pcidi_t type)
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#define M_EQ 0 /* mask and return true if equal */
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#define M_NE 1 /* mask and return true if not equal */
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#define TRUE 2 /* don't read config, always true */
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#define M_TR 2 /* don't read config, always true */
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static const struct condmsg conf82425ex[] =
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{
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{ 0x00, 0x00, 0x00, TRUE, "\tClock " },
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{ 0x00, 0x00, 0x00, M_TR, "\tClock " },
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{ 0x50, 0x06, 0x00, M_EQ, "25" },
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{ 0x50, 0x06, 0x02, M_EQ, "33" },
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{ 0x50, 0x04, 0x04, M_EQ, "??", },
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{ 0x00, 0x00, 0x00, TRUE, "MHz, L1 Cache " },
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{ 0x00, 0x00, 0x00, M_TR, "MHz, L1 Cache " },
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{ 0x50, 0x01, 0x00, M_EQ, "Disabled\n" },
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{ 0x50, 0x09, 0x01, M_EQ, "Write-through\n" },
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{ 0x50, 0x09, 0x09, M_EQ, "Write-back\n" },
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{ 0x00, 0x00, 0x00, TRUE, "\tL2 Cache " },
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{ 0x00, 0x00, 0x00, M_TR, "\tL2 Cache " },
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{ 0x52, 0x07, 0x00, M_EQ, "Disabled" },
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{ 0x52, 0x0f, 0x01, M_EQ, "64KB Write-through" },
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{ 0x52, 0x0f, 0x02, M_EQ, "128KB Write-through" },
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@ -162,27 +162,27 @@ static const struct condmsg conf82425ex[] =
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{ 0x53, 0x18, 0x10, M_EQ, "/?-?-?-?\n" },
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{ 0x53, 0x18, 0x18, M_EQ, "/2-1-1-1\n" },
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{ 0x56, 0x00, 0x00, TRUE, "\tDRAM: " },
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{ 0x56, 0x00, 0x00, M_TR, "\tDRAM: " },
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{ 0x56, 0x02, 0x02, M_EQ, "Fast Code Read, " },
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{ 0x56, 0x04, 0x04, M_EQ, "Fast Data Read, " },
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{ 0x56, 0x08, 0x08, M_EQ, "Fast Write, " },
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{ 0x57, 0x20, 0x20, M_EQ, "Pipelined CAS" },
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{ 0x57, 0x2e, 0x00, M_NE, "\n\t" },
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{ 0x57, 0x00, 0x00, TRUE, "Timing: RAS: " },
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{ 0x57, 0x00, 0x00, M_TR, "Timing: RAS: " },
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{ 0x57, 0x07, 0x00, M_EQ, "4" },
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{ 0x57, 0x07, 0x01, M_EQ, "3" },
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{ 0x57, 0x07, 0x02, M_EQ, "2" },
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{ 0x57, 0x07, 0x04, M_EQ, "1.5" },
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{ 0x57, 0x07, 0x05, M_EQ, "1" },
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{ 0x57, 0x00, 0x00, TRUE, " Clocks, CAS Read: " },
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{ 0x57, 0x00, 0x00, M_TR, " Clocks, CAS Read: " },
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{ 0x57, 0x18, 0x00, M_EQ, "3/1", },
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{ 0x57, 0x18, 0x00, M_EQ, "2/1", },
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{ 0x57, 0x18, 0x00, M_EQ, "1.5/0.5", },
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{ 0x57, 0x18, 0x00, M_EQ, "1/1", },
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{ 0x57, 0x00, 0x00, TRUE, ", CAS Write: " },
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{ 0x57, 0x00, 0x00, M_TR, ", CAS Write: " },
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{ 0x57, 0x20, 0x00, M_EQ, "2/1", },
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{ 0x57, 0x20, 0x20, M_EQ, "1/1", },
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{ 0x57, 0x00, 0x00, TRUE, "\n" },
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{ 0x57, 0x00, 0x00, M_TR, "\n" },
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{ 0x40, 0x01, 0x01, M_EQ, "\tCPU-to-PCI Byte Merging\n" },
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{ 0x40, 0x02, 0x02, M_EQ, "\tCPU-to-PCI Bursting\n" },
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@ -201,16 +201,16 @@ static const struct condmsg conf82425ex[] =
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static const struct condmsg conf82424zx[] =
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{
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{ 0x00, 0x00, 0x00, TRUE, "\tCPU: " },
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{ 0x00, 0x00, 0x00, M_TR, "\tCPU: " },
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{ 0x50, 0xe0, 0x00, M_EQ, "486DX" },
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{ 0x50, 0xe0, 0x20, M_EQ, "486SX" },
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{ 0x50, 0xe0, 0x40, M_EQ, "486DX2 or 486DX4" },
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{ 0x50, 0xe0, 0x80, M_EQ, "Overdrive (writeback)" },
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{ 0x00, 0x00, 0x00, TRUE, ", bus=" },
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{ 0x00, 0x00, 0x00, M_TR, ", bus=" },
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{ 0x50, 0x03, 0x00, M_EQ, "25MHz" },
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{ 0x50, 0x03, 0x01, M_EQ, "33MHz" },
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{ 0x53, 0x01, 0x01, TRUE, ", CPU->Memory posting "},
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{ 0x53, 0x01, 0x01, M_TR, ", CPU->Memory posting "},
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{ 0x53, 0x01, 0x00, M_EQ, "OFF" },
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{ 0x53, 0x01, 0x01, M_EQ, "ON" },
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@ -219,7 +219,7 @@ static const struct condmsg conf82424zx[] =
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{ 0x56, 0x10, 0x00, M_NE, " NO DRAM parity!" },
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{ 0x55, 0x04, 0x04, M_EQ, "\n\tWarning: refresh OFF! " },
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{ 0x00, 0x00, 0x00, TRUE, "\n\tCache: " },
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{ 0x00, 0x00, 0x00, M_TR, "\n\tCache: " },
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{ 0x52, 0x01, 0x00, M_EQ, "None" },
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{ 0x52, 0xc1, 0x01, M_EQ, "64KB" },
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{ 0x52, 0xc1, 0x41, M_EQ, "128KB" },
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@ -232,7 +232,7 @@ static const struct condmsg conf82424zx[] =
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{ 0x52, 0x05, 0x01, M_EQ, "3-1-1-1" },
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{ 0x52, 0x05, 0x05, M_EQ, "2-1-1-1" },
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{ 0x00, 0x00, 0x00, TRUE, "\n\tDRAM:" },
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{ 0x00, 0x00, 0x00, M_TR, "\n\tDRAM:" },
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{ 0x55, 0x43, 0x00, M_NE, " page mode" },
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{ 0x55, 0x02, 0x02, M_EQ, " code fetch" },
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{ 0x55, 0x43, 0x43, M_EQ, "," },
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@ -243,21 +243,21 @@ static const struct condmsg conf82424zx[] =
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{ 0x55, 0x01, 0x01, M_EQ, " write" },
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{ 0x55, 0x43, 0x00, M_NE, "," },
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{ 0x00, 0x00, 0x00, TRUE, " memory clocks=" },
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{ 0x00, 0x00, 0x00, M_TR, " memory clocks=" },
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{ 0x55, 0x20, 0x00, M_EQ, "X-2-2-2" },
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{ 0x55, 0x20, 0x20, M_EQ, "X-1-2-1" },
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{ 0x00, 0x00, 0x00, TRUE, "\n\tCPU->PCI: posting " },
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{ 0x00, 0x00, 0x00, M_TR, "\n\tCPU->PCI: posting " },
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{ 0x53, 0x02, 0x00, M_NE, "ON" },
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{ 0x53, 0x02, 0x00, M_EQ, "OFF" },
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{ 0x00, 0x00, 0x00, TRUE, ", burst mode " },
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{ 0x00, 0x00, 0x00, M_TR, ", burst mode " },
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{ 0x54, 0x02, 0x00, M_NE, "ON" },
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{ 0x54, 0x02, 0x00, M_EQ, "OFF" },
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{ 0x00, 0x00, 0x00, TRUE, "\n\tPCI->Memory: posting " },
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{ 0x00, 0x00, 0x00, M_TR, "\n\tPCI->Memory: posting " },
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{ 0x54, 0x01, 0x00, M_NE, "ON" },
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{ 0x54, 0x01, 0x00, M_EQ, "OFF" },
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{ 0x00, 0x00, 0x00, TRUE, "\n" },
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{ 0x00, 0x00, 0x00, M_TR, "\n" },
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/* end marker */
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{ 0 }
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@ -265,7 +265,7 @@ static const struct condmsg conf82424zx[] =
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static const struct condmsg conf82434lx[] =
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{
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{ 0x00, 0x00, 0x00, TRUE, "\tCPU: " },
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{ 0x00, 0x00, 0x00, M_TR, "\tCPU: " },
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{ 0x50, 0xe3, 0x82, M_EQ, "Pentium, 60MHz" },
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{ 0x50, 0xe3, 0x83, M_EQ, "Pentium, 66MHz" },
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{ 0x50, 0xe3, 0xa2, M_EQ, "Pentium, 90MHz" },
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@ -273,7 +273,7 @@ static const struct condmsg conf82434lx[] =
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{ 0x50, 0xc2, 0x82, M_NE, "(unknown)" },
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{ 0x50, 0x04, 0x00, M_EQ, " (primary cache OFF)" },
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{ 0x53, 0x01, 0x01, TRUE, ", CPU->Memory posting "},
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{ 0x53, 0x01, 0x01, M_TR, ", CPU->Memory posting "},
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{ 0x53, 0x01, 0x01, M_NE, "OFF" },
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{ 0x53, 0x01, 0x01, M_EQ, "ON" },
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@ -283,7 +283,7 @@ static const struct condmsg conf82434lx[] =
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{ 0x57, 0x20, 0x00, M_NE, "\n\tWarning: DRAM parity mask!" },
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{ 0x57, 0x01, 0x00, M_EQ, "\n\tWarning: refresh OFF! " },
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{ 0x00, 0x00, 0x00, TRUE, "\n\tCache: " },
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{ 0x00, 0x00, 0x00, M_TR, "\n\tCache: " },
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{ 0x52, 0x01, 0x00, M_EQ, "None" },
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{ 0x52, 0x81, 0x01, M_EQ, "" },
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{ 0x52, 0xc1, 0x81, M_EQ, "256KB" },
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@ -300,10 +300,10 @@ static const struct condmsg conf82434lx[] =
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{ 0x52, 0x09, 0x09, M_EQ, " byte-control" },
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{ 0x52, 0x05, 0x05, M_EQ, " powersaver" },
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{ 0x00, 0x00, 0x00, TRUE, "\n\tDRAM:" },
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{ 0x00, 0x00, 0x00, M_TR, "\n\tDRAM:" },
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{ 0x57, 0x10, 0x00, M_EQ, " page mode" },
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{ 0x00, 0x00, 0x00, TRUE, " memory clocks=" },
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{ 0x00, 0x00, 0x00, M_TR, " memory clocks=" },
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{ 0x57, 0xc0, 0x00, M_EQ, "X-4-4-4 (70ns)" },
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{ 0x57, 0xc0, 0x40, M_EQ, "X-4-4-4/X-3-3-3 (60ns)" },
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{ 0x57, 0xc0, 0x80, M_EQ, "???" },
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@ -311,16 +311,16 @@ static const struct condmsg conf82434lx[] =
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{ 0x58, 0x02, 0x02, M_EQ, ", RAS-wait" },
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{ 0x58, 0x01, 0x01, M_EQ, ", CAS-wait" },
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{ 0x00, 0x00, 0x00, TRUE, "\n\tCPU->PCI: posting " },
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{ 0x00, 0x00, 0x00, M_TR, "\n\tCPU->PCI: posting " },
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{ 0x53, 0x02, 0x02, M_EQ, "ON" },
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{ 0x53, 0x02, 0x00, M_EQ, "OFF" },
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{ 0x00, 0x00, 0x00, TRUE, ", burst mode " },
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{ 0x00, 0x00, 0x00, M_TR, ", burst mode " },
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{ 0x54, 0x02, 0x00, M_NE, "ON" },
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{ 0x54, 0x02, 0x00, M_EQ, "OFF" },
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{ 0x54, 0x04, 0x00, TRUE, ", PCI clocks=" },
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{ 0x54, 0x04, 0x00, M_TR, ", PCI clocks=" },
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{ 0x54, 0x04, 0x00, M_EQ, "2-2-2-2" },
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{ 0x54, 0x04, 0x00, M_NE, "2-1-1-1" },
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{ 0x00, 0x00, 0x00, TRUE, "\n\tPCI->Memory: posting " },
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{ 0x00, 0x00, 0x00, M_TR, "\n\tPCI->Memory: posting " },
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{ 0x54, 0x01, 0x00, M_NE, "ON" },
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{ 0x54, 0x01, 0x00, M_EQ, "OFF" },
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@ -329,7 +329,7 @@ static const struct condmsg conf82434lx[] =
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{ 0x57, 0x03, 0x01, M_EQ, " RAS#Only" },
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{ 0x57, 0x05, 0x05, M_EQ, " BurstOf4" },
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{ 0x00, 0x00, 0x00, TRUE, "\n" },
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{ 0x00, 0x00, 0x00, M_TR, "\n" },
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/* end marker */
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{ 0 }
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@ -337,7 +337,7 @@ static const struct condmsg conf82434lx[] =
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static const struct condmsg conf82378[] =
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{
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{ 0x00, 0x00, 0x00, TRUE, "\tBus Modes:" },
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{ 0x00, 0x00, 0x00, M_TR, "\tBus Modes:" },
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{ 0x41, 0x04, 0x04, M_EQ, " Bus Park," },
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{ 0x41, 0x02, 0x02, M_EQ, " Bus Lock," },
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{ 0x41, 0x02, 0x00, M_EQ, " Resource Lock," },
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@ -363,7 +363,7 @@ static const struct condmsg conf82378[] =
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{ 0x4f, 0x30, 0x00, M_EQ, "\n\tParallel Port: LPT1 (3BCh-3BFh)" },
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{ 0x4f, 0x30, 0x04, M_EQ, "\n\tParallel Port: LPT2 (378h-37Fh)" },
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{ 0x4f, 0x30, 0x20, M_EQ, "\n\tParallel Port: LPT3 (278h-27Fh)" },
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{ 0x00, 0x00, 0x00, TRUE, "\n" },
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{ 0x00, 0x00, 0x00, M_TR, "\n" },
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/* end marker */
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{ 0 }
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@ -383,7 +383,7 @@ writeconfig (pcici_t config_id, const struct condmsg *tbl)
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{
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while (tbl->text) {
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int cond = 0;
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if (tbl->flags == TRUE) {
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if (tbl->flags == M_TR) {
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cond = 1;
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} else {
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unsigned char v = (unsigned char) confread(config_id, tbl->port);
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