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synced 2025-01-01 00:18:15 +01:00
Work around Cheetah+ erratum 34 (USIII+ erratum #10) by relocating
the locked entry in it16 slot 0, which typically is occupied by the PROM, and manually entering locked entries in slots != 0. Thanks to Hubert Feyrer for donating the Blade 2000 this change was developed on.
This commit is contained in:
Marius Strobl
parent
9de45b2780
commit
d8f4dd34d6
@ -6,6 +6,31 @@
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* As long as the above copyright statement and this notice remain
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* unchanged, you can do what ever you want with this file.
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*/
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/*-
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* Copyright (c) 2008 Marius Strobl <marius@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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@ -65,6 +90,7 @@ static vm_offset_t dtlb_va_to_pa_sun4u(vm_offset_t);
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static inline u_long itlb_get_data_sun4u(int slot);
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static void itlb_enter_sun4u(u_long vpn, u_long data);
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static vm_offset_t itlb_va_to_pa_sun4u(vm_offset_t);
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static void itlb_relocate_locked0_sun4u(void);
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extern vm_offset_t md_load(char *, vm_offset_t *);
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static int sparc64_autoload(void);
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static ssize_t sparc64_readin(const int, vm_offset_t, const size_t);
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@ -456,9 +482,32 @@ static void
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itlb_enter_sun4u(u_long vpn, u_long data)
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{
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u_long reg;
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int i;
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reg = rdpr(pstate);
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wrpr(pstate, reg & ~PSTATE_IE, 0);
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if (cpu_impl == CPU_IMPL_ULTRASPARCIIIp) {
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/*
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* Search an unused slot != 0 and explicitly enter the data
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* and tag there in order to avoid Cheetah+ erratum 34.
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*/
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for (i = 1; i < itlb_slot_max; i++) {
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if ((itlb_get_data_sun4u(i) & TD_V) != 0)
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continue;
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stxa(AA_IMMU_TAR, ASI_IMMU,
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TLB_TAR_VA(vpn) | TLB_TAR_CTX(TLB_CTX_KERNEL));
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stxa(TLB_DAR_SLOT(i), ASI_ITLB_DATA_ACCESS_REG, data);
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flush(KERNBASE);
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break;
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}
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wrpr(pstate, reg, 0);
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if (i == itlb_slot_max)
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panic("%s: could not find an unused slot", __func__);
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return;
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}
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stxa(AA_IMMU_TAR, ASI_IMMU,
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TLB_TAR_VA(vpn) | TLB_TAR_CTX(TLB_CTX_KERNEL));
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stxa(0, ASI_ITLB_DATA_IN_REG, data);
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@ -466,6 +515,48 @@ itlb_enter_sun4u(u_long vpn, u_long data)
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wrpr(pstate, reg, 0);
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}
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static void
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itlb_relocate_locked0_sun4u(void)
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{
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u_long data, pstate, tag;
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int i;
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if (cpu_impl != CPU_IMPL_ULTRASPARCIIIp)
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return;
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pstate = rdpr(pstate);
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wrpr(pstate, pstate & ~PSTATE_IE, 0);
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data = itlb_get_data_sun4u(0);
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if ((data & (TD_V | TD_L)) != (TD_V | TD_L)) {
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wrpr(pstate, pstate, 0);
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return;
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}
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/* Flush the mapping of slot 0. */
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tag = ldxa(TLB_DAR_SLOT(0), ASI_ITLB_TAG_READ_REG);
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stxa(TLB_DEMAP_VA(TLB_TAR_VA(tag)) | TLB_DEMAP_PRIMARY |
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TLB_DEMAP_PAGE, ASI_IMMU_DEMAP, 0);
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flush(0); /* The USIII-family ignores the address. */
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/*
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* Search a replacement slot != 0 and enter the data and tag
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* that formerly were in slot 0.
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*/
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for (i = 1; i < itlb_slot_max; i++) {
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if ((itlb_get_data_sun4u(i) & TD_V) != 0)
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continue;
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stxa(AA_IMMU_TAR, ASI_IMMU, tag);
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stxa(TLB_DAR_SLOT(i), ASI_ITLB_DATA_ACCESS_REG, data);
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flush(0); /* The USIII-family ignores the address. */
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break;
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}
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wrpr(pstate, pstate, 0);
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if (i == itlb_slot_max)
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panic("%s: could not find a replacement slot", __func__);
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}
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static int
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mmu_mapin_sun4u(vm_offset_t va, vm_size_t len)
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{
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@ -603,6 +694,25 @@ tlb_init_sun4u(void)
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OF_getprop(child, "#itlb-entries", &itlb_slot_max,
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sizeof(itlb_slot_max)) == -1)
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panic("%s: can't get TLB slot max.", __func__);
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if (cpu_impl == CPU_IMPL_ULTRASPARCIIIp) {
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#ifdef LOADER_DEBUG
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printf("pre fixup:\n");
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pmap_print_tlb_sun4u();
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#endif
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/*
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* Relocate the locked entry in it16 slot 0 (if existent)
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* as part of working around Cheetah+ erratum 34.
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*/
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itlb_relocate_locked0_sun4u();
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#ifdef LOADER_DEBUG
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printf("post fixup:\n");
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pmap_print_tlb_sun4u();
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#endif
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}
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dtlb_store = malloc(dtlb_slot_max * sizeof(*dtlb_store));
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itlb_store = malloc(itlb_slot_max * sizeof(*itlb_store));
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if (dtlb_store == NULL || itlb_store == NULL)
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@ -123,15 +123,18 @@ ASSYM(TTE_SHIFT, TTE_SHIFT);
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ASSYM(TTE_VPN, offsetof(struct tte, tte_vpn));
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ASSYM(TTE_DATA, offsetof(struct tte, tte_data));
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ASSYM(TD_V, TD_V);
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ASSYM(TD_EXEC, TD_EXEC);
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ASSYM(TD_REF, TD_REF);
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ASSYM(TD_SW, TD_SW);
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ASSYM(TD_L, TD_L);
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ASSYM(TD_CP, TD_CP);
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ASSYM(TD_CV, TD_CV);
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ASSYM(TD_W, TD_W);
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ASSYM(TS_MIN, TS_MIN);
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ASSYM(TS_MAX, TS_MAX);
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ASSYM(TLB_DAR_SLOT_SHIFT, TLB_DAR_SLOT_SHIFT);
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ASSYM(TLB_PCXR_PGSZ_MASK, TLB_PCXR_PGSZ_MASK);
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ASSYM(TLB_DIRECT_TO_TTE_MASK, TLB_DIRECT_TO_TTE_MASK);
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ASSYM(TV_SIZE_BITS, TV_SIZE_BITS);
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@ -1,5 +1,6 @@
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/*-
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* Copyright (c) 2002 Jake Burkholder.
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* Copyright (c) 2008 Marius Strobl <marius@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -42,12 +43,78 @@ __FBSDID("$FreeBSD$");
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.text
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_ALIGN_TEXT
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1: rd %pc, %l0
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ldx [%l0 + (4f-1b)], %l1
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add %l0, (6f-1b), %l2
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/*
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* Initialize misc. state to known values: interrupts disabled,
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* normal globals, no clean windows, PIL 0, and floating point
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* disabled.
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*/
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1: wrpr %g0, PSTATE_NORMAL, %pstate
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wrpr %g0, 0, %cleanwin
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wrpr %g0, 0, %pil
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wr %g0, 0, %fprs
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rdpr %ver, %l7
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srlx %l7, VER_IMPL_SHIFT, %l7
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sll %l7, VER_IMPL_SIZE, %l7
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srl %l7, VER_IMPL_SIZE, %l7
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cmp %l7, CPU_IMPL_ULTRASPARCIIIp
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bne %icc, 3f
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nop
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/*
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* Relocate the locked entry in it16 slot 0 (if existent)
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* as part of working around Cheetah+ erratum 34.
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*/
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setx TD_V | TD_L, %l1, %l0
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/*
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* We read ASI_DTLB_DATA_ACCESS_REG twice in order to work
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* around errata of USIII and beyond.
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*/
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ldxa [%g0] ASI_ITLB_DATA_ACCESS_REG, %g0
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ldxa [%g0] ASI_ITLB_DATA_ACCESS_REG, %l6
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and %l6, %l0, %l1
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cmp %l0, %l1
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bne %xcc, 3f
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nop
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/* Flush the mapping of slot 0. */
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ldxa [%g0] ASI_ITLB_TAG_READ_REG, %l5
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srlx %l5, TAR_VPN_SHIFT, %l0
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sllx %l0, TAR_VPN_SHIFT, %l0
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or %l0, TLB_DEMAP_PRIMARY | TLB_DEMAP_PAGE, %l0
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stxa %g0, [%l0] ASI_IMMU_DEMAP
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/* The USIII-family ignores the address. */
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flush %g0
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/*
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* Search a replacement slot != 0 and enter the data and tag
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* that formerly were in slot 0.
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*/
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mov (1 << TLB_DAR_SLOT_SHIFT), %l4
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setx TD_V, %l1, %l0
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/*
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* We read ASI_DTLB_DATA_ACCESS_REG twice in order to work
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* around errata of USIII and beyond.
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*/
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2: ldxa [%l4] ASI_ITLB_DATA_ACCESS_REG, %g0
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ldxa [%l4] ASI_ITLB_DATA_ACCESS_REG, %l1
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and %l1, %l0, %l1
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cmp %l0, %l1
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be,a %xcc, 2b
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add %l4, (1 << TLB_DAR_SLOT_SHIFT), %l4
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wr %g0, ASI_IMMU, %asi
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stxa %l5, [%g0 + AA_IMMU_TAR] %asi
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stxa %l6, [%l4] ASI_ITLB_DATA_ACCESS_REG
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/* The USIII-family ignores the address. */
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flush %g0
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3: rd %pc, %l6
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ldx [%l6 + (9f-3b)], %l1
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add %l6, (11f-3b), %l2
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clr %l3
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2: cmp %l3, %l1
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be %xcc, 3f
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4: cmp %l3, %l1
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be %xcc, 8f
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nop
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ldx [%l2 + TTE_VPN], %l4
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ldx [%l2 + TTE_DATA], %l5
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@ -56,41 +123,64 @@ __FBSDID("$FreeBSD$");
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wr %g0, ASI_DMMU, %asi
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stxa %l4, [%g0 + AA_DMMU_TAR] %asi
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stxa %l5, [%g0] ASI_DTLB_DATA_IN_REG
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wr %g0, ASI_IMMU, %asi
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membar #Sync
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cmp %l7, CPU_IMPL_ULTRASPARCIIIp
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bne %icc, 6f
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wr %g0, ASI_IMMU, %asi
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/*
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* Search an unused slot != 0 and explicitly enter the data
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* and tag there in order to avoid Cheetah+ erratum 34.
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*/
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mov (1 << TLB_DAR_SLOT_SHIFT), %l0
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setx TD_V, %o1, %o0
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/*
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* We read ASI_DTLB_DATA_ACCESS_REG twice in order to work
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* around errata of USIII and beyond.
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*/
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5: ldxa [%l0] ASI_ITLB_DATA_ACCESS_REG, %g0
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ldxa [%l0] ASI_ITLB_DATA_ACCESS_REG, %o1
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and %o1, %o0, %o1
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cmp %o0, %o1
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be,a %xcc, 5b
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add %l0, (1 << TLB_DAR_SLOT_SHIFT), %l0
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sethi %hi(KERNBASE), %o0
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stxa %l4, [%g0 + AA_IMMU_TAR] %asi
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stxa %l5, [%l0] ASI_ITLB_DATA_ACCESS_REG
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flush %o0
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ba %xcc, 7f
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nop
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6: sethi %hi(KERNBASE), %l0
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stxa %l4, [%g0 + AA_IMMU_TAR] %asi
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stxa %l5, [%g0] ASI_ITLB_DATA_IN_REG
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membar #Sync
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flush %l4
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add %l2, 1 << TTE_SHIFT, %l2
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flush %l0
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7: add %l2, 1 << TTE_SHIFT, %l2
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add %l3, 1, %l3
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ba %xcc, 2b
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ba %xcc, 4b
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nop
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3: ldx [%l0 + (5f-1b)], %l1
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8: ldx [%l6 + (10f-3b)], %l1
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jmpl %l1, %g0
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nop
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_ALIGN_DATA
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4: .xword 0x0
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5: .xword 0x0
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6:
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9: .xword 0x0
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10: .xword 0x0
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11:
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DATA(mp_tramp_code)
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.xword 1b
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DATA(mp_tramp_code_len)
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.xword 6b-1b
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.xword 11b-1b
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DATA(mp_tramp_tlb_slots)
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.xword 4b-1b
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.xword 9b-1b
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DATA(mp_tramp_func)
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.xword 5b-1b
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.xword 10b-1b
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/*
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* void mp_startup(void)
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*/
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ENTRY(mp_startup)
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wrpr %g0, PSTATE_NORMAL, %pstate
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wrpr %g0, 0, %cleanwin
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wrpr %g0, 0, %pil
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wr %g0, 0, %fprs
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SET(cpu_start_args, %l1, %l0)
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mov CPU_TICKSYNC, %l1
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@ -162,6 +162,7 @@
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#define ASI_ITLB_DATA_IN_REG 0x54
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#define ASI_ITLB_DATA_ACCESS_REG 0x55
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#define ASI_ITLB_TAG_READ_REG 0x56
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#define ASI_IMMU_DEMAP 0x57
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#define ASI_DMMU 0x58
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#define ASI_DTLB_DATA_IN_REG 0x5c
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#define ASI_DTLB_DATA_ACCESS_REG 0x5d
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