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Made "AUTO_EOI_1" standard. auto-EOI on the master ICU is a documented

Browse Source 
feature of the ICU. auto-EOI on the slave is not safe, however, so it
remains an option. Killed religious FASTER_NOP when writing the ICU.

Reviewed by:	bde
This commit is contained in:
David Greenman 1995-12-23 16:53:57 +00:00
parent 44198d45b6
commit e8636c6c19
5 changed files with 119 additions and 171 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
sys/amd64/isa/isa.c
View File

@ -34,7 +34,7 @@
* SUCH DAMAGE. * SUCH DAMAGE.
* *
* from: @(#)isa.c 7.2 (Berkeley) 5/13/91 * from: @(#)isa.c 7.2 (Berkeley) 5/13/91
* $Id: isa.c,v 1.58 1995/12/07 12:46:01 davidg Exp $ * $Id: isa.c,v 1.59 1995/12/19 14:30:48 davidg Exp $
*/ */
/* /*
@ -560,11 +560,7 @@ isa_defaultirq()
outb(IO_ICU1, 0x11); /* reset; program device, four bytes */ outb(IO_ICU1, 0x11); /* reset; program device, four bytes */
outb(IO_ICU1+1, NRSVIDT); /* starting at this vector index */ outb(IO_ICU1+1, NRSVIDT); /* starting at this vector index */
outb(IO_ICU1+1, 1<<2); /* slave on line 2 */ outb(IO_ICU1+1, 1<<2); /* slave on line 2 */
#ifdef AUTO_EOI_1 outb(IO_ICU1+1, 2 | 1); /* (master) auto EOI, 8086 mode */
outb(IO_ICU1+1, 2 | 1); /* auto EOI, 8086 mode */
#else
outb(IO_ICU1+1, 1); /* 8086 mode */
#endif
outb(IO_ICU1+1, 0xff); /* leave interrupts masked */ outb(IO_ICU1+1, 0xff); /* leave interrupts masked */
outb(IO_ICU1, 0x0a); /* default to IRR on read */ outb(IO_ICU1, 0x0a); /* default to IRR on read */
outb(IO_ICU1, 0xc0 | (3 - 1)); /* pri order 3-7, 0-2 (com2 first) */ outb(IO_ICU1, 0xc0 | (3 - 1)); /* pri order 3-7, 0-2 (com2 first) */
@ -813,6 +809,8 @@ isa_strayintr(d)
* testing that the in-service bit is _not_ set. The test * testing that the in-service bit is _not_ set. The test
* must be done before sending an EOI so it can't be done if * must be done before sending an EOI so it can't be done if
* we are using AUTO_EOI_1. * we are using AUTO_EOI_1.
*
* XXX AUTO_EOI_1 is now standard.
*/ */
if (intrcnt[NR_DEVICES + d] <= 5) if (intrcnt[NR_DEVICES + d] <= 5)
log(LOG_ERR, "stray irq %d\n", d); log(LOG_ERR, "stray irq %d\n", d);

90
sys/amd64/isa/vector.S
View File

@ -1,6 +1,6 @@
/* /*
* from: vector.s, 386BSD 0.1 unknown origin * from: vector.s, 386BSD 0.1 unknown origin
* $Id: vector.s,v 1.13 1995/10/28 16:58:05 markm Exp $ * $Id: vector.s,v 1.14 1995/11/04 16:00:56 markm Exp $
*/ */
#include <i386/isa/icu.h> #include <i386/isa/icu.h>
@ -11,29 +11,15 @@
#define IRQ_BIT(irq_num) (1 << ((irq_num) % 8)) #define IRQ_BIT(irq_num) (1 << ((irq_num) % 8))
#define IRQ_BYTE(irq_num) ((irq_num) / 8) #define IRQ_BYTE(irq_num) ((irq_num) / 8)
#ifdef AUTO_EOI_1
#define ENABLE_ICU1 /* use auto-EOI to reduce i/o */
#define OUTB_ICU1
#else
#define ENABLE_ICU1 \
movb $ICU_EOI,%al ; /* as soon as possible send EOI ... */ \
OUTB_ICU1 /* ... to clear in service bit */
#define OUTB_ICU1 \
FASTER_NOP ; \
outb %al,$IO_ICU1
#endif
#ifdef AUTO_EOI_2 #ifdef AUTO_EOI_2
/* /*
* The data sheet says no auto-EOI on slave, but it sometimes works. * The data sheet says no auto-EOI on slave, but it sometimes works.
*/ */
#define ENABLE_ICU1_AND_2 ENABLE_ICU1 #define ENABLE_ICU2
#else #else
#define ENABLE_ICU1_AND_2 \ #define ENABLE_ICU2 \
movb $ICU_EOI,%al ; /* as above */ \ movb $ICU_EOI,%al ; \
FASTER_NOP ; \ outb %al,$IO_ICU2 ;
outb %al,$IO_ICU2 ; /* but do second icu first ... */ \
OUTB_ICU1 /* ... then first icu (if !AUTO_EOI_1) */
#endif #endif
#ifdef FAST_INTR_HANDLER_USES_ES #ifdef FAST_INTR_HANDLER_USES_ES
@ -174,7 +160,6 @@ IDTVEC(intr/**/irq_num) ; \
movb _imen + IRQ_BYTE(irq_num),%al ; \ movb _imen + IRQ_BYTE(irq_num),%al ; \
orb $IRQ_BIT(irq_num),%al ; \ orb $IRQ_BIT(irq_num),%al ; \
movb %al,_imen + IRQ_BYTE(irq_num) ; \ movb %al,_imen + IRQ_BYTE(irq_num) ; \
FASTER_NOP ; \
outb %al,$icu+1 ; \ outb %al,$icu+1 ; \
enable_icus ; \ enable_icus ; \
incl _cnt+V_INTR ; /* tally interrupts */ \ incl _cnt+V_INTR ; /* tally interrupts */ \
@ -197,7 +182,6 @@ Xresume/**/irq_num: ; \
movb _imen + IRQ_BYTE(irq_num),%al ; \ movb _imen + IRQ_BYTE(irq_num),%al ; \
andb $~IRQ_BIT(irq_num),%al ; \ andb $~IRQ_BIT(irq_num),%al ; \
movb %al,_imen + IRQ_BYTE(irq_num) ; \ movb %al,_imen + IRQ_BYTE(irq_num) ; \
FASTER_NOP ; \
outb %al,$icu+1 ; \ outb %al,$icu+1 ; \
sti ; /* XXX _doreti repeats the cli/sti */ \ sti ; /* XXX _doreti repeats the cli/sti */ \
/* Add this interrupt to the pool of entropy */ \ /* Add this interrupt to the pool of entropy */ \
@ -218,38 +202,38 @@ Xresume/**/irq_num: ; \
iret iret
MCOUNT_LABEL(bintr) MCOUNT_LABEL(bintr)
FAST_INTR(0, ENABLE_ICU1) FAST_INTR(0,)
FAST_INTR(1, ENABLE_ICU1) FAST_INTR(1,)
FAST_INTR(2, ENABLE_ICU1) FAST_INTR(2,)
FAST_INTR(3, ENABLE_ICU1) FAST_INTR(3,)
FAST_INTR(4, ENABLE_ICU1) FAST_INTR(4,)
FAST_INTR(5, ENABLE_ICU1) FAST_INTR(5,)
FAST_INTR(6, ENABLE_ICU1) FAST_INTR(6,)
FAST_INTR(7, ENABLE_ICU1) FAST_INTR(7,)
FAST_INTR(8, ENABLE_ICU1_AND_2) FAST_INTR(8, ENABLE_ICU2)
FAST_INTR(9, ENABLE_ICU1_AND_2) FAST_INTR(9, ENABLE_ICU2)
FAST_INTR(10, ENABLE_ICU1_AND_2) FAST_INTR(10, ENABLE_ICU2)
FAST_INTR(11, ENABLE_ICU1_AND_2) FAST_INTR(11, ENABLE_ICU2)
FAST_INTR(12, ENABLE_ICU1_AND_2) FAST_INTR(12, ENABLE_ICU2)
FAST_INTR(13, ENABLE_ICU1_AND_2) FAST_INTR(13, ENABLE_ICU2)
FAST_INTR(14, ENABLE_ICU1_AND_2) FAST_INTR(14, ENABLE_ICU2)
FAST_INTR(15, ENABLE_ICU1_AND_2) FAST_INTR(15, ENABLE_ICU2)
INTR(0, IO_ICU1, ENABLE_ICU1, al) INTR(0, IO_ICU1,, al)
INTR(1, IO_ICU1, ENABLE_ICU1, al) INTR(1, IO_ICU1,, al)
INTR(2, IO_ICU1, ENABLE_ICU1, al) INTR(2, IO_ICU1,, al)
INTR(3, IO_ICU1, ENABLE_ICU1, al) INTR(3, IO_ICU1,, al)
INTR(4, IO_ICU1, ENABLE_ICU1, al) INTR(4, IO_ICU1,, al)
INTR(5, IO_ICU1, ENABLE_ICU1, al) INTR(5, IO_ICU1,, al)
INTR(6, IO_ICU1, ENABLE_ICU1, al) INTR(6, IO_ICU1,, al)
INTR(7, IO_ICU1, ENABLE_ICU1, al) INTR(7, IO_ICU1,, al)
INTR(8, IO_ICU2, ENABLE_ICU1_AND_2, ah) INTR(8, IO_ICU2, ENABLE_ICU2, ah)
INTR(9, IO_ICU2, ENABLE_ICU1_AND_2, ah) INTR(9, IO_ICU2, ENABLE_ICU2, ah)
INTR(10, IO_ICU2, ENABLE_ICU1_AND_2, ah) INTR(10, IO_ICU2, ENABLE_ICU2, ah)
INTR(11, IO_ICU2, ENABLE_ICU1_AND_2, ah) INTR(11, IO_ICU2, ENABLE_ICU2, ah)
INTR(12, IO_ICU2, ENABLE_ICU1_AND_2, ah) INTR(12, IO_ICU2, ENABLE_ICU2, ah)
INTR(13, IO_ICU2, ENABLE_ICU1_AND_2, ah) INTR(13, IO_ICU2, ENABLE_ICU2, ah)
INTR(14, IO_ICU2, ENABLE_ICU1_AND_2, ah) INTR(14, IO_ICU2, ENABLE_ICU2, ah)
INTR(15, IO_ICU2, ENABLE_ICU1_AND_2, ah) INTR(15, IO_ICU2, ENABLE_ICU2, ah)
MCOUNT_LABEL(eintr) MCOUNT_LABEL(eintr)
.data .data

90
sys/amd64/isa/vector.s
View File

@ -1,6 +1,6 @@
/* /*
* from: vector.s, 386BSD 0.1 unknown origin * from: vector.s, 386BSD 0.1 unknown origin
* $Id: vector.s,v 1.13 1995/10/28 16:58:05 markm Exp $ * $Id: vector.s,v 1.14 1995/11/04 16:00:56 markm Exp $
*/ */
#include <i386/isa/icu.h> #include <i386/isa/icu.h>
@ -11,29 +11,15 @@
#define IRQ_BIT(irq_num) (1 << ((irq_num) % 8)) #define IRQ_BIT(irq_num) (1 << ((irq_num) % 8))
#define IRQ_BYTE(irq_num) ((irq_num) / 8) #define IRQ_BYTE(irq_num) ((irq_num) / 8)
#ifdef AUTO_EOI_1
#define ENABLE_ICU1 /* use auto-EOI to reduce i/o */
#define OUTB_ICU1
#else
#define ENABLE_ICU1 \
movb $ICU_EOI,%al ; /* as soon as possible send EOI ... */ \
OUTB_ICU1 /* ... to clear in service bit */
#define OUTB_ICU1 \
FASTER_NOP ; \
outb %al,$IO_ICU1
#endif
#ifdef AUTO_EOI_2 #ifdef AUTO_EOI_2
/* /*
* The data sheet says no auto-EOI on slave, but it sometimes works. * The data sheet says no auto-EOI on slave, but it sometimes works.
*/ */
#define ENABLE_ICU1_AND_2 ENABLE_ICU1 #define ENABLE_ICU2
#else #else
#define ENABLE_ICU1_AND_2 \ #define ENABLE_ICU2 \
movb $ICU_EOI,%al ; /* as above */ \ movb $ICU_EOI,%al ; \
FASTER_NOP ; \ outb %al,$IO_ICU2 ;
outb %al,$IO_ICU2 ; /* but do second icu first ... */ \
OUTB_ICU1 /* ... then first icu (if !AUTO_EOI_1) */
#endif #endif
#ifdef FAST_INTR_HANDLER_USES_ES #ifdef FAST_INTR_HANDLER_USES_ES
@ -174,7 +160,6 @@ IDTVEC(intr/**/irq_num) ; \
movb _imen + IRQ_BYTE(irq_num),%al ; \ movb _imen + IRQ_BYTE(irq_num),%al ; \
orb $IRQ_BIT(irq_num),%al ; \ orb $IRQ_BIT(irq_num),%al ; \
movb %al,_imen + IRQ_BYTE(irq_num) ; \ movb %al,_imen + IRQ_BYTE(irq_num) ; \
FASTER_NOP ; \
outb %al,$icu+1 ; \ outb %al,$icu+1 ; \
enable_icus ; \ enable_icus ; \
incl _cnt+V_INTR ; /* tally interrupts */ \ incl _cnt+V_INTR ; /* tally interrupts */ \
@ -197,7 +182,6 @@ Xresume/**/irq_num: ; \
movb _imen + IRQ_BYTE(irq_num),%al ; \ movb _imen + IRQ_BYTE(irq_num),%al ; \
andb $~IRQ_BIT(irq_num),%al ; \ andb $~IRQ_BIT(irq_num),%al ; \
movb %al,_imen + IRQ_BYTE(irq_num) ; \ movb %al,_imen + IRQ_BYTE(irq_num) ; \
FASTER_NOP ; \
outb %al,$icu+1 ; \ outb %al,$icu+1 ; \
sti ; /* XXX _doreti repeats the cli/sti */ \ sti ; /* XXX _doreti repeats the cli/sti */ \
/* Add this interrupt to the pool of entropy */ \ /* Add this interrupt to the pool of entropy */ \
@ -218,38 +202,38 @@ Xresume/**/irq_num: ; \
iret iret
MCOUNT_LABEL(bintr) MCOUNT_LABEL(bintr)
FAST_INTR(0, ENABLE_ICU1) FAST_INTR(0,)
FAST_INTR(1, ENABLE_ICU1) FAST_INTR(1,)
FAST_INTR(2, ENABLE_ICU1) FAST_INTR(2,)
FAST_INTR(3, ENABLE_ICU1) FAST_INTR(3,)
FAST_INTR(4, ENABLE_ICU1) FAST_INTR(4,)
FAST_INTR(5, ENABLE_ICU1) FAST_INTR(5,)
FAST_INTR(6, ENABLE_ICU1) FAST_INTR(6,)
FAST_INTR(7, ENABLE_ICU1) FAST_INTR(7,)
FAST_INTR(8, ENABLE_ICU1_AND_2) FAST_INTR(8, ENABLE_ICU2)
FAST_INTR(9, ENABLE_ICU1_AND_2) FAST_INTR(9, ENABLE_ICU2)
FAST_INTR(10, ENABLE_ICU1_AND_2) FAST_INTR(10, ENABLE_ICU2)
FAST_INTR(11, ENABLE_ICU1_AND_2) FAST_INTR(11, ENABLE_ICU2)
FAST_INTR(12, ENABLE_ICU1_AND_2) FAST_INTR(12, ENABLE_ICU2)
FAST_INTR(13, ENABLE_ICU1_AND_2) FAST_INTR(13, ENABLE_ICU2)
FAST_INTR(14, ENABLE_ICU1_AND_2) FAST_INTR(14, ENABLE_ICU2)
FAST_INTR(15, ENABLE_ICU1_AND_2) FAST_INTR(15, ENABLE_ICU2)
INTR(0, IO_ICU1, ENABLE_ICU1, al) INTR(0, IO_ICU1,, al)
INTR(1, IO_ICU1, ENABLE_ICU1, al) INTR(1, IO_ICU1,, al)
INTR(2, IO_ICU1, ENABLE_ICU1, al) INTR(2, IO_ICU1,, al)
INTR(3, IO_ICU1, ENABLE_ICU1, al) INTR(3, IO_ICU1,, al)
INTR(4, IO_ICU1, ENABLE_ICU1, al) INTR(4, IO_ICU1,, al)
INTR(5, IO_ICU1, ENABLE_ICU1, al) INTR(5, IO_ICU1,, al)
INTR(6, IO_ICU1, ENABLE_ICU1, al) INTR(6, IO_ICU1,, al)
INTR(7, IO_ICU1, ENABLE_ICU1, al) INTR(7, IO_ICU1,, al)
INTR(8, IO_ICU2, ENABLE_ICU1_AND_2, ah) INTR(8, IO_ICU2, ENABLE_ICU2, ah)
INTR(9, IO_ICU2, ENABLE_ICU1_AND_2, ah) INTR(9, IO_ICU2, ENABLE_ICU2, ah)
INTR(10, IO_ICU2, ENABLE_ICU1_AND_2, ah) INTR(10, IO_ICU2, ENABLE_ICU2, ah)
INTR(11, IO_ICU2, ENABLE_ICU1_AND_2, ah) INTR(11, IO_ICU2, ENABLE_ICU2, ah)
INTR(12, IO_ICU2, ENABLE_ICU1_AND_2, ah) INTR(12, IO_ICU2, ENABLE_ICU2, ah)
INTR(13, IO_ICU2, ENABLE_ICU1_AND_2, ah) INTR(13, IO_ICU2, ENABLE_ICU2, ah)
INTR(14, IO_ICU2, ENABLE_ICU1_AND_2, ah) INTR(14, IO_ICU2, ENABLE_ICU2, ah)
INTR(15, IO_ICU2, ENABLE_ICU1_AND_2, ah) INTR(15, IO_ICU2, ENABLE_ICU2, ah)
MCOUNT_LABEL(eintr) MCOUNT_LABEL(eintr)
.data .data

10
sys/i386/isa/isa.c
View File

@ -34,7 +34,7 @@
* SUCH DAMAGE. * SUCH DAMAGE.
* *
* from: @(#)isa.c 7.2 (Berkeley) 5/13/91 * from: @(#)isa.c 7.2 (Berkeley) 5/13/91
* $Id: isa.c,v 1.58 1995/12/07 12:46:01 davidg Exp $ * $Id: isa.c,v 1.59 1995/12/19 14:30:48 davidg Exp $
*/ */
/* /*
@ -560,11 +560,7 @@ isa_defaultirq()
outb(IO_ICU1, 0x11); /* reset; program device, four bytes */ outb(IO_ICU1, 0x11); /* reset; program device, four bytes */
outb(IO_ICU1+1, NRSVIDT); /* starting at this vector index */ outb(IO_ICU1+1, NRSVIDT); /* starting at this vector index */
outb(IO_ICU1+1, 1<<2); /* slave on line 2 */ outb(IO_ICU1+1, 1<<2); /* slave on line 2 */
#ifdef AUTO_EOI_1 outb(IO_ICU1+1, 2 | 1); /* (master) auto EOI, 8086 mode */
outb(IO_ICU1+1, 2 | 1); /* auto EOI, 8086 mode */
#else
outb(IO_ICU1+1, 1); /* 8086 mode */
#endif
outb(IO_ICU1+1, 0xff); /* leave interrupts masked */ outb(IO_ICU1+1, 0xff); /* leave interrupts masked */
outb(IO_ICU1, 0x0a); /* default to IRR on read */ outb(IO_ICU1, 0x0a); /* default to IRR on read */
outb(IO_ICU1, 0xc0 | (3 - 1)); /* pri order 3-7, 0-2 (com2 first) */ outb(IO_ICU1, 0xc0 | (3 - 1)); /* pri order 3-7, 0-2 (com2 first) */
@ -813,6 +809,8 @@ isa_strayintr(d)
* testing that the in-service bit is _not_ set. The test * testing that the in-service bit is _not_ set. The test
* must be done before sending an EOI so it can't be done if * must be done before sending an EOI so it can't be done if
* we are using AUTO_EOI_1. * we are using AUTO_EOI_1.
*
* XXX AUTO_EOI_1 is now standard.
*/ */
if (intrcnt[NR_DEVICES + d] <= 5) if (intrcnt[NR_DEVICES + d] <= 5)
log(LOG_ERR, "stray irq %d\n", d); log(LOG_ERR, "stray irq %d\n", d);

90
sys/i386/isa/vector.s
View File

@ -1,6 +1,6 @@
/* /*
* from: vector.s, 386BSD 0.1 unknown origin * from: vector.s, 386BSD 0.1 unknown origin
* $Id: vector.s,v 1.13 1995/10/28 16:58:05 markm Exp $ * $Id: vector.s,v 1.14 1995/11/04 16:00:56 markm Exp $
*/ */
#include <i386/isa/icu.h> #include <i386/isa/icu.h>
@ -11,29 +11,15 @@
#define IRQ_BIT(irq_num) (1 << ((irq_num) % 8)) #define IRQ_BIT(irq_num) (1 << ((irq_num) % 8))
#define IRQ_BYTE(irq_num) ((irq_num) / 8) #define IRQ_BYTE(irq_num) ((irq_num) / 8)
#ifdef AUTO_EOI_1
#define ENABLE_ICU1 /* use auto-EOI to reduce i/o */
#define OUTB_ICU1
#else
#define ENABLE_ICU1 \
movb $ICU_EOI,%al ; /* as soon as possible send EOI ... */ \
OUTB_ICU1 /* ... to clear in service bit */
#define OUTB_ICU1 \
FASTER_NOP ; \
outb %al,$IO_ICU1
#endif
#ifdef AUTO_EOI_2 #ifdef AUTO_EOI_2
/* /*
* The data sheet says no auto-EOI on slave, but it sometimes works. * The data sheet says no auto-EOI on slave, but it sometimes works.
*/ */
#define ENABLE_ICU1_AND_2 ENABLE_ICU1 #define ENABLE_ICU2
#else #else
#define ENABLE_ICU1_AND_2 \ #define ENABLE_ICU2 \
movb $ICU_EOI,%al ; /* as above */ \ movb $ICU_EOI,%al ; \
FASTER_NOP ; \ outb %al,$IO_ICU2 ;
outb %al,$IO_ICU2 ; /* but do second icu first ... */ \
OUTB_ICU1 /* ... then first icu (if !AUTO_EOI_1) */
#endif #endif
#ifdef FAST_INTR_HANDLER_USES_ES #ifdef FAST_INTR_HANDLER_USES_ES
@ -174,7 +160,6 @@ IDTVEC(intr/**/irq_num) ; \
movb _imen + IRQ_BYTE(irq_num),%al ; \ movb _imen + IRQ_BYTE(irq_num),%al ; \
orb $IRQ_BIT(irq_num),%al ; \ orb $IRQ_BIT(irq_num),%al ; \
movb %al,_imen + IRQ_BYTE(irq_num) ; \ movb %al,_imen + IRQ_BYTE(irq_num) ; \
FASTER_NOP ; \
outb %al,$icu+1 ; \ outb %al,$icu+1 ; \
enable_icus ; \ enable_icus ; \
incl _cnt+V_INTR ; /* tally interrupts */ \ incl _cnt+V_INTR ; /* tally interrupts */ \
@ -197,7 +182,6 @@ Xresume/**/irq_num: ; \
movb _imen + IRQ_BYTE(irq_num),%al ; \ movb _imen + IRQ_BYTE(irq_num),%al ; \
andb $~IRQ_BIT(irq_num),%al ; \ andb $~IRQ_BIT(irq_num),%al ; \
movb %al,_imen + IRQ_BYTE(irq_num) ; \ movb %al,_imen + IRQ_BYTE(irq_num) ; \
FASTER_NOP ; \
outb %al,$icu+1 ; \ outb %al,$icu+1 ; \
sti ; /* XXX _doreti repeats the cli/sti */ \ sti ; /* XXX _doreti repeats the cli/sti */ \
/* Add this interrupt to the pool of entropy */ \ /* Add this interrupt to the pool of entropy */ \
@ -218,38 +202,38 @@ Xresume/**/irq_num: ; \
iret iret
MCOUNT_LABEL(bintr) MCOUNT_LABEL(bintr)
FAST_INTR(0, ENABLE_ICU1) FAST_INTR(0,)
FAST_INTR(1, ENABLE_ICU1) FAST_INTR(1,)
FAST_INTR(2, ENABLE_ICU1) FAST_INTR(2,)
FAST_INTR(3, ENABLE_ICU1) FAST_INTR(3,)
FAST_INTR(4, ENABLE_ICU1) FAST_INTR(4,)
FAST_INTR(5, ENABLE_ICU1) FAST_INTR(5,)
FAST_INTR(6, ENABLE_ICU1) FAST_INTR(6,)
FAST_INTR(7, ENABLE_ICU1) FAST_INTR(7,)
FAST_INTR(8, ENABLE_ICU1_AND_2) FAST_INTR(8, ENABLE_ICU2)
FAST_INTR(9, ENABLE_ICU1_AND_2) FAST_INTR(9, ENABLE_ICU2)
FAST_INTR(10, ENABLE_ICU1_AND_2) FAST_INTR(10, ENABLE_ICU2)
FAST_INTR(11, ENABLE_ICU1_AND_2) FAST_INTR(11, ENABLE_ICU2)
FAST_INTR(12, ENABLE_ICU1_AND_2) FAST_INTR(12, ENABLE_ICU2)
FAST_INTR(13, ENABLE_ICU1_AND_2) FAST_INTR(13, ENABLE_ICU2)
FAST_INTR(14, ENABLE_ICU1_AND_2) FAST_INTR(14, ENABLE_ICU2)
FAST_INTR(15, ENABLE_ICU1_AND_2) FAST_INTR(15, ENABLE_ICU2)
INTR(0, IO_ICU1, ENABLE_ICU1, al) INTR(0, IO_ICU1,, al)
INTR(1, IO_ICU1, ENABLE_ICU1, al) INTR(1, IO_ICU1,, al)
INTR(2, IO_ICU1, ENABLE_ICU1, al) INTR(2, IO_ICU1,, al)
INTR(3, IO_ICU1, ENABLE_ICU1, al) INTR(3, IO_ICU1,, al)
INTR(4, IO_ICU1, ENABLE_ICU1, al) INTR(4, IO_ICU1,, al)
INTR(5, IO_ICU1, ENABLE_ICU1, al) INTR(5, IO_ICU1,, al)
INTR(6, IO_ICU1, ENABLE_ICU1, al) INTR(6, IO_ICU1,, al)
INTR(7, IO_ICU1, ENABLE_ICU1, al) INTR(7, IO_ICU1,, al)
INTR(8, IO_ICU2, ENABLE_ICU1_AND_2, ah) INTR(8, IO_ICU2, ENABLE_ICU2, ah)
INTR(9, IO_ICU2, ENABLE_ICU1_AND_2, ah) INTR(9, IO_ICU2, ENABLE_ICU2, ah)
INTR(10, IO_ICU2, ENABLE_ICU1_AND_2, ah) INTR(10, IO_ICU2, ENABLE_ICU2, ah)
INTR(11, IO_ICU2, ENABLE_ICU1_AND_2, ah) INTR(11, IO_ICU2, ENABLE_ICU2, ah)
INTR(12, IO_ICU2, ENABLE_ICU1_AND_2, ah) INTR(12, IO_ICU2, ENABLE_ICU2, ah)
INTR(13, IO_ICU2, ENABLE_ICU1_AND_2, ah) INTR(13, IO_ICU2, ENABLE_ICU2, ah)
INTR(14, IO_ICU2, ENABLE_ICU1_AND_2, ah) INTR(14, IO_ICU2, ENABLE_ICU2, ah)
INTR(15, IO_ICU2, ENABLE_ICU1_AND_2, ah) INTR(15, IO_ICU2, ENABLE_ICU2, ah)
MCOUNT_LABEL(eintr) MCOUNT_LABEL(eintr)
.data .data