mirror of
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243 lines
6.4 KiB
C
243 lines
6.4 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (C) 2013 Ganbold Tsagaankhuu <ganbold@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef __IF_EMACREG_H__
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#define __IF_EMACREG_H__
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/*
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* EMAC register definitions
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*/
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#define EMAC_CTL 0x00
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#define EMAC_CTL_RST (1 << 0)
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#define EMAC_CTL_TX_EN (1 << 1)
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#define EMAC_CTL_RX_EN (1 << 2)
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#define EMAC_TX_MODE 0x04
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#define EMAC_TX_FLOW 0x08
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#define EMAC_TX_CTL0 0x0C
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#define EMAC_TX_CTL1 0x10
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#define EMAC_TX_INS 0x14
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#define EMAC_TX_PL0 0x18
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#define EMAC_TX_PL1 0x1C
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#define EMAC_TX_STA 0x20
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#define EMAC_TX_IO_DATA 0x24
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#define EMAC_TX_IO_DATA1 0x28
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#define EMAC_TX_TSVL0 0x2C
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#define EMAC_TX_TSVH0 0x30
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#define EMAC_TX_TSVL1 0x34
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#define EMAC_TX_TSVH1 0x38
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#define EMAC_TX_FIFO0 (1 << 0)
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#define EMAC_TX_FIFO1 (1 << 1)
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#define EMAC_RX_CTL 0x3C
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#define EMAC_RX_HASH0 0x40
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#define EMAC_RX_HASH1 0x44
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#define EMAC_RX_STA 0x48
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#define EMAC_RX_IO_DATA 0x4C
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#define EMAC_RX_FBC 0x50
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#define EMAC_INT_CTL 0x54
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#define EMAC_INT_STA 0x58
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#define EMAC_INT_STA_TX (EMAC_TX_FIFO0 | EMAC_TX_FIFO1)
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#define EMAC_INT_STA_RX 0x100
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#define EMAC_INT_EN (0xf << 0) | (1 << 8)
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#define EMAC_MAC_CTL0 0x5C
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#define EMAC_MAC_CTL1 0x60
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#define EMAC_MAC_IPGT 0x64
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#define EMAC_MAC_IPGR 0x68
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#define EMAC_MAC_CLRT 0x6C
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#define EMAC_MAC_MAXF 0x70
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#define EMAC_MAC_SUPP 0x74
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#define EMAC_MAC_TEST 0x78
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#define EMAC_MAC_MCFG 0x7C
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#define EMAC_MAC_MCMD 0x80
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#define EMAC_MAC_MADR 0x84
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#define EMAC_MAC_MWTD 0x88
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#define EMAC_MAC_MRDD 0x8C
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#define EMAC_MAC_MIND 0x90
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#define EMAC_MAC_SSRR 0x94
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#define EMAC_MAC_A0 0x98
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#define EMAC_MAC_A1 0x9C
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#define EMAC_MAC_A2 0xA0
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#define EMAC_SAFX_L0 0xA4
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#define EMAC_SAFX_H0 0xA8
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#define EMAC_SAFX_L1 0xAC
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#define EMAC_SAFX_H1 0xB0
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#define EMAC_SAFX_L2 0xB4
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#define EMAC_SAFX_H2 0xB8
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#define EMAC_SAFX_L3 0xBC
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#define EMAC_SAFX_H3 0xC0
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#define EMAC_PHY_DUPLEX (1 << 8)
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/*
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* Each received packet has 8 bytes header:
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* Byte 0: Packet valid flag: 0x01 valid, 0x00 not valid
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* Byte 1: 0x43 -> Ascii code 'C'
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* Byte 2: 0x41 -> Ascii code 'A'
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* Byte 3: 0x4d -> Ascii code 'M'
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* Byte 4: High byte of received packet's status
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* Byte 5: Low byte of received packet's status
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* Byte 6: High byte of packet size
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* Byte 7: Low byte of packet size
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*/
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#define EMAC_PACKET_HEADER (0x0143414d)
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/* Aborted frame enable */
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#define EMAC_TX_AB_M (1 << 0)
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/* 0: Enable CPU mode for TX, 1: DMA */
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#define EMAC_TX_TM ~(1 << 1)
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/* 0: DRQ asserted, 1: DRQ automatically */
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#define EMAC_RX_DRQ_MODE (1 << 1)
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/* 0: Enable CPU mode for RX, 1: DMA */
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#define EMAC_RX_TM ~(1 << 2)
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/* Pass all Frames */
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#define EMAC_RX_PA (1 << 4)
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/* Pass Control Frames */
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#define EMAC_RX_PCF (1 << 5)
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/* Pass Frames with CRC Error */
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#define EMAC_RX_PCRCE (1 << 6)
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/* Pass Frames with Length Error */
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#define EMAC_RX_PLE (1 << 7)
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/* Pass Frames length out of range */
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#define EMAC_RX_POR (1 << 8)
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/* Accept unicast Packets */
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#define EMAC_RX_UCAD (1 << 16)
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/* Enable DA Filtering */
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#define EMAC_RX_DAF (1 << 17)
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/* Accept multicast Packets */
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#define EMAC_RX_MCO (1 << 20)
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/* Enable Hash filter */
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#define EMAC_RX_MHF (1 << 21)
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/* Accept Broadcast Packets */
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#define EMAC_RX_BCO (1 << 22)
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/* Enable SA Filtering */
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#define EMAC_RX_SAF (1 << 24)
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/* Inverse Filtering */
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#define EMAC_RX_SAIF (1 << 25)
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#define EMAC_RX_SETUP (EMAC_RX_POR | EMAC_RX_UCAD | \
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EMAC_RX_DAF | EMAC_RX_MCO | EMAC_RX_BCO)
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/* Enable Receive Flow Control */
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#define EMAC_MAC_CTL0_RFC (1 << 2)
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/* Enable Transmit Flow Control */
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#define EMAC_MAC_CTL0_TFC (1 << 3)
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/* Enable soft reset */
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#define EMAC_MAC_CTL0_SOFT_RST (1 << 15)
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#define EMAC_MAC_CTL0_SETUP (EMAC_MAC_CTL0_RFC | EMAC_MAC_CTL0_TFC)
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/* Enable duplex */
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#define EMAC_MAC_CTL1_DUP (1 << 0)
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/* Enable MAC Frame Length Checking */
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#define EMAC_MAC_CTL1_FLC (1 << 1)
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/* Enable Huge Frame */
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#define EMAC_MAC_CTL1_HF (1 << 2)
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/* Enable MAC Delayed CRC */
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#define EMAC_MAC_CTL1_DCRC (1 << 3)
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/* Enable MAC CRC */
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#define EMAC_MAC_CTL1_CRC (1 << 4)
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/* Enable MAC PAD Short frames */
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#define EMAC_MAC_CTL1_PC (1 << 5)
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/* Enable MAC PAD Short frames and append CRC */
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#define EMAC_MAC_CTL1_VC (1 << 6)
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/* Enable MAC auto detect Short frames */
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#define EMAC_MAC_CTL1_ADP (1 << 7)
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#define EMAC_MAC_CTL1_PRE (1 << 8)
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#define EMAC_MAC_CTL1_LPE (1 << 9)
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/* Enable no back off */
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#define EMAC_MAC_CTL1_NB (1 << 12)
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#define EMAC_MAC_CTL1_BNB (1 << 13)
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#define EMAC_MAC_CTL1_ED (1 << 14)
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#define EMAC_MAC_CTL1_SETUP (EMAC_MAC_CTL1_FLC | EMAC_MAC_CTL1_CRC | \
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EMAC_MAC_CTL1_PC)
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/* half duplex */
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#define EMAC_MAC_IPGT_HD 0x12
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/* full duplex */
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#define EMAC_MAC_IPGT_FD 0x15
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#define EMAC_MAC_NBTB_IPG1 0xC
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#define EMAC_MAC_NBTB_IPG2 0x12
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#define EMAC_MAC_CW 0x37
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#define EMAC_MAC_RM 0xF
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#define EMAC_MAC_MFL 0x0600
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/* Receive status */
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#define EMAC_CRCERR (1 << 4)
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#define EMAC_LENERR (3 << 5)
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#define EMAC_PKT_OK (1 << 7)
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#define EMAC_RX_FLUSH_FIFO (1 << 3)
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#define EMAC_PHY_RESET (1 << 15)
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#define EMAC_PHY_PWRDOWN (1 << 11)
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#define EMAC_PROC_MIN 16
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#define EMAC_PROC_MAX 255
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#define EMAC_PROC_DEFAULT 64
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#define EMAC_LOCK(cs) mtx_lock(&(sc)->emac_mtx)
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#define EMAC_UNLOCK(cs) mtx_unlock(&(sc)->emac_mtx)
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#define EMAC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->emac_mtx, MA_OWNED);
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#endif /* __IF_EMACREG_H__ */
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